module Mult(input wire [31:0] AFio, input wire [31:0] BFio, input wire clk,
			output reg [31:0] MultLoFio, output reg [31:0] MultHiFio);
//afio M
//bfio Q

	integer Q_1;
	integer i;
	reg [1:0] temp;
	reg [63:0] A;
	A <= 64'd0;

	Q_1 = 0;
	i = 0;
	always @(posedge clk)
	begin
		if(i<32)
		begin
		temp = {BFio[0], Q_1};
		Q_1 = BFio[0];
		case(temp)
			2'b00:
			begin
				BFio = BFio >>>1;
			end

			2'b11:
			begin
				BFio = BFio >>>1;
			end

			2'b10:
			begin
				A = A - AFio;
				BFio = BFio >>>1;
			end

			2'b01:
			begin
				A = A + AFio;
				BFio = BFio >>>1;
			end

		endcase
		i = i+1;
		end
	end

	MultHiFio = A[63:32];
	MultLoFio = A[31:0;]


endmodule