CLZ in Verilog

always @(posedge i_clk)
    casez(i_input)
    //
    32'b1???_????_????_????_????_????_????_????: clz <= 6'd32;
    32'b01??_????_????_????_????_????_????_????: clz <= 6'd31;
    32'b001?_????_????_????_????_????_????_????: clz <= 6'd30;
    32'b0001_????_????_????_????_????_????_????: clz <= 6'd29;
    //
    32'b0000_1???_????_????_????_????_????_????: clz <= 6'd28;
    32'b0000_01??_????_????_????_????_????_????: clz <= 6'd27;
    32'b0000_001?_????_????_????_????_????_????: clz <= 6'd26;
    32'b0000_0001_????_????_????_????_????_????: clz <= 6'd25;
    //
    32'b0000_0000_1???_????_????_????_????_????: clz <= 6'd24;
    32'b0000_0000_01??_????_????_????_????_????: clz <= 6'd23;
    32'b0000_0000_001?_????_????_????_????_????: clz <= 6'd22;
    32'b0000_0000_0001_????_????_????_????_????: clz <= 6'd21;
    //
    32'b0000_0000_0000_1???_????_????_????_????: clz <= 6'd20;
    32'b0000_0000_0000_01??_????_????_????_????: clz <= 6'd19;
    32'b0000_0000_0000_001?_????_????_????_????: clz <= 6'd18;
    32'b0000_0000_0000_0001_????_????_????_????: clz <= 6'd17;
    //
    32'b0000_0000_0000_0000_1???_????_????_????: clz <= 6'd16;
    32'b0000_0000_0000_0000_01??_????_????_????: clz <= 6'd15;
    32'b0000_0000_0000_0000_001?_????_????_????: clz <= 6'd14;
    32'b0000_0000_0000_0000_0001_????_????_????: clz <= 6'd13;
    //
    32'b0000_0000_0000_0000_0000_1???_????_????: clz <= 6'd12;
    32'b0000_0000_0000_0000_0000_01??_????_????: clz <= 6'd11;
    32'b0000_0000_0000_0000_0000_001?_????_????: clz <= 6'd10;
    32'b0000_0000_0000_0000_0000_0001_????_????: clz <= 6'd09;
    //
    32'b0000_0000_0000_0000_0000_0000_1???_????: clz <= 6'd08;
    32'b0000_0000_0000_0000_0000_0000_01??_????: clz <= 6'd07;
    32'b0000_0000_0000_0000_0000_0000_001?_????: clz <= 6'd06;
    32'b0000_0000_0000_0000_0000_0000_0001_????: clz <= 6'd05;
    //
    32'b0000_0000_0000_0000_0000_0000_0000_1???: clz <= 6'd04;
    32'b0000_0000_0000_0000_0000_0000_0000_01??: clz <= 6'd03;
    32'b0000_0000_0000_0000_0000_0000_0000_001?: clz <= 6'd02;
    32'b0000_0000_0000_0000_0000_0000_0000_0001: clz <= 6'd01;
    //
    default:    clz <= 6'd0;
    endcase