module zad3(
    input [1:0] SW,
    output [0:0]LEDR );

    wire out1;

    D_boolean(~SW[1], SW[0], out1);
    D_boolean(SW[1], out1, LEDR[0]);
endmodule

module D_boolean(Clk, D, Q);
    input Clk, D;
    output Q;
    (* KEEP = "TRUE" *) wire R_g, S_g, Qa, Qb /* synthesis keep */ ;
    assign R_g = ~(~D & Clk);
    assign S_g = ~(D & Clk);
    assign Qa = ~(S_g & Qb);
    assign Qb = ~(R_g & Qa);
    assign Q = Qa;
endmodule