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PipelineWithAxiLiteSlave

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  1. module PipelineWithAxiLiteSlave( // @[:@3.2]
  2.   input         clock, // @[:@4.4]
  3.   input         reset, // @[:@5.4]
  4.   output        io_ctrl_AW_ready, // @[:@6.4]
  5.   input         io_ctrl_AW_valid, // @[:@6.4]
  6.   input  [3:0]  io_ctrl_AW_bits, // @[:@6.4]
  7.   output        io_ctrl_W_ready, // @[:@6.4]
  8.   input         io_ctrl_W_valid, // @[:@6.4]
  9.   input  [31:0] io_ctrl_W_bits_wdata, // @[:@6.4]
  10.   input  [3:0]  io_ctrl_W_bits_wstrb, // @[:@6.4]
  11.   input         io_ctrl_B_ready, // @[:@6.4]
  12.   output        io_ctrl_B_valid, // @[:@6.4]
  13.   output        io_ctrl_AR_ready, // @[:@6.4]
  14.   input         io_ctrl_AR_valid, // @[:@6.4]
  15.   input  [3:0]  io_ctrl_AR_bits, // @[:@6.4]
  16.   input         io_ctrl_R_ready, // @[:@6.4]
  17.   output        io_ctrl_R_valid, // @[:@6.4]
  18.   output [31:0] io_ctrl_R_bits_rdata, // @[:@6.4]
  19.   output [15:0] io_coef, // @[:@6.4]
  20.   input  [31:0] io_stats_nr_samp // @[:@6.4]
  21. );
  22.   reg [15:0] REG_COEF; // @[PipelineWithAxiLiteSlave.scala 48:28:@8.4]
  23.   reg [31:0] _RAND_0;
  24.   reg [1:0] state_wr; // @[PipelineWithAxiLiteSlave.scala 56:25:@10.4]
  25.   reg [31:0] _RAND_1;
  26.   reg  wr_en; // @[PipelineWithAxiLiteSlave.scala 58:20:@11.4]
  27.   reg [31:0] _RAND_2;
  28.   reg [1:0] wr_addr; // @[PipelineWithAxiLiteSlave.scala 59:20:@12.4]
  29.   reg [31:0] _RAND_3;
  30.   reg [31:0] wr_data; // @[PipelineWithAxiLiteSlave.scala 60:20:@13.4]
  31.   reg [31:0] _RAND_4;
  32.   reg [3:0] wr_strb; // @[PipelineWithAxiLiteSlave.scala 61:20:@14.4]
  33.   reg [31:0] _RAND_5;
  34.   wire  _T_65; // @[Conditional.scala 37:30:@16.4]
  35.   wire  _T_66; // @[PipelineWithAxiLiteSlave.scala 69:30:@18.6]
  36.   wire [1:0] _T_68; // @[PipelineWithAxiLiteSlave.scala 71:36:@21.8]
  37.   wire [31:0] _GEN_0; // @[PipelineWithAxiLiteSlave.scala 78:37:@34.10]
  38.   wire [3:0] _GEN_1; // @[PipelineWithAxiLiteSlave.scala 78:37:@34.10]
  39.   wire [1:0] _GEN_2; // @[PipelineWithAxiLiteSlave.scala 78:37:@34.10]
  40.   wire [1:0] _GEN_3; // @[PipelineWithAxiLiteSlave.scala 75:38:@28.8]
  41.   wire [1:0] _GEN_4; // @[PipelineWithAxiLiteSlave.scala 75:38:@28.8]
  42.   wire [31:0] _GEN_5; // @[PipelineWithAxiLiteSlave.scala 75:38:@28.8]
  43.   wire [3:0] _GEN_6; // @[PipelineWithAxiLiteSlave.scala 75:38:@28.8]
  44.   wire [1:0] _GEN_8; // @[PipelineWithAxiLiteSlave.scala 69:50:@19.6]
  45.   wire [31:0] _GEN_9; // @[PipelineWithAxiLiteSlave.scala 69:50:@19.6]
  46.   wire [3:0] _GEN_10; // @[PipelineWithAxiLiteSlave.scala 69:50:@19.6]
  47.   wire [1:0] _GEN_11; // @[PipelineWithAxiLiteSlave.scala 69:50:@19.6]
  48.   wire  _T_70; // @[Conditional.scala 37:30:@41.6]
  49.   wire [1:0] _GEN_13; // @[PipelineWithAxiLiteSlave.scala 85:30:@43.8]
  50.   wire  _T_72; // @[Conditional.scala 37:30:@51.8]
  51.   wire [1:0] _GEN_16; // @[PipelineWithAxiLiteSlave.scala 93:31:@53.10]
  52.   wire  _T_75; // @[Conditional.scala 37:30:@61.10]
  53.   wire [1:0] _GEN_17; // @[PipelineWithAxiLiteSlave.scala 100:30:@63.12]
  54.   wire [1:0] _GEN_18; // @[Conditional.scala 39:67:@62.10]
  55.   wire  _GEN_19; // @[Conditional.scala 39:67:@52.8]
  56.   wire [1:0] _GEN_20; // @[Conditional.scala 39:67:@52.8]
  57.   wire [1:0] _GEN_21; // @[Conditional.scala 39:67:@52.8]
  58.   wire  _GEN_22; // @[Conditional.scala 39:67:@42.6]
  59.   wire [31:0] _GEN_23; // @[Conditional.scala 39:67:@42.6]
  60.   wire [3:0] _GEN_24; // @[Conditional.scala 39:67:@42.6]
  61.   wire [1:0] _GEN_25; // @[Conditional.scala 39:67:@42.6]
  62.   wire [1:0] _GEN_26; // @[Conditional.scala 39:67:@42.6]
  63.   wire [1:0] _GEN_31; // @[Conditional.scala 40:58:@17.4]
  64.   wire  _GEN_36; // @[Conditional.scala 39:67:@85.8]
  65.   wire  _GEN_38; // @[Conditional.scala 39:67:@78.6]
  66.   wire  _GEN_39; // @[Conditional.scala 39:67:@78.6]
  67.   wire  _T_97; // @[Conditional.scala 37:30:@100.6]
  68.   wire [3:0] _T_107; // @[PipelineWithAxiLiteSlave.scala 145:21:@103.8]
  69.   wire  _T_109; // @[PipelineWithAxiLiteSlave.scala 145:35:@104.8]
  70.   wire [7:0] _T_110; // @[PipelineWithAxiLiteSlave.scala 146:23:@106.10]
  71.   wire [7:0] _T_111; // @[PipelineWithAxiLiteSlave.scala 148:23:@110.10]
  72.   wire [7:0] _GEN_43; // @[PipelineWithAxiLiteSlave.scala 145:44:@105.8]
  73.   wire [3:0] _T_113; // @[PipelineWithAxiLiteSlave.scala 145:21:@113.8]
  74.   wire  _T_115; // @[PipelineWithAxiLiteSlave.scala 145:35:@114.8]
  75.   wire [7:0] _T_116; // @[PipelineWithAxiLiteSlave.scala 146:23:@116.10]
  76.   wire [7:0] _T_117; // @[PipelineWithAxiLiteSlave.scala 148:23:@120.10]
  77.   wire [7:0] _GEN_44; // @[PipelineWithAxiLiteSlave.scala 145:44:@115.8]
  78.   wire [15:0] _T_118; // @[PipelineWithAxiLiteSlave.scala 152:15:@123.8]
  79.   wire [15:0] _GEN_45; // @[Conditional.scala 40:58:@101.6]
  80.   wire [15:0] _GEN_46; // @[PipelineWithAxiLiteSlave.scala 155:16:@99.4]
  81.   reg [1:0] state_rd; // @[PipelineWithAxiLiteSlave.scala 165:25:@127.4]
  82.   reg [31:0] _RAND_6;
  83.   reg  rd_en; // @[PipelineWithAxiLiteSlave.scala 167:20:@128.4]
  84.   reg [31:0] _RAND_7;
  85.   reg [1:0] rd_addr; // @[PipelineWithAxiLiteSlave.scala 168:20:@129.4]
  86.   reg [31:0] _RAND_8;
  87.   reg [33:0] rd_data; // @[PipelineWithAxiLiteSlave.scala 169:20:@130.4]
  88.   reg [63:0] _RAND_9;
  89.   wire  _T_124; // @[Conditional.scala 37:30:@132.4]
  90.   wire [1:0] _T_126; // @[PipelineWithAxiLiteSlave.scala 178:36:@136.8]
  91.   wire [1:0] _GEN_48; // @[PipelineWithAxiLiteSlave.scala 176:31:@134.6]
  92.   wire [1:0] _GEN_49; // @[PipelineWithAxiLiteSlave.scala 176:31:@134.6]
  93.   wire  _T_127; // @[Conditional.scala 37:30:@142.6]
  94.   wire  _T_128; // @[Conditional.scala 37:30:@147.8]
  95.   wire [1:0] _GEN_50; // @[PipelineWithAxiLiteSlave.scala 186:30:@149.10]
  96.   wire [1:0] _GEN_51; // @[Conditional.scala 39:67:@148.8]
  97.   wire [1:0] _GEN_52; // @[Conditional.scala 39:67:@143.6]
  98.   wire [1:0] _GEN_55; // @[Conditional.scala 40:58:@133.4]
  99.   wire [33:0] _GEN_58; // @[Conditional.scala 39:67:@171.8]
  100.   wire  _GEN_60; // @[Conditional.scala 39:67:@164.6]
  101.   wire [33:0] _GEN_61; // @[Conditional.scala 39:67:@164.6]
  102.   wire [33:0] _GEN_64; // @[Conditional.scala 40:58:@157.4]
  103.   wire  _T_143; // @[Conditional.scala 37:30:@177.6]
  104.   wire  _T_144; // @[Conditional.scala 37:30:@182.8]
  105.   wire  _T_145; // @[Conditional.scala 37:30:@187.10]
  106.   wire  _T_146; // @[Conditional.scala 37:30:@192.12]
  107.   wire [33:0] _GEN_65; // @[Conditional.scala 39:67:@193.12]
  108.   wire [33:0] _GEN_66; // @[Conditional.scala 39:67:@188.10]
  109.   wire [33:0] _GEN_67; // @[Conditional.scala 39:67:@183.8]
  110.   wire [33:0] _GEN_68; // @[Conditional.scala 40:58:@178.6]
  111.   assign _T_65 = 2'h0 == state_wr; // @[Conditional.scala 37:30:@16.4]
  112.   assign _T_66 = io_ctrl_AW_valid & io_ctrl_W_valid; // @[PipelineWithAxiLiteSlave.scala 69:30:@18.6]
  113.   assign _T_68 = io_ctrl_AW_bits[3:2]; // @[PipelineWithAxiLiteSlave.scala 71:36:@21.8]
  114.   assign _GEN_0 = io_ctrl_W_valid ? io_ctrl_W_bits_wdata : wr_data; // @[PipelineWithAxiLiteSlave.scala 78:37:@34.10]
  115.   assign _GEN_1 = io_ctrl_W_valid ? io_ctrl_W_bits_wstrb : wr_strb; // @[PipelineWithAxiLiteSlave.scala 78:37:@34.10]
  116.   assign _GEN_2 = io_ctrl_W_valid ? 2'h2 : state_wr; // @[PipelineWithAxiLiteSlave.scala 78:37:@34.10]
  117.   assign _GEN_3 = io_ctrl_AW_valid ? _T_68 : wr_addr; // @[PipelineWithAxiLiteSlave.scala 75:38:@28.8]
  118.   assign _GEN_4 = io_ctrl_AW_valid ? 2'h1 : _GEN_2; // @[PipelineWithAxiLiteSlave.scala 75:38:@28.8]
  119.   assign _GEN_5 = io_ctrl_AW_valid ? wr_data : _GEN_0; // @[PipelineWithAxiLiteSlave.scala 75:38:@28.8]
  120.   assign _GEN_6 = io_ctrl_AW_valid ? wr_strb : _GEN_1; // @[PipelineWithAxiLiteSlave.scala 75:38:@28.8]
  121.   assign _GEN_8 = _T_66 ? _T_68 : _GEN_3; // @[PipelineWithAxiLiteSlave.scala 69:50:@19.6]
  122.   assign _GEN_9 = _T_66 ? io_ctrl_W_bits_wdata : _GEN_5; // @[PipelineWithAxiLiteSlave.scala 69:50:@19.6]
  123.   assign _GEN_10 = _T_66 ? io_ctrl_W_bits_wstrb : _GEN_6; // @[PipelineWithAxiLiteSlave.scala 69:50:@19.6]
  124.   assign _GEN_11 = _T_66 ? 2'h3 : _GEN_4; // @[PipelineWithAxiLiteSlave.scala 69:50:@19.6]
  125.   assign _T_70 = 2'h1 == state_wr; // @[Conditional.scala 37:30:@41.6]
  126.   assign _GEN_13 = io_ctrl_W_valid ? 2'h3 : state_wr; // @[PipelineWithAxiLiteSlave.scala 85:30:@43.8]
  127.   assign _T_72 = 2'h2 == state_wr; // @[Conditional.scala 37:30:@51.8]
  128.   assign _GEN_16 = io_ctrl_AW_valid ? 2'h3 : state_wr; // @[PipelineWithAxiLiteSlave.scala 93:31:@53.10]
  129.   assign _T_75 = 2'h3 == state_wr; // @[Conditional.scala 37:30:@61.10]
  130.   assign _GEN_17 = io_ctrl_B_ready ? 2'h0 : state_wr; // @[PipelineWithAxiLiteSlave.scala 100:30:@63.12]
  131.   assign _GEN_18 = _T_75 ? _GEN_17 : state_wr; // @[Conditional.scala 39:67:@62.10]
  132.   assign _GEN_19 = _T_72 ? io_ctrl_AW_valid : 1'h0; // @[Conditional.scala 39:67:@52.8]
  133.   assign _GEN_20 = _T_72 ? _GEN_3 : wr_addr; // @[Conditional.scala 39:67:@52.8]
  134.   assign _GEN_21 = _T_72 ? _GEN_16 : _GEN_18; // @[Conditional.scala 39:67:@52.8]
  135.   assign _GEN_22 = _T_70 ? io_ctrl_W_valid : _GEN_19; // @[Conditional.scala 39:67:@42.6]
  136.   assign _GEN_23 = _T_70 ? _GEN_0 : wr_data; // @[Conditional.scala 39:67:@42.6]
  137.   assign _GEN_24 = _T_70 ? _GEN_1 : wr_strb; // @[Conditional.scala 39:67:@42.6]
  138.   assign _GEN_25 = _T_70 ? _GEN_13 : _GEN_21; // @[Conditional.scala 39:67:@42.6]
  139.   assign _GEN_26 = _T_70 ? wr_addr : _GEN_20; // @[Conditional.scala 39:67:@42.6]
  140.   assign _GEN_31 = _T_65 ? _GEN_11 : _GEN_25; // @[Conditional.scala 40:58:@17.4]
  141.   assign _GEN_36 = _T_70 ? 1'h0 : _T_75; // @[Conditional.scala 39:67:@85.8]
  142.   assign _GEN_38 = _T_72 ? 1'h0 : _T_70; // @[Conditional.scala 39:67:@78.6]
  143.   assign _GEN_39 = _T_72 ? 1'h0 : _GEN_36; // @[Conditional.scala 39:67:@78.6]
  144.   assign _T_97 = 2'h3 == wr_addr; // @[Conditional.scala 37:30:@100.6]
  145.   assign _T_107 = wr_strb & 4'h1; // @[PipelineWithAxiLiteSlave.scala 145:21:@103.8]
  146.   assign _T_109 = _T_107 != 4'h0; // @[PipelineWithAxiLiteSlave.scala 145:35:@104.8]
  147.   assign _T_110 = wr_data[7:0]; // @[PipelineWithAxiLiteSlave.scala 146:23:@106.10]
  148.   assign _T_111 = REG_COEF[7:0]; // @[PipelineWithAxiLiteSlave.scala 148:23:@110.10]
  149.   assign _GEN_43 = _T_109 ? _T_110 : _T_111; // @[PipelineWithAxiLiteSlave.scala 145:44:@105.8]
  150.   assign _T_113 = wr_strb & 4'h2; // @[PipelineWithAxiLiteSlave.scala 145:21:@113.8]
  151.   assign _T_115 = _T_113 != 4'h0; // @[PipelineWithAxiLiteSlave.scala 145:35:@114.8]
  152.   assign _T_116 = wr_data[15:8]; // @[PipelineWithAxiLiteSlave.scala 146:23:@116.10]
  153.   assign _T_117 = REG_COEF[15:8]; // @[PipelineWithAxiLiteSlave.scala 148:23:@120.10]
  154.   assign _GEN_44 = _T_115 ? _T_116 : _T_117; // @[PipelineWithAxiLiteSlave.scala 145:44:@115.8]
  155.   assign _T_118 = {_GEN_44,_GEN_43}; // @[PipelineWithAxiLiteSlave.scala 152:15:@123.8]
  156.   assign _GEN_45 = _T_97 ? _T_118 : REG_COEF; // @[Conditional.scala 40:58:@101.6]
  157.   assign _GEN_46 = wr_en ? _GEN_45 : REG_COEF; // @[PipelineWithAxiLiteSlave.scala 155:16:@99.4]
  158.   assign _T_124 = 2'h0 == state_rd; // @[Conditional.scala 37:30:@132.4]
  159.   assign _T_126 = io_ctrl_AR_bits[3:2]; // @[PipelineWithAxiLiteSlave.scala 178:36:@136.8]
  160.   assign _GEN_48 = io_ctrl_AR_valid ? _T_126 : rd_addr; // @[PipelineWithAxiLiteSlave.scala 176:31:@134.6]
  161.   assign _GEN_49 = io_ctrl_AR_valid ? 2'h1 : state_rd; // @[PipelineWithAxiLiteSlave.scala 176:31:@134.6]
  162.   assign _T_127 = 2'h1 == state_rd; // @[Conditional.scala 37:30:@142.6]
  163.   assign _T_128 = 2'h2 == state_rd; // @[Conditional.scala 37:30:@147.8]
  164.   assign _GEN_50 = io_ctrl_R_ready ? 2'h0 : state_rd; // @[PipelineWithAxiLiteSlave.scala 186:30:@149.10]
  165.   assign _GEN_51 = _T_128 ? _GEN_50 : state_rd; // @[Conditional.scala 39:67:@148.8]
  166.   assign _GEN_52 = _T_127 ? 2'h2 : _GEN_51; // @[Conditional.scala 39:67:@143.6]
  167.   assign _GEN_55 = _T_124 ? _GEN_49 : _GEN_52; // @[Conditional.scala 40:58:@133.4]
  168.   assign _GEN_58 = _T_128 ? rd_data : 34'h0; // @[Conditional.scala 39:67:@171.8]
  169.   assign _GEN_60 = _T_127 ? 1'h0 : _T_128; // @[Conditional.scala 39:67:@164.6]
  170.   assign _GEN_61 = _T_127 ? 34'h0 : _GEN_58; // @[Conditional.scala 39:67:@164.6]
  171.   assign _GEN_64 = _T_124 ? 34'h0 : _GEN_61; // @[Conditional.scala 40:58:@157.4]
  172.   assign _T_143 = 2'h0 == rd_addr; // @[Conditional.scala 37:30:@177.6]
  173.   assign _T_144 = 2'h1 == rd_addr; // @[Conditional.scala 37:30:@182.8]
  174.   assign _T_145 = 2'h2 == rd_addr; // @[Conditional.scala 37:30:@187.10]
  175.   assign _T_146 = 2'h3 == rd_addr; // @[Conditional.scala 37:30:@192.12]
  176.   assign _GEN_65 = _T_146 ? {{18'd0}, REG_COEF} : rd_data; // @[Conditional.scala 39:67:@193.12]
  177.   assign _GEN_66 = _T_145 ? {{2'd0}, io_stats_nr_samp} : _GEN_65; // @[Conditional.scala 39:67:@188.10]
  178.   assign _GEN_67 = _T_144 ? 34'h10000 : _GEN_66; // @[Conditional.scala 39:67:@183.8]
  179.   assign _GEN_68 = _T_143 ? 34'h71711123 : _GEN_67; // @[Conditional.scala 40:58:@178.6]
  180.   assign io_ctrl_AW_ready = _T_65 ? 1'h1 : _T_72; // @[PipelineWithAxiLiteSlave.scala 108:20:@67.4 PipelineWithAxiLiteSlave.scala 114:24:@72.6 PipelineWithAxiLiteSlave.scala 119:24:@79.8 PipelineWithAxiLiteSlave.scala 124:24:@86.10 PipelineWithAxiLiteSlave.scala 129:24:@93.12]
  181.   assign io_ctrl_W_ready = _T_65 ? 1'h1 : _GEN_38; // @[PipelineWithAxiLiteSlave.scala 109:20:@68.4 PipelineWithAxiLiteSlave.scala 115:24:@73.6 PipelineWithAxiLiteSlave.scala 120:24:@80.8 PipelineWithAxiLiteSlave.scala 125:24:@87.10 PipelineWithAxiLiteSlave.scala 130:24:@94.12]
  182.   assign io_ctrl_B_valid = _T_65 ? 1'h0 : _GEN_39; // @[PipelineWithAxiLiteSlave.scala 110:20:@69.4 PipelineWithAxiLiteSlave.scala 116:24:@74.6 PipelineWithAxiLiteSlave.scala 121:24:@81.8 PipelineWithAxiLiteSlave.scala 126:24:@88.10 PipelineWithAxiLiteSlave.scala 131:24:@95.12]
  183.   assign io_ctrl_AR_ready = 2'h0 == state_rd; // @[PipelineWithAxiLiteSlave.scala 192:24:@153.4 PipelineWithAxiLiteSlave.scala 198:28:@158.6 PipelineWithAxiLiteSlave.scala 203:28:@165.8 PipelineWithAxiLiteSlave.scala 208:28:@172.10]
  184.   assign io_ctrl_R_valid = _T_124 ? 1'h0 : _GEN_60; // @[PipelineWithAxiLiteSlave.scala 193:24:@154.4 PipelineWithAxiLiteSlave.scala 199:28:@159.6 PipelineWithAxiLiteSlave.scala 204:28:@166.8 PipelineWithAxiLiteSlave.scala 209:28:@173.10]
  185.   assign io_ctrl_R_bits_rdata = _GEN_64[31:0]; // @[PipelineWithAxiLiteSlave.scala 194:24:@155.4 PipelineWithAxiLiteSlave.scala 200:28:@160.6 PipelineWithAxiLiteSlave.scala 205:28:@167.8 PipelineWithAxiLiteSlave.scala 210:28:@174.10]
  186.   assign io_coef = REG_COEF; // @[PipelineWithAxiLiteSlave.scala 50:11:@9.4]
  187. `ifdef RANDOMIZE_GARBAGE_ASSIGN
  188. `define RANDOMIZE
  189. `endif
  190. `ifdef RANDOMIZE_INVALID_ASSIGN
  191. `define RANDOMIZE
  192. `endif
  193. `ifdef RANDOMIZE_REG_INIT
  194. `define RANDOMIZE
  195. `endif
  196. `ifdef RANDOMIZE_MEM_INIT
  197. `define RANDOMIZE
  198. `endif
  199. `ifndef RANDOM
  200. `define RANDOM $random
  201. `endif
  202. `ifdef RANDOMIZE
  203.   integer initvar;
  204.   initial begin
  205.     `ifdef INIT_RANDOM
  206.       `INIT_RANDOM
  207.     `endif
  208.     `ifndef VERILATOR
  209.       #0.002 begin end
  210.     `endif
  211.   `ifdef RANDOMIZE_REG_INIT
  212.   _RAND_0 = {1{`RANDOM}};
  213.   REG_COEF = _RAND_0[15:0];
  214.   `endif // RANDOMIZE_REG_INIT
  215.   `ifdef RANDOMIZE_REG_INIT
  216.   _RAND_1 = {1{`RANDOM}};
  217.   state_wr = _RAND_1[1:0];
  218.   `endif // RANDOMIZE_REG_INIT
  219.   `ifdef RANDOMIZE_REG_INIT
  220.   _RAND_2 = {1{`RANDOM}};
  221.   wr_en = _RAND_2[0:0];
  222.   `endif // RANDOMIZE_REG_INIT
  223.   `ifdef RANDOMIZE_REG_INIT
  224.   _RAND_3 = {1{`RANDOM}};
  225.   wr_addr = _RAND_3[1:0];
  226.   `endif // RANDOMIZE_REG_INIT
  227.   `ifdef RANDOMIZE_REG_INIT
  228.   _RAND_4 = {1{`RANDOM}};
  229.   wr_data = _RAND_4[31:0];
  230.   `endif // RANDOMIZE_REG_INIT
  231.   `ifdef RANDOMIZE_REG_INIT
  232.   _RAND_5 = {1{`RANDOM}};
  233.   wr_strb = _RAND_5[3:0];
  234.   `endif // RANDOMIZE_REG_INIT
  235.   `ifdef RANDOMIZE_REG_INIT
  236.   _RAND_6 = {1{`RANDOM}};
  237.   state_rd = _RAND_6[1:0];
  238.   `endif // RANDOMIZE_REG_INIT
  239.   `ifdef RANDOMIZE_REG_INIT
  240.   _RAND_7 = {1{`RANDOM}};
  241.   rd_en = _RAND_7[0:0];
  242.   `endif // RANDOMIZE_REG_INIT
  243.   `ifdef RANDOMIZE_REG_INIT
  244.   _RAND_8 = {1{`RANDOM}};
  245.   rd_addr = _RAND_8[1:0];
  246.   `endif // RANDOMIZE_REG_INIT
  247.   `ifdef RANDOMIZE_REG_INIT
  248.   _RAND_9 = {2{`RANDOM}};
  249.   rd_data = _RAND_9[33:0];
  250.   `endif // RANDOMIZE_REG_INIT
  251.   end
  252. `endif // RANDOMIZE
  253.   always @(posedge clock) begin
  254.     if (reset) begin
  255.       REG_COEF <= 16'h0;
  256.     end else begin
  257.       if (wr_en) begin
  258.         if (_T_97) begin
  259.           REG_COEF <= _T_118;
  260.         end
  261.       end
  262.     end
  263.     if (reset) begin
  264.       state_wr <= 2'h0;
  265.     end else begin
  266.       if (_T_65) begin
  267.         if (_T_66) begin
  268.           state_wr <= 2'h3;
  269.         end else begin
  270.           if (io_ctrl_AW_valid) begin
  271.             state_wr <= 2'h1;
  272.           end else begin
  273.             if (io_ctrl_W_valid) begin
  274.               state_wr <= 2'h2;
  275.             end
  276.           end
  277.         end
  278.       end else begin
  279.         if (_T_70) begin
  280.           if (io_ctrl_W_valid) begin
  281.             state_wr <= 2'h3;
  282.           end
  283.         end else begin
  284.           if (_T_72) begin
  285.             if (io_ctrl_AW_valid) begin
  286.               state_wr <= 2'h3;
  287.             end
  288.           end else begin
  289.             if (_T_75) begin
  290.               if (io_ctrl_B_ready) begin
  291.                 state_wr <= 2'h0;
  292.               end
  293.             end
  294.           end
  295.         end
  296.       end
  297.     end
  298.     if (_T_65) begin
  299.       wr_en <= _T_66;
  300.     end else begin
  301.       if (_T_70) begin
  302.         wr_en <= io_ctrl_W_valid;
  303.       end else begin
  304.         if (_T_72) begin
  305.           wr_en <= io_ctrl_AW_valid;
  306.         end else begin
  307.           wr_en <= 1'h0;
  308.         end
  309.       end
  310.     end
  311.     if (_T_65) begin
  312.       if (_T_66) begin
  313.         wr_addr <= _T_68;
  314.       end else begin
  315.         if (io_ctrl_AW_valid) begin
  316.           wr_addr <= _T_68;
  317.         end
  318.       end
  319.     end else begin
  320.       if (!(_T_70)) begin
  321.         if (_T_72) begin
  322.           if (io_ctrl_AW_valid) begin
  323.             wr_addr <= _T_68;
  324.           end
  325.         end
  326.       end
  327.     end
  328.     if (_T_65) begin
  329.       if (_T_66) begin
  330.         wr_data <= io_ctrl_W_bits_wdata;
  331.       end else begin
  332.         if (!(io_ctrl_AW_valid)) begin
  333.           if (io_ctrl_W_valid) begin
  334.             wr_data <= io_ctrl_W_bits_wdata;
  335.           end
  336.         end
  337.       end
  338.     end else begin
  339.       if (_T_70) begin
  340.         if (io_ctrl_W_valid) begin
  341.           wr_data <= io_ctrl_W_bits_wdata;
  342.         end
  343.       end
  344.     end
  345.     if (_T_65) begin
  346.       if (_T_66) begin
  347.         wr_strb <= io_ctrl_W_bits_wstrb;
  348.       end else begin
  349.         if (!(io_ctrl_AW_valid)) begin
  350.           if (io_ctrl_W_valid) begin
  351.             wr_strb <= io_ctrl_W_bits_wstrb;
  352.           end
  353.         end
  354.       end
  355.     end else begin
  356.       if (_T_70) begin
  357.         if (io_ctrl_W_valid) begin
  358.           wr_strb <= io_ctrl_W_bits_wstrb;
  359.         end
  360.       end
  361.     end
  362.     if (reset) begin
  363.       state_rd <= 2'h0;
  364.     end else begin
  365.       if (_T_124) begin
  366.         if (io_ctrl_AR_valid) begin
  367.           state_rd <= 2'h1;
  368.         end
  369.       end else begin
  370.         if (_T_127) begin
  371.           state_rd <= 2'h2;
  372.         end else begin
  373.           if (_T_128) begin
  374.             if (io_ctrl_R_ready) begin
  375.               state_rd <= 2'h0;
  376.             end
  377.           end
  378.         end
  379.       end
  380.     end
  381.     if (_T_124) begin
  382.       rd_en <= io_ctrl_AR_valid;
  383.     end else begin
  384.       rd_en <= 1'h0;
  385.     end
  386.     if (_T_124) begin
  387.       if (io_ctrl_AR_valid) begin
  388.         rd_addr <= _T_126;
  389.       end
  390.     end
  391.     if (rd_en) begin
  392.       if (_T_143) begin
  393.         rd_data <= 34'h71711123;
  394.       end else begin
  395.         if (_T_144) begin
  396.           rd_data <= 34'h10000;
  397.         end else begin
  398.           if (_T_145) begin
  399.             rd_data <= {{2'd0}, io_stats_nr_samp};
  400.           end else begin
  401.             if (_T_146) begin
  402.               rd_data <= {{18'd0}, REG_COEF};
  403.             end
  404.           end
  405.         end
  406.       end
  407.     end
  408.   end
  409. endmodule
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