`define NO_OP 2'b00
`define PUSH1 2'b01
`define POP   2'b10

`define PUSH2 3'b000
`define ADD   3'b001
`define SUB   3'b010
`define MUL   3'b011
`define COM   3'b100
`define PUSHANS 3'b101
`define READCOM 3'b110
`define INIT  3'b111



module DFF (clk, next_out, out);
  parameter n = 1;
  input clk;
  input [n-1:0] next_out;
  output reg [n-1:0] out;
  always@(posedge clk) begin
      out <= next_out;
  end
endmodule


module SM(clk, rst_n, instr, pc, d_valid, out_data, err_code, fin);
    input clk;
    input rst_n;
    input [12:0] instr;
    output [9:0] pc;
    output d_valid;
    output signed [19:0] out_data;
    output reg [2:0] err_code;
    output fin;
    wire [9:0]  next_pc;
    wire [2:0]  com,com_next;
    wire signed [19:0] w_data, r_data;
    wire [1:0]  cntrl;
    wire full,empty;
    reg  [9:0]  next_pc1;
    reg  [2:0]  com_next1,last;
    reg  [12:0] num;
    reg  [1:0]  cntrl_next;
    reg  signed [19:0] temp1,temp2,out_next,w_data1;
    reg  fin1,d_next1;
    wire [4:0] true_num,num_next;
    reg  [4:0] stack_num;
    DFF #(10) DFF0(clk, next_pc, pc);
    DFF #(3) DFF1(clk, com_next, com);
    DFF #(5) DFF2(clk,num_next,true_num);
    SM_Mem SM0(clk, rst_n, cntrl_next, w_data1, r_data, full, empty);

    always@(*) begin
        next_pc1 = pc;
        com_next1 = com;
        d_next1 = 10'd0;
        stack_num = true_num;
        //out_next = out_data;
        fin1 = fin;

        case(com)
            `INIT: begin
                cntrl_next = `NO_OP;
                next_pc1 = next_pc1 + 10'd1;
                d_next1 = 10'd0;
                w_data1 = 0;
                err_code = 3'b000;
                out_next = 0;
                stack_num = 0;
                com_next1 = `READCOM;   //it's a big fault
            end
            `READCOM: begin
                cntrl_next = `NO_OP;
                w_data1 = 0;
                if(instr[12:10] == 3'b100) begin
                    d_next1 = 1;
                    out_next = 0;
                    err_code = 3'b010;
                    next_pc1 = next_pc1 + 10'd1;
                    com_next1 = `READCOM;
                end
                else if(instr[12:10] == 3'b101) begin
                    d_next1 = 1;
                    out_next = 0;
                    err_code = 3'b010;
                    next_pc1 = next_pc1 + 10'd1;
                    com_next1 = `READCOM;
                end
                else if(instr[12:10] == 3'b110) begin
                    d_next1 = 1;
                    out_next = 0;
                    err_code = 3'b010;
                    next_pc1 = next_pc1 + 10'd1;
                    com_next1 = `READCOM;
                end
                else if(instr[12:10] == 3'b111) begin
                    d_next1 = 1;
                    out_next = 0;
                    err_code = 3'b010;
                    next_pc1 = next_pc1 + 10'd1;
                    com_next1 = `READCOM;
                end
                else begin//*/
                    d_next1 = 10'd0;
                    err_code = 3'b000;
                    out_next = 0;
                    com_next1 = instr[12:10];
               end
                w_data1 = 10'd0;
                //next_pc1 = next_pc1 + 10'd1;
            end
            `PUSH2: begin
                 out_next = 0;
                if(true_num < 8) begin
                    cntrl_next = `PUSH1;
                    err_code = 3'b000;
                    w_data1 = instr[9:0];
                    next_pc1 = next_pc1 + 10'd1;
                    d_next1 = 10'd0;
                    stack_num = stack_num + 1;
                    com_next1 = `READCOM;
                end
                else begin
                    d_next1 = 1;
                    cntrl_next = `NO_OP;
                    err_code = 3'b001;
                    next_pc1 = next_pc1 + 10'd1;
                    com_next1 = `READCOM;
                end
            end
            `ADD: begin//1
                out_next = 0;
                w_data1 = 0;
                if(stack_num >= 2) begin
                    cntrl_next = `POP;
                    err_code = 3'b000;
                    temp1 = r_data;
                    last = `ADD;
                    com_next1 = `COM;
                    d_next1 = 10'd0;
                end
                else begin
                    d_next1 = 1;
                    cntrl_next = `NO_OP;
                    err_code = 3'b100;
                    next_pc1 = next_pc1 + 10'd1;
                    com_next1 = `READCOM;
                end
                //next_pc1 = next_pc1 + 10'd1;
            end
            `SUB: begin//2
                 out_next = 0;
                 w_data1 = 0;
                if(stack_num >= 2) begin
                    cntrl_next = `POP;
                    err_code = 3'b000;
                    temp1 = r_data;
                    last = `SUB;
                    com_next1 = `COM;
                    d_next1 = 10'd0;
                end
                else begin
                    d_next1 = 1;
                    //out_next = 0;
                    cntrl_next = `NO_OP;
                    err_code = 3'b100;
                    next_pc1 = next_pc1 + 10'd1;
                    com_next1 = `READCOM;
                end
                //next_pc1 = next_pc1 + 10'd1;
            end
            `MUL: begin//3
                 out_next = 0;
                 w_data1 = 0;
                if(stack_num >= 2) begin
                    cntrl_next = `POP;
                    err_code = 3'b000;
                    temp1 = r_data;
                    last = `MUL;
                    com_next1 = `COM;
                    d_next1 = 10'd0;
                end
                else begin
                    d_next1 = 1;
                    //out_next = 0;
                    cntrl_next = `NO_OP;
                    err_code = 3'b100;
                    next_pc1 = next_pc1 + 10'd1;
                    com_next1 = `READCOM;
                end
                //next_pc1 = next_pc1 + 10'd1;
            end
            `COM: begin
                cntrl_next = `POP;
                err_code = 3'b000;
                out_next = 0;
                w_data1 = 0;
                d_next1 = 10'd0;
                temp2 = r_data;
                com_next1 = `PUSHANS;
                stack_num = stack_num - 1;

            end
            `PUSHANS: begin
                cntrl_next = `PUSH1;
                err_code = 3'b000;
                d_next1 = 10'd1;
                next_pc1 = next_pc1 + 10'd1;
                com_next1 = `READCOM;

                if(instr[12:10] == `ADD) begin
                    out_next = temp1 + temp2;
                    w_data1 = temp1 +temp2;
                end
                else if(instr[12:10] == `SUB) begin
                    out_next = temp1 - temp2;
                    w_data1 = temp1 - temp2;
                end
                else if(instr[12:10] == `MUL)  begin
                    out_next = temp1 * temp2;
                   w_data1 = temp1 * temp2;
                end
                else begin end
            end
            default: begin
                out_next = 0;
            end
        endcase
        if(pc == 10'd1023) begin
            num = instr[9:0];
        end
        else begin end
        fin1 = (pc == num)? 10'd1: 10'd0;
        //d_next1 = (fin1 == 10'd1)? 10'd1: d_next1;
    end
   // assign w_data = (rst_n == 10'd0)? 10'd0: w_data1;
    //assign cntrl = (rst_n == 10'd0)? `NO_OP: cntrl_next;
    assign next_pc = (rst_n == 10'd0)? 10'd1023: next_pc1;
    assign fin = (rst_n == 10'd0)? 10'd0: fin1;
    assign com_next = (rst_n == 10'd0)? `INIT: com_next1;
    assign d_valid = (rst_n == 10'd0)? 10'd0: d_next1;
    assign out_data = (rst_n == 10'd0)? 10'd0: out_next;
    assign num_next = (rst_n == 0)? 0: stack_num;
    // your code here, remember to instantiate your SM_Mem
endmodule
module SM_Mem(clk, rst_n, cntrl, w_data, r_data, full, empty);
    input clk;
    input rst_n;
    input [1:0] cntrl;
    input signed[19:0] w_data;
    output signed [19:0] r_data;
    output reg full;
    output reg empty;
    reg signed [19:0] r_data1;
    wire [3:0] trueptr,next_ptr;
    reg [2:0] ptr;
    reg signed [19:0] stack [7:0];
    reg signed [19:0] temp;
    DFF #(4) DFF0(clk, next_ptr, trueptr);
    always @(*) begin
       ptr = trueptr;
       temp = trueptr - 1;
        if (rst_n == 0) begin
            ptr = 0;
            r_data1 = 0;
        end
        else begin end
        if (cntrl == `PUSH1) begin
            if(trueptr < 8) begin
                 stack[trueptr] = w_data;
                 ptr = trueptr + 1;
                 //r_data1 = 0;
            end
            else begin
                 //r_data1 = 0;
            end
        end
        else if (cntrl == `POP) begin
            if(trueptr > 0) begin
                 ptr = trueptr - 1;
                 r_data1 = stack[temp];
            end
            else begin
                 //r_data1 = 0;
            end
        end
        else begin
          //r_data1 = 0;
        end
        full = (trueptr < 8)? 0: 1;
        empty = (trueptr > 0)? 1: 0;
    end
    assign next_ptr = (rst_n == 10'd0)? 10'd0: ptr;
    assign r_data = (rst_n == 0)? 0: r_data1;
    // your code
endmodule