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  1. name jemallocator.regular.txt ns/iter jemallocator.xlto.txt ns/iter diff ns/iter diff % speedup
  2. even::rt_alloc_excess_unused_size_1000000_align_1 162 149 -13 -8.02% x 1.09
  3. even::rt_alloc_excess_unused_size_1000000_align_16 165 149 -16 -9.70% x 1.11
  4. even::rt_alloc_excess_unused_size_1000000_align_2 163 149 -14 -8.59% x 1.09
  5. even::rt_alloc_excess_unused_size_1000000_align_32 163 154 -9 -5.52% x 1.06
  6. even::rt_alloc_excess_unused_size_1000000_align_4 162 149 -13 -8.02% x 1.09
  7. even::rt_alloc_excess_unused_size_1000000_align_8 163 149 -14 -8.59% x 1.09
  8. even::rt_alloc_excess_unused_size_100000_align_1 376 344 -32 -8.51% x 1.09
  9. even::rt_alloc_excess_unused_size_100000_align_16 371 347 -24 -6.47% x 1.07
  10. even::rt_alloc_excess_unused_size_100000_align_2 367 353 -14 -3.81% x 1.04
  11. even::rt_alloc_excess_unused_size_100000_align_32 370 346 -24 -6.49% x 1.07
  12. even::rt_alloc_excess_unused_size_100000_align_4 366 344 -22 -6.01% x 1.06
  13. even::rt_alloc_excess_unused_size_100000_align_8 366 343 -23 -6.28% x 1.07
  14. even::rt_alloc_excess_unused_size_10000_align_1 17 15 -2 -11.76% x 1.13
  15. even::rt_alloc_excess_unused_size_10000_align_16 17 15 -2 -11.76% x 1.13
  16. even::rt_alloc_excess_unused_size_10000_align_2 17 15 -2 -11.76% x 1.13
  17. even::rt_alloc_excess_unused_size_10000_align_32 24 21 -3 -12.50% x 1.14
  18. even::rt_alloc_excess_unused_size_10000_align_4 17 15 -2 -11.76% x 1.13
  19. even::rt_alloc_excess_unused_size_10000_align_8 17 15 -2 -11.76% x 1.13
  20. even::rt_alloc_excess_unused_size_1000_align_1 13 11 -2 -15.38% x 1.18
  21. even::rt_alloc_excess_unused_size_1000_align_16 13 11 -2 -15.38% x 1.18
  22. even::rt_alloc_excess_unused_size_1000_align_2 14 11 -3 -21.43% x 1.27
  23. even::rt_alloc_excess_unused_size_1000_align_32 20 17 -3 -15.00% x 1.18
  24. even::rt_alloc_excess_unused_size_1000_align_4 13 11 -2 -15.38% x 1.18
  25. even::rt_alloc_excess_unused_size_1000_align_8 13 11 -2 -15.38% x 1.18
  26. even::rt_alloc_excess_unused_size_100_align_1 13 11 -2 -15.38% x 1.18
  27. even::rt_alloc_excess_unused_size_100_align_16 13 11 -2 -15.38% x 1.18
  28. even::rt_alloc_excess_unused_size_100_align_2 14 11 -3 -21.43% x 1.27
  29. even::rt_alloc_excess_unused_size_100_align_32 20 17 -3 -15.00% x 1.18
  30. even::rt_alloc_excess_unused_size_100_align_4 13 11 -2 -15.38% x 1.18
  31. even::rt_alloc_excess_unused_size_100_align_8 13 11 -2 -15.38% x 1.18
  32. even::rt_alloc_excess_unused_size_10_align_1 14 11 -3 -21.43% x 1.27
  33. even::rt_alloc_excess_unused_size_10_align_16 20 17 -3 -15.00% x 1.18
  34. even::rt_alloc_excess_unused_size_10_align_2 13 11 -2 -15.38% x 1.18
  35. even::rt_alloc_excess_unused_size_10_align_32 20 17 -3 -15.00% x 1.18
  36. even::rt_alloc_excess_unused_size_10_align_4 14 11 -3 -21.43% x 1.27
  37. even::rt_alloc_excess_unused_size_10_align_8 14 11 -3 -21.43% x 1.27
  38. even::rt_alloc_excess_used_size_1000000_align_1 161 168 7 4.35% x 0.96
  39. even::rt_alloc_excess_used_size_1000000_align_16 162 167 5 3.09% x 0.97
  40. even::rt_alloc_excess_used_size_1000000_align_2 161 168 7 4.35% x 0.96
  41. even::rt_alloc_excess_used_size_1000000_align_32 162 167 5 3.09% x 0.97
  42. even::rt_alloc_excess_used_size_1000000_align_4 161 167 6 3.73% x 0.96
  43. even::rt_alloc_excess_used_size_1000000_align_8 160 169 9 5.62% x 0.95
  44. even::rt_alloc_excess_used_size_100000_align_1 162 288 126 77.78% x 0.56
  45. even::rt_alloc_excess_used_size_100000_align_16 161 168 7 4.35% x 0.96
  46. even::rt_alloc_excess_used_size_100000_align_2 161 168 7 4.35% x 0.96
  47. even::rt_alloc_excess_used_size_100000_align_32 162 170 8 4.94% x 0.95
  48. even::rt_alloc_excess_used_size_100000_align_4 161 168 7 4.35% x 0.96
  49. even::rt_alloc_excess_used_size_100000_align_8 160 167 7 4.38% x 0.96
  50. even::rt_alloc_excess_used_size_10000_align_1 17 15 -2 -11.76% x 1.13
  51. even::rt_alloc_excess_used_size_10000_align_16 17 15 -2 -11.76% x 1.13
  52. even::rt_alloc_excess_used_size_10000_align_2 17 15 -2 -11.76% x 1.13
  53. even::rt_alloc_excess_used_size_10000_align_32 24 21 -3 -12.50% x 1.14
  54. even::rt_alloc_excess_used_size_10000_align_4 17 15 -2 -11.76% x 1.13
  55. even::rt_alloc_excess_used_size_10000_align_8 18 15 -3 -16.67% x 1.20
  56. even::rt_alloc_excess_used_size_1000_align_1 13 11 -2 -15.38% x 1.18
  57. even::rt_alloc_excess_used_size_1000_align_16 13 11 -2 -15.38% x 1.18
  58. even::rt_alloc_excess_used_size_1000_align_2 13 11 -2 -15.38% x 1.18
  59. even::rt_alloc_excess_used_size_1000_align_32 20 17 -3 -15.00% x 1.18
  60. even::rt_alloc_excess_used_size_1000_align_4 14 11 -3 -21.43% x 1.27
  61. even::rt_alloc_excess_used_size_1000_align_8 13 11 -2 -15.38% x 1.18
  62. even::rt_alloc_excess_used_size_100_align_1 13 11 -2 -15.38% x 1.18
  63. even::rt_alloc_excess_used_size_100_align_16 13 11 -2 -15.38% x 1.18
  64. even::rt_alloc_excess_used_size_100_align_2 13 11 -2 -15.38% x 1.18
  65. even::rt_alloc_excess_used_size_100_align_32 20 17 -3 -15.00% x 1.18
  66. even::rt_alloc_excess_used_size_100_align_4 13 11 -2 -15.38% x 1.18
  67. even::rt_alloc_excess_used_size_100_align_8 13 11 -2 -15.38% x 1.18
  68. even::rt_alloc_excess_used_size_10_align_1 13 11 -2 -15.38% x 1.18
  69. even::rt_alloc_excess_used_size_10_align_16 20 17 -3 -15.00% x 1.18
  70. even::rt_alloc_excess_used_size_10_align_2 13 11 -2 -15.38% x 1.18
  71. even::rt_alloc_excess_used_size_10_align_32 20 17 -3 -15.00% x 1.18
  72. even::rt_alloc_excess_used_size_10_align_4 14 11 -3 -21.43% x 1.27
  73. even::rt_alloc_excess_used_size_10_align_8 13 11 -2 -15.38% x 1.18
  74. even::rt_alloc_layout_checked_size_1000000_align_1 157 164 7 4.46% x 0.96
  75. even::rt_alloc_layout_checked_size_1000000_align_16 157 166 9 5.73% x 0.95
  76. even::rt_alloc_layout_checked_size_1000000_align_2 157 164 7 4.46% x 0.96
  77. even::rt_alloc_layout_checked_size_1000000_align_32 158 164 6 3.80% x 0.96
  78. even::rt_alloc_layout_checked_size_1000000_align_4 157 167 10 6.37% x 0.94
  79. even::rt_alloc_layout_checked_size_1000000_align_8 157 165 8 5.10% x 0.95
  80. even::rt_alloc_layout_checked_size_100000_align_1 179 164 -15 -8.38% x 1.09
  81. even::rt_alloc_layout_checked_size_100000_align_16 177 164 -13 -7.34% x 1.08
  82. even::rt_alloc_layout_checked_size_100000_align_2 177 164 -13 -7.34% x 1.08
  83. even::rt_alloc_layout_checked_size_100000_align_32 179 166 -13 -7.26% x 1.08
  84. even::rt_alloc_layout_checked_size_100000_align_4 178 164 -14 -7.87% x 1.09
  85. even::rt_alloc_layout_checked_size_100000_align_8 178 164 -14 -7.87% x 1.09
  86. even::rt_alloc_layout_checked_size_10000_align_1 14 12 -2 -14.29% x 1.17
  87. even::rt_alloc_layout_checked_size_10000_align_16 14 12 -2 -14.29% x 1.17
  88. even::rt_alloc_layout_checked_size_10000_align_2 14 12 -2 -14.29% x 1.17
  89. even::rt_alloc_layout_checked_size_10000_align_32 20 18 -2 -10.00% x 1.11
  90. even::rt_alloc_layout_checked_size_10000_align_4 14 12 -2 -14.29% x 1.17
  91. even::rt_alloc_layout_checked_size_10000_align_8 14 12 -2 -14.29% x 1.17
  92. even::rt_alloc_layout_checked_size_1000_align_1 11 9 -2 -18.18% x 1.22
  93. even::rt_alloc_layout_checked_size_1000_align_16 11 9 -2 -18.18% x 1.22
  94. even::rt_alloc_layout_checked_size_1000_align_2 11 9 -2 -18.18% x 1.22
  95. even::rt_alloc_layout_checked_size_1000_align_32 17 14 -3 -17.65% x 1.21
  96. even::rt_alloc_layout_checked_size_1000_align_4 11 9 -2 -18.18% x 1.22
  97. even::rt_alloc_layout_checked_size_1000_align_8 11 9 -2 -18.18% x 1.22
  98. even::rt_alloc_layout_checked_size_100_align_1 11 9 -2 -18.18% x 1.22
  99. even::rt_alloc_layout_checked_size_100_align_16 11 9 -2 -18.18% x 1.22
  100. even::rt_alloc_layout_checked_size_100_align_2 11 9 -2 -18.18% x 1.22
  101. even::rt_alloc_layout_checked_size_100_align_32 17 14 -3 -17.65% x 1.21
  102. even::rt_alloc_layout_checked_size_100_align_4 11 9 -2 -18.18% x 1.22
  103. even::rt_alloc_layout_checked_size_100_align_8 11 9 -2 -18.18% x 1.22
  104. even::rt_alloc_layout_checked_size_10_align_1 11 9 -2 -18.18% x 1.22
  105. even::rt_alloc_layout_checked_size_10_align_16 16 14 -2 -12.50% x 1.14
  106. even::rt_alloc_layout_checked_size_10_align_2 11 9 -2 -18.18% x 1.22
  107. even::rt_alloc_layout_checked_size_10_align_32 17 14 -3 -17.65% x 1.21
  108. even::rt_alloc_layout_checked_size_10_align_4 11 9 -2 -18.18% x 1.22
  109. even::rt_alloc_layout_checked_size_10_align_8 11 9 -2 -18.18% x 1.22
  110. even::rt_alloc_layout_unchecked_size_1000000_align_1 157 164 7 4.46% x 0.96
  111. even::rt_alloc_layout_unchecked_size_1000000_align_16 158 164 6 3.80% x 0.96
  112. even::rt_alloc_layout_unchecked_size_1000000_align_2 159 164 5 3.14% x 0.97
  113. even::rt_alloc_layout_unchecked_size_1000000_align_32 158 165 7 4.43% x 0.96
  114. even::rt_alloc_layout_unchecked_size_1000000_align_4 157 164 7 4.46% x 0.96
  115. even::rt_alloc_layout_unchecked_size_1000000_align_8 157 164 7 4.46% x 0.96
  116. even::rt_alloc_layout_unchecked_size_100000_align_1 368 164 -204 -55.43% x 2.24
  117. even::rt_alloc_layout_unchecked_size_100000_align_16 157 164 7 4.46% x 0.96
  118. even::rt_alloc_layout_unchecked_size_100000_align_2 157 165 8 5.10% x 0.95
  119. even::rt_alloc_layout_unchecked_size_100000_align_32 158 168 10 6.33% x 0.94
  120. even::rt_alloc_layout_unchecked_size_100000_align_4 157 164 7 4.46% x 0.96
  121. even::rt_alloc_layout_unchecked_size_100000_align_8 158 163 5 3.16% x 0.97
  122. even::rt_alloc_layout_unchecked_size_10000_align_1 14 12 -2 -14.29% x 1.17
  123. even::rt_alloc_layout_unchecked_size_10000_align_16 14 12 -2 -14.29% x 1.17
  124. even::rt_alloc_layout_unchecked_size_10000_align_2 14 12 -2 -14.29% x 1.17
  125. even::rt_alloc_layout_unchecked_size_10000_align_32 20 18 -2 -10.00% x 1.11
  126. even::rt_alloc_layout_unchecked_size_10000_align_4 14 12 -2 -14.29% x 1.17
  127. even::rt_alloc_layout_unchecked_size_10000_align_8 14 12 -2 -14.29% x 1.17
  128. even::rt_alloc_layout_unchecked_size_1000_align_1 11 9 -2 -18.18% x 1.22
  129. even::rt_alloc_layout_unchecked_size_1000_align_16 11 9 -2 -18.18% x 1.22
  130. even::rt_alloc_layout_unchecked_size_1000_align_2 11 9 -2 -18.18% x 1.22
  131. even::rt_alloc_layout_unchecked_size_1000_align_32 17 14 -3 -17.65% x 1.21
  132. even::rt_alloc_layout_unchecked_size_1000_align_4 11 9 -2 -18.18% x 1.22
  133. even::rt_alloc_layout_unchecked_size_1000_align_8 11 9 -2 -18.18% x 1.22
  134. even::rt_alloc_layout_unchecked_size_100_align_1 11 9 -2 -18.18% x 1.22
  135. even::rt_alloc_layout_unchecked_size_100_align_16 11 9 -2 -18.18% x 1.22
  136. even::rt_alloc_layout_unchecked_size_100_align_2 11 9 -2 -18.18% x 1.22
  137. even::rt_alloc_layout_unchecked_size_100_align_32 17 14 -3 -17.65% x 1.21
  138. even::rt_alloc_layout_unchecked_size_100_align_4 11 9 -2 -18.18% x 1.22
  139. even::rt_alloc_layout_unchecked_size_100_align_8 11 9 -2 -18.18% x 1.22
  140. even::rt_alloc_layout_unchecked_size_10_align_1 11 9 -2 -18.18% x 1.22
  141. even::rt_alloc_layout_unchecked_size_10_align_16 16 14 -2 -12.50% x 1.14
  142. even::rt_alloc_layout_unchecked_size_10_align_2 11 9 -2 -18.18% x 1.22
  143. even::rt_alloc_layout_unchecked_size_10_align_32 17 14 -3 -17.65% x 1.21
  144. even::rt_alloc_layout_unchecked_size_10_align_4 11 9 -2 -18.18% x 1.22
  145. even::rt_alloc_layout_unchecked_size_10_align_8 11 9 -2 -18.18% x 1.22
  146. even::rt_calloc_size_1000000_align_1 742 792 50 6.74% x 0.94
  147. even::rt_calloc_size_1000000_align_16 735 791 56 7.62% x 0.93
  148. even::rt_calloc_size_1000000_align_2 740 792 52 7.03% x 0.93
  149. even::rt_calloc_size_1000000_align_32 741 791 50 6.75% x 0.94
  150. even::rt_calloc_size_1000000_align_4 739 791 52 7.04% x 0.93
  151. even::rt_calloc_size_1000000_align_8 739 792 53 7.17% x 0.93
  152. even::rt_calloc_size_100000_align_1 4,784 4,580 -204 -4.26% x 1.04
  153. even::rt_calloc_size_100000_align_16 4,789 4,579 -210 -4.39% x 1.05
  154. even::rt_calloc_size_100000_align_2 4,763 4,629 -134 -2.81% x 1.03
  155. even::rt_calloc_size_100000_align_32 4,791 4,627 -164 -3.42% x 1.04
  156. even::rt_calloc_size_100000_align_4 4,789 4,605 -184 -3.84% x 1.04
  157. even::rt_calloc_size_100000_align_8 4,745 4,587 -158 -3.33% x 1.03
  158. even::rt_calloc_size_10000_align_1 58 55 -3 -5.17% x 1.05
  159. even::rt_calloc_size_10000_align_16 58 55 -3 -5.17% x 1.05
  160. even::rt_calloc_size_10000_align_2 59 55 -4 -6.78% x 1.07
  161. even::rt_calloc_size_10000_align_32 58 56 -2 -3.45% x 1.04
  162. even::rt_calloc_size_10000_align_4 58 56 -2 -3.45% x 1.04
  163. even::rt_calloc_size_10000_align_8 58 55 -3 -5.17% x 1.05
  164. even::rt_calloc_size_1000_align_1 19 18 -1 -5.26% x 1.06
  165. even::rt_calloc_size_1000_align_16 19 18 -1 -5.26% x 1.06
  166. even::rt_calloc_size_1000_align_2 19 18 -1 -5.26% x 1.06
  167. even::rt_calloc_size_1000_align_32 19 18 -1 -5.26% x 1.06
  168. even::rt_calloc_size_1000_align_4 19 18 -1 -5.26% x 1.06
  169. even::rt_calloc_size_1000_align_8 19 18 -1 -5.26% x 1.06
  170. even::rt_calloc_size_100_align_1 13 9 -4 -30.77% x 1.44
  171. even::rt_calloc_size_100_align_16 13 10 -3 -23.08% x 1.30
  172. even::rt_calloc_size_100_align_2 13 9 -4 -30.77% x 1.44
  173. even::rt_calloc_size_100_align_32 13 9 -4 -30.77% x 1.44
  174. even::rt_calloc_size_100_align_4 13 9 -4 -30.77% x 1.44
  175. even::rt_calloc_size_100_align_8 13 9 -4 -30.77% x 1.44
  176. even::rt_calloc_size_10_align_1 12 9 -3 -25.00% x 1.33
  177. even::rt_calloc_size_10_align_16 13 9 -4 -30.77% x 1.44
  178. even::rt_calloc_size_10_align_2 12 9 -3 -25.00% x 1.33
  179. even::rt_calloc_size_10_align_32 12 9 -3 -25.00% x 1.33
  180. even::rt_calloc_size_10_align_4 12 9 -3 -25.00% x 1.33
  181. even::rt_calloc_size_10_align_8 12 9 -3 -25.00% x 1.33
  182. even::rt_mallocx_nallocx_size_1000000_align_1 159 167 8 5.03% x 0.95
  183. even::rt_mallocx_nallocx_size_1000000_align_16 160 167 7 4.38% x 0.96
  184. even::rt_mallocx_nallocx_size_1000000_align_2 160 170 10 6.25% x 0.94
  185. even::rt_mallocx_nallocx_size_1000000_align_32 159 167 8 5.03% x 0.95
  186. even::rt_mallocx_nallocx_size_1000000_align_4 159 167 8 5.03% x 0.95
  187. even::rt_mallocx_nallocx_size_1000000_align_8 159 170 11 6.92% x 0.94
  188. even::rt_mallocx_nallocx_size_100000_align_1 159 167 8 5.03% x 0.95
  189. even::rt_mallocx_nallocx_size_100000_align_16 159 167 8 5.03% x 0.95
  190. even::rt_mallocx_nallocx_size_100000_align_2 160 171 11 6.88% x 0.94
  191. even::rt_mallocx_nallocx_size_100000_align_32 160 167 7 4.38% x 0.96
  192. even::rt_mallocx_nallocx_size_100000_align_4 158 167 9 5.70% x 0.95
  193. even::rt_mallocx_nallocx_size_100000_align_8 159 169 10 6.29% x 0.94
  194. even::rt_mallocx_nallocx_size_10000_align_1 16 15 -1 -6.25% x 1.07
  195. even::rt_mallocx_nallocx_size_10000_align_16 16 15 -1 -6.25% x 1.07
  196. even::rt_mallocx_nallocx_size_10000_align_2 16 15 -1 -6.25% x 1.07
  197. even::rt_mallocx_nallocx_size_10000_align_32 22 22 0 0.00% x 1.00
  198. even::rt_mallocx_nallocx_size_10000_align_4 16 15 -1 -6.25% x 1.07
  199. even::rt_mallocx_nallocx_size_10000_align_8 16 15 -1 -6.25% x 1.07
  200. even::rt_mallocx_nallocx_size_1000_align_1 12 11 -1 -8.33% x 1.09
  201. even::rt_mallocx_nallocx_size_1000_align_16 12 11 -1 -8.33% x 1.09
  202. even::rt_mallocx_nallocx_size_1000_align_2 12 11 -1 -8.33% x 1.09
  203. even::rt_mallocx_nallocx_size_1000_align_32 18 17 -1 -5.56% x 1.06
  204. even::rt_mallocx_nallocx_size_1000_align_4 12 11 -1 -8.33% x 1.09
  205. even::rt_mallocx_nallocx_size_1000_align_8 12 11 -1 -8.33% x 1.09
  206. even::rt_mallocx_nallocx_size_100_align_1 12 11 -1 -8.33% x 1.09
  207. even::rt_mallocx_nallocx_size_100_align_16 12 11 -1 -8.33% x 1.09
  208. even::rt_mallocx_nallocx_size_100_align_2 12 11 -1 -8.33% x 1.09
  209. even::rt_mallocx_nallocx_size_100_align_32 18 17 -1 -5.56% x 1.06
  210. even::rt_mallocx_nallocx_size_100_align_4 13 11 -2 -15.38% x 1.18
  211. even::rt_mallocx_nallocx_size_100_align_8 13 11 -2 -15.38% x 1.18
  212. even::rt_mallocx_nallocx_size_10_align_1 12 11 -1 -8.33% x 1.09
  213. even::rt_mallocx_nallocx_size_10_align_16 19 17 -2 -10.53% x 1.12
  214. even::rt_mallocx_nallocx_size_10_align_2 12 11 -1 -8.33% x 1.09
  215. even::rt_mallocx_nallocx_size_10_align_32 18 17 -1 -5.56% x 1.06
  216. even::rt_mallocx_nallocx_size_10_align_4 12 11 -1 -8.33% x 1.09
  217. even::rt_mallocx_nallocx_size_10_align_8 12 11 -1 -8.33% x 1.09
  218. even::rt_mallocx_size_1000000_align_1 156 163 7 4.49% x 0.96
  219. even::rt_mallocx_size_1000000_align_16 158 163 5 3.16% x 0.97
  220. even::rt_mallocx_size_1000000_align_2 156 163 7 4.49% x 0.96
  221. even::rt_mallocx_size_1000000_align_32 156 164 8 5.13% x 0.95
  222. even::rt_mallocx_size_1000000_align_4 157 164 7 4.46% x 0.96
  223. even::rt_mallocx_size_1000000_align_8 156 165 9 5.77% x 0.95
  224. even::rt_mallocx_size_100000_align_1 160 163 3 1.88% x 0.98
  225. even::rt_mallocx_size_100000_align_16 156 164 8 5.13% x 0.95
  226. even::rt_mallocx_size_100000_align_2 156 163 7 4.49% x 0.96
  227. even::rt_mallocx_size_100000_align_32 156 163 7 4.49% x 0.96
  228. even::rt_mallocx_size_100000_align_4 156 163 7 4.49% x 0.96
  229. even::rt_mallocx_size_100000_align_8 156 165 9 5.77% x 0.95
  230. even::rt_mallocx_size_10000_align_1 13 12 -1 -7.69% x 1.08
  231. even::rt_mallocx_size_10000_align_16 13 12 -1 -7.69% x 1.08
  232. even::rt_mallocx_size_10000_align_2 13 12 -1 -7.69% x 1.08
  233. even::rt_mallocx_size_10000_align_32 18 18 0 0.00% x 1.00
  234. even::rt_mallocx_size_10000_align_4 13 12 -1 -7.69% x 1.08
  235. even::rt_mallocx_size_10000_align_8 13 12 -1 -7.69% x 1.08
  236. even::rt_mallocx_size_1000_align_1 10 9 -1 -10.00% x 1.11
  237. even::rt_mallocx_size_1000_align_16 10 9 -1 -10.00% x 1.11
  238. even::rt_mallocx_size_1000_align_2 10 9 -1 -10.00% x 1.11
  239. even::rt_mallocx_size_1000_align_32 15 15 0 0.00% x 1.00
  240. even::rt_mallocx_size_1000_align_4 10 9 -1 -10.00% x 1.11
  241. even::rt_mallocx_size_1000_align_8 10 9 -1 -10.00% x 1.11
  242. even::rt_mallocx_size_100_align_1 10 9 -1 -10.00% x 1.11
  243. even::rt_mallocx_size_100_align_16 10 9 -1 -10.00% x 1.11
  244. even::rt_mallocx_size_100_align_2 10 9 -1 -10.00% x 1.11
  245. even::rt_mallocx_size_100_align_32 15 14 -1 -6.67% x 1.07
  246. even::rt_mallocx_size_100_align_4 10 9 -1 -10.00% x 1.11
  247. even::rt_mallocx_size_100_align_8 10 9 -1 -10.00% x 1.11
  248. even::rt_mallocx_size_10_align_1 10 9 -1 -10.00% x 1.11
  249. even::rt_mallocx_size_10_align_16 15 14 -1 -6.67% x 1.07
  250. even::rt_mallocx_size_10_align_2 10 9 -1 -10.00% x 1.11
  251. even::rt_mallocx_size_10_align_32 15 14 -1 -6.67% x 1.07
  252. even::rt_mallocx_size_10_align_4 10 9 -1 -10.00% x 1.11
  253. even::rt_mallocx_size_10_align_8 10 9 -1 -10.00% x 1.11
  254. even::rt_mallocx_zeroed_size_1000000_align_1 835 792 -43 -5.15% x 1.05
  255. even::rt_mallocx_zeroed_size_1000000_align_16 832 792 -40 -4.81% x 1.05
  256. even::rt_mallocx_zeroed_size_1000000_align_2 831 794 -37 -4.45% x 1.05
  257. even::rt_mallocx_zeroed_size_1000000_align_32 826 781 -45 -5.45% x 1.06
  258. even::rt_mallocx_zeroed_size_1000000_align_4 833 794 -39 -4.68% x 1.05
  259. even::rt_mallocx_zeroed_size_1000000_align_8 838 796 -42 -5.01% x 1.05
  260. even::rt_mallocx_zeroed_size_100000_align_1 4,804 4,659 -145 -3.02% x 1.03
  261. even::rt_mallocx_zeroed_size_100000_align_16 4,785 4,837 52 1.09% x 0.99
  262. even::rt_mallocx_zeroed_size_100000_align_2 4,829 4,576 -253 -5.24% x 1.06
  263. even::rt_mallocx_zeroed_size_100000_align_32 4,787 4,623 -164 -3.43% x 1.04
  264. even::rt_mallocx_zeroed_size_100000_align_4 4,892 4,627 -265 -5.42% x 1.06
  265. even::rt_mallocx_zeroed_size_100000_align_8 4,788 4,616 -172 -3.59% x 1.04
  266. even::rt_mallocx_zeroed_size_10000_align_1 61 56 -5 -8.20% x 1.09
  267. even::rt_mallocx_zeroed_size_10000_align_16 60 56 -4 -6.67% x 1.07
  268. even::rt_mallocx_zeroed_size_10000_align_2 60 56 -4 -6.67% x 1.07
  269. even::rt_mallocx_zeroed_size_10000_align_32 64 61 -3 -4.69% x 1.05
  270. even::rt_mallocx_zeroed_size_10000_align_4 61 57 -4 -6.56% x 1.07
  271. even::rt_mallocx_zeroed_size_10000_align_8 60 57 -3 -5.00% x 1.05
  272. even::rt_mallocx_zeroed_size_1000_align_1 19 19 0 0.00% x 1.00
  273. even::rt_mallocx_zeroed_size_1000_align_16 19 18 -1 -5.26% x 1.06
  274. even::rt_mallocx_zeroed_size_1000_align_2 19 19 0 0.00% x 1.00
  275. even::rt_mallocx_zeroed_size_1000_align_32 24 22 -2 -8.33% x 1.09
  276. even::rt_mallocx_zeroed_size_1000_align_4 19 19 0 0.00% x 1.00
  277. even::rt_mallocx_zeroed_size_1000_align_8 19 19 0 0.00% x 1.00
  278. even::rt_mallocx_zeroed_size_100_align_1 14 11 -3 -21.43% x 1.27
  279. even::rt_mallocx_zeroed_size_100_align_16 13 11 -2 -15.38% x 1.18
  280. even::rt_mallocx_zeroed_size_100_align_2 13 11 -2 -15.38% x 1.18
  281. even::rt_mallocx_zeroed_size_100_align_32 17 15 -2 -11.76% x 1.13
  282. even::rt_mallocx_zeroed_size_100_align_4 13 11 -2 -15.38% x 1.18
  283. even::rt_mallocx_zeroed_size_100_align_8 13 11 -2 -15.38% x 1.18
  284. even::rt_mallocx_zeroed_size_10_align_1 14 11 -3 -21.43% x 1.27
  285. even::rt_mallocx_zeroed_size_10_align_16 17 15 -2 -11.76% x 1.13
  286. even::rt_mallocx_zeroed_size_10_align_2 14 11 -3 -21.43% x 1.27
  287. even::rt_mallocx_zeroed_size_10_align_32 17 15 -2 -11.76% x 1.13
  288. even::rt_mallocx_zeroed_size_10_align_4 14 11 -3 -21.43% x 1.27
  289. even::rt_mallocx_zeroed_size_10_align_8 14 11 -3 -21.43% x 1.27
  290. even::rt_realloc_excess_unused_size_1000000_align_1 425 413 -12 -2.82% x 1.03
  291. even::rt_realloc_excess_unused_size_1000000_align_16 426 413 -13 -3.05% x 1.03
  292. even::rt_realloc_excess_unused_size_1000000_align_2 429 410 -19 -4.43% x 1.05
  293. even::rt_realloc_excess_unused_size_1000000_align_32 427 411 -16 -3.75% x 1.04
  294. even::rt_realloc_excess_unused_size_1000000_align_4 425 413 -12 -2.82% x 1.03
  295. even::rt_realloc_excess_unused_size_1000000_align_8 427 411 -16 -3.75% x 1.04
  296. even::rt_realloc_excess_unused_size_100000_align_1 636 411 -225 -35.38% x 1.55
  297. even::rt_realloc_excess_unused_size_100000_align_16 430 412 -18 -4.19% x 1.04
  298. even::rt_realloc_excess_unused_size_100000_align_2 428 410 -18 -4.21% x 1.04
  299. even::rt_realloc_excess_unused_size_100000_align_32 425 412 -13 -3.06% x 1.03
  300. even::rt_realloc_excess_unused_size_100000_align_4 425 413 -12 -2.82% x 1.03
  301. even::rt_realloc_excess_unused_size_100000_align_8 431 418 -13 -3.02% x 1.03
  302. even::rt_realloc_excess_unused_size_10000_align_1 97 92 -5 -5.15% x 1.05
  303. even::rt_realloc_excess_unused_size_10000_align_16 98 95 -3 -3.06% x 1.03
  304. even::rt_realloc_excess_unused_size_10000_align_2 98 94 -4 -4.08% x 1.04
  305. even::rt_realloc_excess_unused_size_10000_align_32 399 385 -14 -3.51% x 1.04
  306. even::rt_realloc_excess_unused_size_10000_align_4 91 86 -5 -5.49% x 1.06
  307. even::rt_realloc_excess_unused_size_10000_align_8 91 87 -4 -4.40% x 1.05
  308. even::rt_realloc_excess_unused_size_1000_align_1 44 39 -5 -11.36% x 1.13
  309. even::rt_realloc_excess_unused_size_1000_align_16 44 39 -5 -11.36% x 1.13
  310. even::rt_realloc_excess_unused_size_1000_align_2 44 39 -5 -11.36% x 1.13
  311. even::rt_realloc_excess_unused_size_1000_align_32 54 48 -6 -11.11% x 1.12
  312. even::rt_realloc_excess_unused_size_1000_align_4 44 39 -5 -11.36% x 1.13
  313. even::rt_realloc_excess_unused_size_1000_align_8 44 39 -5 -11.36% x 1.13
  314. even::rt_realloc_excess_unused_size_100_align_1 35 30 -5 -14.29% x 1.17
  315. even::rt_realloc_excess_unused_size_100_align_16 35 30 -5 -14.29% x 1.17
  316. even::rt_realloc_excess_unused_size_100_align_2 35 31 -4 -11.43% x 1.13
  317. even::rt_realloc_excess_unused_size_100_align_32 47 41 -6 -12.77% x 1.15
  318. even::rt_realloc_excess_unused_size_100_align_4 35 31 -4 -11.43% x 1.13
  319. even::rt_realloc_excess_unused_size_100_align_8 35 31 -4 -11.43% x 1.13
  320. even::rt_realloc_excess_unused_size_10_align_1 36 30 -6 -16.67% x 1.20
  321. even::rt_realloc_excess_unused_size_10_align_16 41 34 -7 -17.07% x 1.21
  322. even::rt_realloc_excess_unused_size_10_align_2 36 30 -6 -16.67% x 1.20
  323. even::rt_realloc_excess_unused_size_10_align_32 38 31 -7 -18.42% x 1.23
  324. even::rt_realloc_excess_unused_size_10_align_4 36 30 -6 -16.67% x 1.20
  325. even::rt_realloc_excess_unused_size_10_align_8 36 30 -6 -16.67% x 1.20
  326. even::rt_realloc_excess_used_size_1000000_align_1 445 415 -30 -6.74% x 1.07
  327. even::rt_realloc_excess_used_size_1000000_align_16 446 417 -29 -6.50% x 1.07
  328. even::rt_realloc_excess_used_size_1000000_align_2 448 413 -35 -7.81% x 1.08
  329. even::rt_realloc_excess_used_size_1000000_align_32 444 418 -26 -5.86% x 1.06
  330. even::rt_realloc_excess_used_size_1000000_align_4 446 413 -33 -7.40% x 1.08
  331. even::rt_realloc_excess_used_size_1000000_align_8 445 416 -29 -6.52% x 1.07
  332. even::rt_realloc_excess_used_size_100000_align_1 445 413 -32 -7.19% x 1.08
  333. even::rt_realloc_excess_used_size_100000_align_16 449 419 -30 -6.68% x 1.07
  334. even::rt_realloc_excess_used_size_100000_align_2 445 417 -28 -6.29% x 1.07
  335. even::rt_realloc_excess_used_size_100000_align_32 448 414 -34 -7.59% x 1.08
  336. even::rt_realloc_excess_used_size_100000_align_4 445 413 -32 -7.19% x 1.08
  337. even::rt_realloc_excess_used_size_100000_align_8 445 420 -25 -5.62% x 1.06
  338. even::rt_realloc_excess_used_size_10000_align_1 92 85 -7 -7.61% x 1.08
  339. even::rt_realloc_excess_used_size_10000_align_16 93 85 -8 -8.60% x 1.09
  340. even::rt_realloc_excess_used_size_10000_align_2 93 85 -8 -8.60% x 1.09
  341. even::rt_realloc_excess_used_size_10000_align_32 370 360 -10 -2.70% x 1.03
  342. even::rt_realloc_excess_used_size_10000_align_4 98 85 -13 -13.27% x 1.15
  343. even::rt_realloc_excess_used_size_10000_align_8 100 85 -15 -15.00% x 1.18
  344. even::rt_realloc_excess_used_size_1000_align_1 44 40 -4 -9.09% x 1.10
  345. even::rt_realloc_excess_used_size_1000_align_16 44 39 -5 -11.36% x 1.13
  346. even::rt_realloc_excess_used_size_1000_align_2 44 39 -5 -11.36% x 1.13
  347. even::rt_realloc_excess_used_size_1000_align_32 54 48 -6 -11.11% x 1.12
  348. even::rt_realloc_excess_used_size_1000_align_4 44 39 -5 -11.36% x 1.13
  349. even::rt_realloc_excess_used_size_1000_align_8 44 39 -5 -11.36% x 1.13
  350. even::rt_realloc_excess_used_size_100_align_1 36 31 -5 -13.89% x 1.16
  351. even::rt_realloc_excess_used_size_100_align_16 36 31 -5 -13.89% x 1.16
  352. even::rt_realloc_excess_used_size_100_align_2 35 31 -4 -11.43% x 1.13
  353. even::rt_realloc_excess_used_size_100_align_32 47 40 -7 -14.89% x 1.18
  354. even::rt_realloc_excess_used_size_100_align_4 35 31 -4 -11.43% x 1.13
  355. even::rt_realloc_excess_used_size_100_align_8 36 30 -6 -16.67% x 1.20
  356. even::rt_realloc_excess_used_size_10_align_1 37 30 -7 -18.92% x 1.23
  357. even::rt_realloc_excess_used_size_10_align_16 42 34 -8 -19.05% x 1.24
  358. even::rt_realloc_excess_used_size_10_align_2 37 30 -7 -18.92% x 1.23
  359. even::rt_realloc_excess_used_size_10_align_32 38 32 -6 -15.79% x 1.19
  360. even::rt_realloc_excess_used_size_10_align_4 36 31 -5 -13.89% x 1.16
  361. even::rt_realloc_excess_used_size_10_align_8 37 30 -7 -18.92% x 1.23
  362. even::rt_realloc_naive_size_1000000_align_1 41,959 45,772 3,813 9.09% x 0.92
  363. even::rt_realloc_naive_size_1000000_align_16 41,938 46,261 4,323 10.31% x 0.91
  364. even::rt_realloc_naive_size_1000000_align_2 41,939 45,552 3,613 8.61% x 0.92
  365. even::rt_realloc_naive_size_1000000_align_32 42,054 45,897 3,843 9.14% x 0.92
  366. even::rt_realloc_naive_size_1000000_align_4 42,161 45,662 3,501 8.30% x 0.92
  367. even::rt_realloc_naive_size_1000000_align_8 41,929 46,144 4,215 10.05% x 0.91
  368. even::rt_realloc_naive_size_100000_align_1 2,501 2,499 -2 -0.08% x 1.00
  369. even::rt_realloc_naive_size_100000_align_16 2,500 2,430 -70 -2.80% x 1.03
  370. even::rt_realloc_naive_size_100000_align_2 2,285 2,427 142 6.21% x 0.94
  371. even::rt_realloc_naive_size_100000_align_32 2,190 2,422 232 10.59% x 0.90
  372. even::rt_realloc_naive_size_100000_align_4 2,277 2,394 117 5.14% x 0.95
  373. even::rt_realloc_naive_size_100000_align_8 2,257 2,410 153 6.78% x 0.94
  374. even::rt_realloc_naive_size_10000_align_1 90 73 -17 -18.89% x 1.23
  375. even::rt_realloc_naive_size_10000_align_16 91 105 14 15.38% x 0.87
  376. even::rt_realloc_naive_size_10000_align_2 89 73 -16 -17.98% x 1.22
  377. even::rt_realloc_naive_size_10000_align_32 366 365 -1 -0.27% x 1.00
  378. even::rt_realloc_naive_size_10000_align_4 82 74 -8 -9.76% x 1.11
  379. even::rt_realloc_naive_size_10000_align_8 82 73 -9 -10.98% x 1.12
  380. even::rt_realloc_naive_size_1000_align_1 32 26 -6 -18.75% x 1.23
  381. even::rt_realloc_naive_size_1000_align_16 32 27 -5 -15.62% x 1.19
  382. even::rt_realloc_naive_size_1000_align_2 32 26 -6 -18.75% x 1.23
  383. even::rt_realloc_naive_size_1000_align_32 43 38 -5 -11.63% x 1.13
  384. even::rt_realloc_naive_size_1000_align_4 32 27 -5 -15.62% x 1.19
  385. even::rt_realloc_naive_size_1000_align_8 32 26 -6 -18.75% x 1.23
  386. even::rt_realloc_naive_size_100_align_1 27 20 -7 -25.93% x 1.35
  387. even::rt_realloc_naive_size_100_align_16 27 19 -8 -29.63% x 1.42
  388. even::rt_realloc_naive_size_100_align_2 27 19 -8 -29.63% x 1.42
  389. even::rt_realloc_naive_size_100_align_32 36 30 -6 -16.67% x 1.20
  390. even::rt_realloc_naive_size_100_align_4 26 20 -6 -23.08% x 1.30
  391. even::rt_realloc_naive_size_100_align_8 26 19 -7 -26.92% x 1.37
  392. even::rt_realloc_naive_size_10_align_1 25 18 -7 -28.00% x 1.39
  393. even::rt_realloc_naive_size_10_align_16 30 24 -6 -20.00% x 1.25
  394. even::rt_realloc_naive_size_10_align_2 25 18 -7 -28.00% x 1.39
  395. even::rt_realloc_naive_size_10_align_32 34 29 -5 -14.71% x 1.17
  396. even::rt_realloc_naive_size_10_align_4 23 18 -5 -21.74% x 1.28
  397. even::rt_realloc_naive_size_10_align_8 22 18 -4 -18.18% x 1.22
  398. even::rt_realloc_size_1000000_align_1 421 410 -11 -2.61% x 1.03
  399. even::rt_realloc_size_1000000_align_16 420 410 -10 -2.38% x 1.02
  400. even::rt_realloc_size_1000000_align_2 420 413 -7 -1.67% x 1.02
  401. even::rt_realloc_size_1000000_align_32 420 410 -10 -2.38% x 1.02
  402. even::rt_realloc_size_1000000_align_4 421 412 -9 -2.14% x 1.02
  403. even::rt_realloc_size_1000000_align_8 418 415 -3 -0.72% x 1.01
  404. even::rt_realloc_size_100000_align_1 424 410 -14 -3.30% x 1.03
  405. even::rt_realloc_size_100000_align_16 426 420 -6 -1.41% x 1.01
  406. even::rt_realloc_size_100000_align_2 421 410 -11 -2.61% x 1.03
  407. even::rt_realloc_size_100000_align_32 421 410 -11 -2.61% x 1.03
  408. even::rt_realloc_size_100000_align_4 421 411 -10 -2.38% x 1.02
  409. even::rt_realloc_size_100000_align_8 424 410 -14 -3.30% x 1.03
  410. even::rt_realloc_size_10000_align_1 86 82 -4 -4.65% x 1.05
  411. even::rt_realloc_size_10000_align_16 86 83 -3 -3.49% x 1.04
  412. even::rt_realloc_size_10000_align_2 86 82 -4 -4.65% x 1.05
  413. even::rt_realloc_size_10000_align_32 363 387 24 6.61% x 0.94
  414. even::rt_realloc_size_10000_align_4 92 82 -10 -10.87% x 1.12
  415. even::rt_realloc_size_10000_align_8 90 83 -7 -7.78% x 1.08
  416. even::rt_realloc_size_1000_align_1 41 37 -4 -9.76% x 1.11
  417. even::rt_realloc_size_1000_align_16 41 37 -4 -9.76% x 1.11
  418. even::rt_realloc_size_1000_align_2 42 37 -5 -11.90% x 1.14
  419. even::rt_realloc_size_1000_align_32 49 45 -4 -8.16% x 1.09
  420. even::rt_realloc_size_1000_align_4 41 38 -3 -7.32% x 1.08
  421. even::rt_realloc_size_1000_align_8 41 37 -4 -9.76% x 1.11
  422. even::rt_realloc_size_100_align_1 33 28 -5 -15.15% x 1.18
  423. even::rt_realloc_size_100_align_16 33 28 -5 -15.15% x 1.18
  424. even::rt_realloc_size_100_align_2 34 28 -6 -17.65% x 1.21
  425. even::rt_realloc_size_100_align_32 43 38 -5 -11.63% x 1.13
  426. even::rt_realloc_size_100_align_4 33 28 -5 -15.15% x 1.18
  427. even::rt_realloc_size_100_align_8 33 28 -5 -15.15% x 1.18
  428. even::rt_realloc_size_10_align_1 34 28 -6 -17.65% x 1.21
  429. even::rt_realloc_size_10_align_16 39 32 -7 -17.95% x 1.22
  430. even::rt_realloc_size_10_align_2 34 28 -6 -17.65% x 1.21
  431. even::rt_realloc_size_10_align_32 33 28 -5 -15.15% x 1.18
  432. even::rt_realloc_size_10_align_4 34 28 -6 -17.65% x 1.21
  433. even::rt_realloc_size_10_align_8 34 28 -6 -17.65% x 1.21
  434. odd::rt_alloc_excess_unused_size_999999_align_1 161 167 6 3.73% x 0.96
  435. odd::rt_alloc_excess_unused_size_999999_align_16 162 167 5 3.09% x 0.97
  436. odd::rt_alloc_excess_unused_size_999999_align_2 163 167 4 2.45% x 0.98
  437. odd::rt_alloc_excess_unused_size_999999_align_32 162 167 5 3.09% x 0.97
  438. odd::rt_alloc_excess_unused_size_999999_align_4 161 167 6 3.73% x 0.96
  439. odd::rt_alloc_excess_unused_size_999999_align_8 161 167 6 3.73% x 0.96
  440. odd::rt_alloc_excess_unused_size_99999_align_1 161 167 6 3.73% x 0.96
  441. odd::rt_alloc_excess_unused_size_99999_align_16 160 168 8 5.00% x 0.95
  442. odd::rt_alloc_excess_unused_size_99999_align_2 161 168 7 4.35% x 0.96
  443. odd::rt_alloc_excess_unused_size_99999_align_32 164 167 3 1.83% x 0.98
  444. odd::rt_alloc_excess_unused_size_99999_align_4 160 170 10 6.25% x 0.94
  445. odd::rt_alloc_excess_unused_size_99999_align_8 161 169 8 4.97% x 0.95
  446. odd::rt_alloc_excess_unused_size_9999_align_1 17 15 -2 -11.76% x 1.13
  447. odd::rt_alloc_excess_unused_size_9999_align_16 17 15 -2 -11.76% x 1.13
  448. odd::rt_alloc_excess_unused_size_9999_align_2 17 15 -2 -11.76% x 1.13
  449. odd::rt_alloc_excess_unused_size_9999_align_32 24 21 -3 -12.50% x 1.14
  450. odd::rt_alloc_excess_unused_size_9999_align_4 18 15 -3 -16.67% x 1.20
  451. odd::rt_alloc_excess_unused_size_9999_align_8 17 15 -2 -11.76% x 1.13
  452. odd::rt_alloc_excess_unused_size_999_align_1 14 11 -3 -21.43% x 1.27
  453. odd::rt_alloc_excess_unused_size_999_align_16 13 11 -2 -15.38% x 1.18
  454. odd::rt_alloc_excess_unused_size_999_align_2 13 11 -2 -15.38% x 1.18
  455. odd::rt_alloc_excess_unused_size_999_align_32 20 17 -3 -15.00% x 1.18
  456. odd::rt_alloc_excess_unused_size_999_align_4 13 11 -2 -15.38% x 1.18
  457. odd::rt_alloc_excess_unused_size_999_align_8 13 11 -2 -15.38% x 1.18
  458. odd::rt_alloc_excess_unused_size_99_align_1 13 11 -2 -15.38% x 1.18
  459. odd::rt_alloc_excess_unused_size_99_align_16 13 11 -2 -15.38% x 1.18
  460. odd::rt_alloc_excess_unused_size_99_align_2 13 11 -2 -15.38% x 1.18
  461. odd::rt_alloc_excess_unused_size_99_align_32 20 17 -3 -15.00% x 1.18
  462. odd::rt_alloc_excess_unused_size_99_align_4 13 11 -2 -15.38% x 1.18
  463. odd::rt_alloc_excess_unused_size_99_align_8 14 11 -3 -21.43% x 1.27
  464. odd::rt_alloc_excess_unused_size_9_align_1 13 11 -2 -15.38% x 1.18
  465. odd::rt_alloc_excess_unused_size_9_align_16 20 17 -3 -15.00% x 1.18
  466. odd::rt_alloc_excess_unused_size_9_align_2 13 12 -1 -7.69% x 1.08
  467. odd::rt_alloc_excess_unused_size_9_align_32 20 17 -3 -15.00% x 1.18
  468. odd::rt_alloc_excess_unused_size_9_align_4 13 11 -2 -15.38% x 1.18
  469. odd::rt_alloc_excess_unused_size_9_align_8 13 11 -2 -15.38% x 1.18
  470. odd::rt_alloc_excess_used_size_999999_align_1 182 167 -15 -8.24% x 1.09
  471. odd::rt_alloc_excess_used_size_999999_align_16 183 167 -16 -8.74% x 1.10
  472. odd::rt_alloc_excess_used_size_999999_align_2 181 167 -14 -7.73% x 1.08
  473. odd::rt_alloc_excess_used_size_999999_align_32 182 167 -15 -8.24% x 1.09
  474. odd::rt_alloc_excess_used_size_999999_align_4 182 169 -13 -7.14% x 1.08
  475. odd::rt_alloc_excess_used_size_999999_align_8 182 167 -15 -8.24% x 1.09
  476. odd::rt_alloc_excess_used_size_99999_align_1 181 167 -14 -7.73% x 1.08
  477. odd::rt_alloc_excess_used_size_99999_align_16 183 167 -16 -8.74% x 1.10
  478. odd::rt_alloc_excess_used_size_99999_align_2 182 167 -15 -8.24% x 1.09
  479. odd::rt_alloc_excess_used_size_99999_align_32 183 167 -16 -8.74% x 1.10
  480. odd::rt_alloc_excess_used_size_99999_align_4 181 167 -14 -7.73% x 1.08
  481. odd::rt_alloc_excess_used_size_99999_align_8 182 167 -15 -8.24% x 1.09
  482. odd::rt_alloc_excess_used_size_9999_align_1 18 15 -3 -16.67% x 1.20
  483. odd::rt_alloc_excess_used_size_9999_align_16 18 15 -3 -16.67% x 1.20
  484. odd::rt_alloc_excess_used_size_9999_align_2 17 15 -2 -11.76% x 1.13
  485. odd::rt_alloc_excess_used_size_9999_align_32 24 21 -3 -12.50% x 1.14
  486. odd::rt_alloc_excess_used_size_9999_align_4 17 15 -2 -11.76% x 1.13
  487. odd::rt_alloc_excess_used_size_9999_align_8 18 15 -3 -16.67% x 1.20
  488. odd::rt_alloc_excess_used_size_999_align_1 13 11 -2 -15.38% x 1.18
  489. odd::rt_alloc_excess_used_size_999_align_16 14 11 -3 -21.43% x 1.27
  490. odd::rt_alloc_excess_used_size_999_align_2 13 11 -2 -15.38% x 1.18
  491. odd::rt_alloc_excess_used_size_999_align_32 20 17 -3 -15.00% x 1.18
  492. odd::rt_alloc_excess_used_size_999_align_4 13 11 -2 -15.38% x 1.18
  493. odd::rt_alloc_excess_used_size_999_align_8 13 11 -2 -15.38% x 1.18
  494. odd::rt_alloc_excess_used_size_99_align_1 13 11 -2 -15.38% x 1.18
  495. odd::rt_alloc_excess_used_size_99_align_16 13 12 -1 -7.69% x 1.08
  496. odd::rt_alloc_excess_used_size_99_align_2 13 11 -2 -15.38% x 1.18
  497. odd::rt_alloc_excess_used_size_99_align_32 20 17 -3 -15.00% x 1.18
  498. odd::rt_alloc_excess_used_size_99_align_4 13 11 -2 -15.38% x 1.18
  499. odd::rt_alloc_excess_used_size_99_align_8 13 11 -2 -15.38% x 1.18
  500. odd::rt_alloc_excess_used_size_9_align_1 13 11 -2 -15.38% x 1.18
  501. odd::rt_alloc_excess_used_size_9_align_16 20 17 -3 -15.00% x 1.18
  502. odd::rt_alloc_excess_used_size_9_align_2 13 11 -2 -15.38% x 1.18
  503. odd::rt_alloc_excess_used_size_9_align_32 21 17 -4 -19.05% x 1.24
  504. odd::rt_alloc_excess_used_size_9_align_4 13 11 -2 -15.38% x 1.18
  505. odd::rt_alloc_excess_used_size_9_align_8 13 11 -2 -15.38% x 1.18
  506. odd::rt_alloc_layout_checked_size_999999_align_1 177 165 -12 -6.78% x 1.07
  507. odd::rt_alloc_layout_checked_size_999999_align_16 180 167 -13 -7.22% x 1.08
  508. odd::rt_alloc_layout_checked_size_999999_align_2 178 164 -14 -7.87% x 1.09
  509. odd::rt_alloc_layout_checked_size_999999_align_32 178 166 -12 -6.74% x 1.07
  510. odd::rt_alloc_layout_checked_size_999999_align_4 177 164 -13 -7.34% x 1.08
  511. odd::rt_alloc_layout_checked_size_999999_align_8 181 163 -18 -9.94% x 1.11
  512. odd::rt_alloc_layout_checked_size_99999_align_1 179 166 -13 -7.26% x 1.08
  513. odd::rt_alloc_layout_checked_size_99999_align_16 178 164 -14 -7.87% x 1.09
  514. odd::rt_alloc_layout_checked_size_99999_align_2 177 164 -13 -7.34% x 1.08
  515. odd::rt_alloc_layout_checked_size_99999_align_32 178 164 -14 -7.87% x 1.09
  516. odd::rt_alloc_layout_checked_size_99999_align_4 179 163 -16 -8.94% x 1.10
  517. odd::rt_alloc_layout_checked_size_99999_align_8 178 163 -15 -8.43% x 1.09
  518. odd::rt_alloc_layout_checked_size_9999_align_1 14 12 -2 -14.29% x 1.17
  519. odd::rt_alloc_layout_checked_size_9999_align_16 14 12 -2 -14.29% x 1.17
  520. odd::rt_alloc_layout_checked_size_9999_align_2 14 12 -2 -14.29% x 1.17
  521. odd::rt_alloc_layout_checked_size_9999_align_32 20 18 -2 -10.00% x 1.11
  522. odd::rt_alloc_layout_checked_size_9999_align_4 14 12 -2 -14.29% x 1.17
  523. odd::rt_alloc_layout_checked_size_9999_align_8 14 12 -2 -14.29% x 1.17
  524. odd::rt_alloc_layout_checked_size_999_align_1 11 9 -2 -18.18% x 1.22
  525. odd::rt_alloc_layout_checked_size_999_align_16 11 9 -2 -18.18% x 1.22
  526. odd::rt_alloc_layout_checked_size_999_align_2 11 9 -2 -18.18% x 1.22
  527. odd::rt_alloc_layout_checked_size_999_align_32 17 14 -3 -17.65% x 1.21
  528. odd::rt_alloc_layout_checked_size_999_align_4 11 9 -2 -18.18% x 1.22
  529. odd::rt_alloc_layout_checked_size_999_align_8 11 9 -2 -18.18% x 1.22
  530. odd::rt_alloc_layout_checked_size_99_align_1 11 9 -2 -18.18% x 1.22
  531. odd::rt_alloc_layout_checked_size_99_align_16 11 9 -2 -18.18% x 1.22
  532. odd::rt_alloc_layout_checked_size_99_align_2 11 9 -2 -18.18% x 1.22
  533. odd::rt_alloc_layout_checked_size_99_align_32 17 14 -3 -17.65% x 1.21
  534. odd::rt_alloc_layout_checked_size_99_align_4 11 9 -2 -18.18% x 1.22
  535. odd::rt_alloc_layout_checked_size_99_align_8 11 9 -2 -18.18% x 1.22
  536. odd::rt_alloc_layout_checked_size_9_align_1 11 9 -2 -18.18% x 1.22
  537. odd::rt_alloc_layout_checked_size_9_align_16 16 14 -2 -12.50% x 1.14
  538. odd::rt_alloc_layout_checked_size_9_align_2 11 9 -2 -18.18% x 1.22
  539. odd::rt_alloc_layout_checked_size_9_align_32 17 14 -3 -17.65% x 1.21
  540. odd::rt_alloc_layout_checked_size_9_align_4 11 9 -2 -18.18% x 1.22
  541. odd::rt_alloc_layout_checked_size_9_align_8 11 9 -2 -18.18% x 1.22
  542. odd::rt_alloc_layout_unchecked_size_999999_align_1 178 172 -6 -3.37% x 1.03
  543. odd::rt_alloc_layout_unchecked_size_999999_align_16 181 164 -17 -9.39% x 1.10
  544. odd::rt_alloc_layout_unchecked_size_999999_align_2 178 164 -14 -7.87% x 1.09
  545. odd::rt_alloc_layout_unchecked_size_999999_align_32 178 164 -14 -7.87% x 1.09
  546. odd::rt_alloc_layout_unchecked_size_999999_align_4 177 163 -14 -7.91% x 1.09
  547. odd::rt_alloc_layout_unchecked_size_999999_align_8 177 166 -11 -6.21% x 1.07
  548. odd::rt_alloc_layout_unchecked_size_99999_align_1 177 359 182 102.82% x 0.49
  549. odd::rt_alloc_layout_unchecked_size_99999_align_16 177 164 -13 -7.34% x 1.08
  550. odd::rt_alloc_layout_unchecked_size_99999_align_2 178 164 -14 -7.87% x 1.09
  551. odd::rt_alloc_layout_unchecked_size_99999_align_32 177 163 -14 -7.91% x 1.09
  552. odd::rt_alloc_layout_unchecked_size_99999_align_4 176 166 -10 -5.68% x 1.06
  553. odd::rt_alloc_layout_unchecked_size_99999_align_8 177 164 -13 -7.34% x 1.08
  554. odd::rt_alloc_layout_unchecked_size_9999_align_1 14 12 -2 -14.29% x 1.17
  555. odd::rt_alloc_layout_unchecked_size_9999_align_16 14 12 -2 -14.29% x 1.17
  556. odd::rt_alloc_layout_unchecked_size_9999_align_2 14 12 -2 -14.29% x 1.17
  557. odd::rt_alloc_layout_unchecked_size_9999_align_32 20 18 -2 -10.00% x 1.11
  558. odd::rt_alloc_layout_unchecked_size_9999_align_4 14 12 -2 -14.29% x 1.17
  559. odd::rt_alloc_layout_unchecked_size_9999_align_8 14 12 -2 -14.29% x 1.17
  560. odd::rt_alloc_layout_unchecked_size_999_align_1 11 9 -2 -18.18% x 1.22
  561. odd::rt_alloc_layout_unchecked_size_999_align_16 11 9 -2 -18.18% x 1.22
  562. odd::rt_alloc_layout_unchecked_size_999_align_2 11 9 -2 -18.18% x 1.22
  563. odd::rt_alloc_layout_unchecked_size_999_align_32 17 14 -3 -17.65% x 1.21
  564. odd::rt_alloc_layout_unchecked_size_999_align_4 11 9 -2 -18.18% x 1.22
  565. odd::rt_alloc_layout_unchecked_size_999_align_8 11 9 -2 -18.18% x 1.22
  566. odd::rt_alloc_layout_unchecked_size_99_align_1 11 9 -2 -18.18% x 1.22
  567. odd::rt_alloc_layout_unchecked_size_99_align_16 11 9 -2 -18.18% x 1.22
  568. odd::rt_alloc_layout_unchecked_size_99_align_2 11 9 -2 -18.18% x 1.22
  569. odd::rt_alloc_layout_unchecked_size_99_align_32 17 14 -3 -17.65% x 1.21
  570. odd::rt_alloc_layout_unchecked_size_99_align_4 11 9 -2 -18.18% x 1.22
  571. odd::rt_alloc_layout_unchecked_size_99_align_8 11 9 -2 -18.18% x 1.22
  572. odd::rt_alloc_layout_unchecked_size_9_align_1 11 9 -2 -18.18% x 1.22
  573. odd::rt_alloc_layout_unchecked_size_9_align_16 16 15 -1 -6.25% x 1.07
  574. odd::rt_alloc_layout_unchecked_size_9_align_2 11 9 -2 -18.18% x 1.22
  575. odd::rt_alloc_layout_unchecked_size_9_align_32 17 14 -3 -17.65% x 1.21
  576. odd::rt_alloc_layout_unchecked_size_9_align_4 11 9 -2 -18.18% x 1.22
  577. odd::rt_alloc_layout_unchecked_size_9_align_8 11 9 -2 -18.18% x 1.22
  578. odd::rt_calloc_size_999999_align_1 912 917 5 0.55% x 0.99
  579. odd::rt_calloc_size_999999_align_16 919 899 -20 -2.18% x 1.02
  580. odd::rt_calloc_size_999999_align_2 919 923 4 0.44% x 1.00
  581. odd::rt_calloc_size_999999_align_32 909 900 -9 -0.99% x 1.01
  582. odd::rt_calloc_size_999999_align_4 930 891 -39 -4.19% x 1.04
  583. odd::rt_calloc_size_999999_align_8 923 892 -31 -3.36% x 1.03
  584. odd::rt_calloc_size_99999_align_1 4,969 4,771 -198 -3.98% x 1.04
  585. odd::rt_calloc_size_99999_align_16 4,889 4,656 -233 -4.77% x 1.05
  586. odd::rt_calloc_size_99999_align_2 4,989 4,793 -196 -3.93% x 1.04
  587. odd::rt_calloc_size_99999_align_32 5,015 4,681 -334 -6.66% x 1.07
  588. odd::rt_calloc_size_99999_align_4 4,980 4,711 -269 -5.40% x 1.06
  589. odd::rt_calloc_size_99999_align_8 4,922 4,620 -302 -6.14% x 1.07
  590. odd::rt_calloc_size_9999_align_1 60 55 -5 -8.33% x 1.09
  591. odd::rt_calloc_size_9999_align_16 60 56 -4 -6.67% x 1.07
  592. odd::rt_calloc_size_9999_align_2 60 57 -3 -5.00% x 1.05
  593. odd::rt_calloc_size_9999_align_32 61 55 -6 -9.84% x 1.11
  594. odd::rt_calloc_size_9999_align_4 60 56 -4 -6.67% x 1.07
  595. odd::rt_calloc_size_9999_align_8 59 56 -3 -5.08% x 1.05
  596. odd::rt_calloc_size_999_align_1 19 18 -1 -5.26% x 1.06
  597. odd::rt_calloc_size_999_align_16 19 18 -1 -5.26% x 1.06
  598. odd::rt_calloc_size_999_align_2 19 18 -1 -5.26% x 1.06
  599. odd::rt_calloc_size_999_align_32 19 19 0 0.00% x 1.00
  600. odd::rt_calloc_size_999_align_4 19 19 0 0.00% x 1.00
  601. odd::rt_calloc_size_999_align_8 19 18 -1 -5.26% x 1.06
  602. odd::rt_calloc_size_99_align_1 12 10 -2 -16.67% x 1.20
  603. odd::rt_calloc_size_99_align_16 12 10 -2 -16.67% x 1.20
  604. odd::rt_calloc_size_99_align_2 12 9 -3 -25.00% x 1.33
  605. odd::rt_calloc_size_99_align_32 12 9 -3 -25.00% x 1.33
  606. odd::rt_calloc_size_99_align_4 12 10 -2 -16.67% x 1.20
  607. odd::rt_calloc_size_99_align_8 12 10 -2 -16.67% x 1.20
  608. odd::rt_calloc_size_9_align_1 13 10 -3 -23.08% x 1.30
  609. odd::rt_calloc_size_9_align_16 12 10 -2 -16.67% x 1.20
  610. odd::rt_calloc_size_9_align_2 12 10 -2 -16.67% x 1.20
  611. odd::rt_calloc_size_9_align_32 12 10 -2 -16.67% x 1.20
  612. odd::rt_calloc_size_9_align_4 12 10 -2 -16.67% x 1.20
  613. odd::rt_calloc_size_9_align_8 12 10 -2 -16.67% x 1.20
  614. odd::rt_mallocx_nallocx_size_999999_align_1 181 171 -10 -5.52% x 1.06
  615. odd::rt_mallocx_nallocx_size_999999_align_16 180 167 -13 -7.22% x 1.08
  616. odd::rt_mallocx_nallocx_size_999999_align_2 182 167 -15 -8.24% x 1.09
  617. odd::rt_mallocx_nallocx_size_999999_align_32 184 174 -10 -5.43% x 1.06
  618. odd::rt_mallocx_nallocx_size_999999_align_4 182 171 -11 -6.04% x 1.06
  619. odd::rt_mallocx_nallocx_size_999999_align_8 182 168 -14 -7.69% x 1.08
  620. odd::rt_mallocx_nallocx_size_99999_align_1 183 168 -15 -8.20% x 1.09
  621. odd::rt_mallocx_nallocx_size_99999_align_16 183 170 -13 -7.10% x 1.08
  622. odd::rt_mallocx_nallocx_size_99999_align_2 181 171 -10 -5.52% x 1.06
  623. odd::rt_mallocx_nallocx_size_99999_align_32 182 177 -5 -2.75% x 1.03
  624. odd::rt_mallocx_nallocx_size_99999_align_4 182 170 -12 -6.59% x 1.07
  625. odd::rt_mallocx_nallocx_size_99999_align_8 180 175 -5 -2.78% x 1.03
  626. odd::rt_mallocx_nallocx_size_9999_align_1 16 15 -1 -6.25% x 1.07
  627. odd::rt_mallocx_nallocx_size_9999_align_16 16 15 -1 -6.25% x 1.07
  628. odd::rt_mallocx_nallocx_size_9999_align_2 16 15 -1 -6.25% x 1.07
  629. odd::rt_mallocx_nallocx_size_9999_align_32 22 22 0 0.00% x 1.00
  630. odd::rt_mallocx_nallocx_size_9999_align_4 16 15 -1 -6.25% x 1.07
  631. odd::rt_mallocx_nallocx_size_9999_align_8 16 15 -1 -6.25% x 1.07
  632. odd::rt_mallocx_nallocx_size_999_align_1 12 11 -1 -8.33% x 1.09
  633. odd::rt_mallocx_nallocx_size_999_align_16 12 11 -1 -8.33% x 1.09
  634. odd::rt_mallocx_nallocx_size_999_align_2 12 11 -1 -8.33% x 1.09
  635. odd::rt_mallocx_nallocx_size_999_align_32 19 17 -2 -10.53% x 1.12
  636. odd::rt_mallocx_nallocx_size_999_align_4 12 11 -1 -8.33% x 1.09
  637. odd::rt_mallocx_nallocx_size_999_align_8 13 11 -2 -15.38% x 1.18
  638. odd::rt_mallocx_nallocx_size_99_align_1 12 11 -1 -8.33% x 1.09
  639. odd::rt_mallocx_nallocx_size_99_align_16 12 11 -1 -8.33% x 1.09
  640. odd::rt_mallocx_nallocx_size_99_align_2 12 11 -1 -8.33% x 1.09
  641. odd::rt_mallocx_nallocx_size_99_align_32 18 17 -1 -5.56% x 1.06
  642. odd::rt_mallocx_nallocx_size_99_align_4 12 12 0 0.00% x 1.00
  643. odd::rt_mallocx_nallocx_size_99_align_8 12 11 -1 -8.33% x 1.09
  644. odd::rt_mallocx_nallocx_size_9_align_1 12 12 0 0.00% x 1.00
  645. odd::rt_mallocx_nallocx_size_9_align_16 18 17 -1 -5.56% x 1.06
  646. odd::rt_mallocx_nallocx_size_9_align_2 12 11 -1 -8.33% x 1.09
  647. odd::rt_mallocx_nallocx_size_9_align_32 18 18 0 0.00% x 1.00
  648. odd::rt_mallocx_nallocx_size_9_align_4 13 11 -2 -15.38% x 1.18
  649. odd::rt_mallocx_nallocx_size_9_align_8 12 11 -1 -8.33% x 1.09
  650. odd::rt_mallocx_size_999999_align_1 177 164 -13 -7.34% x 1.08
  651. odd::rt_mallocx_size_999999_align_16 176 164 -12 -6.82% x 1.07
  652. odd::rt_mallocx_size_999999_align_2 177 164 -13 -7.34% x 1.08
  653. odd::rt_mallocx_size_999999_align_32 177 164 -13 -7.34% x 1.08
  654. odd::rt_mallocx_size_999999_align_4 175 164 -11 -6.29% x 1.07
  655. odd::rt_mallocx_size_999999_align_8 177 165 -12 -6.78% x 1.07
  656. odd::rt_mallocx_size_99999_align_1 179 168 -11 -6.15% x 1.07
  657. odd::rt_mallocx_size_99999_align_16 177 164 -13 -7.34% x 1.08
  658. odd::rt_mallocx_size_99999_align_2 179 166 -13 -7.26% x 1.08
  659. odd::rt_mallocx_size_99999_align_32 180 173 -7 -3.89% x 1.04
  660. odd::rt_mallocx_size_99999_align_4 180 164 -16 -8.89% x 1.10
  661. odd::rt_mallocx_size_99999_align_8 177 164 -13 -7.34% x 1.08
  662. odd::rt_mallocx_size_9999_align_1 13 12 -1 -7.69% x 1.08
  663. odd::rt_mallocx_size_9999_align_16 13 12 -1 -7.69% x 1.08
  664. odd::rt_mallocx_size_9999_align_2 13 12 -1 -7.69% x 1.08
  665. odd::rt_mallocx_size_9999_align_32 19 18 -1 -5.26% x 1.06
  666. odd::rt_mallocx_size_9999_align_4 13 12 -1 -7.69% x 1.08
  667. odd::rt_mallocx_size_9999_align_8 13 12 -1 -7.69% x 1.08
  668. odd::rt_mallocx_size_999_align_1 10 9 -1 -10.00% x 1.11
  669. odd::rt_mallocx_size_999_align_16 10 9 -1 -10.00% x 1.11
  670. odd::rt_mallocx_size_999_align_2 10 9 -1 -10.00% x 1.11
  671. odd::rt_mallocx_size_999_align_32 15 14 -1 -6.67% x 1.07
  672. odd::rt_mallocx_size_999_align_4 10 9 -1 -10.00% x 1.11
  673. odd::rt_mallocx_size_999_align_8 10 9 -1 -10.00% x 1.11
  674. odd::rt_mallocx_size_99_align_1 10 9 -1 -10.00% x 1.11
  675. odd::rt_mallocx_size_99_align_16 10 9 -1 -10.00% x 1.11
  676. odd::rt_mallocx_size_99_align_2 10 9 -1 -10.00% x 1.11
  677. odd::rt_mallocx_size_99_align_32 15 14 -1 -6.67% x 1.07
  678. odd::rt_mallocx_size_99_align_4 10 9 -1 -10.00% x 1.11
  679. odd::rt_mallocx_size_99_align_8 10 9 -1 -10.00% x 1.11
  680. odd::rt_mallocx_size_9_align_1 10 9 -1 -10.00% x 1.11
  681. odd::rt_mallocx_size_9_align_16 15 14 -1 -6.67% x 1.07
  682. odd::rt_mallocx_size_9_align_2 10 9 -1 -10.00% x 1.11
  683. odd::rt_mallocx_size_9_align_32 15 14 -1 -6.67% x 1.07
  684. odd::rt_mallocx_size_9_align_4 10 9 -1 -10.00% x 1.11
  685. odd::rt_mallocx_size_9_align_8 10 9 -1 -10.00% x 1.11
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