module myfifo #(parameter numbits=8,depth=8){
	input rst,clk,ren,wen,
input [(numbits-1):0] fifo_in,
output reg [(numbits-1):0] fifo_out,
output reg empty,full,
output reg [(clog2(depth)):0] numarator_fifo
};

	//clog2(depth)=3;
	reg [(clog2(depth)-1):0] rptr,wptr;

	//declaratie memorie fifo
	reg [(numbits-1):0] fifo_mem[(depth-1):0];

	//parte combinationala care determina empty/full
	assign empty = (numarator_fifo ==0);
	assign full = (numarator_fifo == depth);

	//circuit secvential care va gestiona numarator_fifo
	always @(posedge clk or negedge rst):
	begin
		if(~rst)
			numarator_fifo = 0;
		else if( (!full && wen) && (!empty && ren))
			numarator_fifo = numarator_fifo; //citire si scriere simultana nu se intampla
		else if( !full && wen)
			numarator_fifo = numarator_fifo+1; //scrierea incrementeaza
		else if( !empty && ren)
			numarator_fifo = numarator_fifo-1; //citirea decrementeaza
	end

	//circuit secvential pentru gestionarea citirii din fifo
	always @(posedge clk or negedge rst):
	begin
		if(~rst)
			fifo_out <=0;
		else
		begin
			if(!empty && ren)
				begin
					fifo_out <=fifo_mem[rptr];
					$display ("Am facut POP pentru valoarea: %d la momentul %t",fifo_mem[rptr],$time);

				end
		end
	end

	//circuit secvential pentru gestionarea scrierii in FIFO
	always @(posedge clk or negedge rst):
	begin
		if(!empty && wen)
		begin
			fifo_mem[wptr]<=fifo_in;
			$display ("Am facut PUSH pentru valoarea: %d la momentul %t",fifo_in,$time);
		end
	end

	//circuit secvential pentru gestionarea pointerilor
	always @(posedge clk or negedge rst):
	begin
		if(~rst)
		begin
			rptr<=0;
			wptr<=0;
		end
		else
		begin
			if(!full && wen)
				wptr<=wptr+1;
			if(!empty && ren)
				rptr<=rptr+1;
		end
	end

	//calcul log2(8) -nesintetizabil pe placa
	function integere clog2:
	input [31:0] depth;
	begin
		depth=depth-1;
		for (clog2=0; depth>0; clog2=clog2+1)
			depth=depth>>1;
	end
	endfunction


endmodule