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Matisse SMUIO Block

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Jan 20th, 2021
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  1. - BLOCK_NAME: 'SMUIO'
  2. - DESCRIPTION: 'SMUIO Block SMUSVI registers'
  3.  
  4. Registers:
  5. PWR_OVERRIDE (smn_addr_map:0x5a30c,iod_smn_addr_map:0x5a30c) 32bit:
  6. 0 VDDCR_VDD_OVERRIDE
  7.  
  8. SMUIO_FORCE_SELFREFRESH (smn_addr_map:0x5a314,iod_smn_addr_map:0x5a314) 32bit:
  9. 0 PU
  10. 1 PD
  11. 2 OE
  12. 3 TXIMPSEL
  13. 4 RXSEL1
  14. 5 RXSEL0
  15. 6 RXEN
  16. 7 A
  17. 8 Y(R)
  18.  
  19. SMUIO_MCM_CONFIG (smn_addr_map:0x5a08c,iod_smn_addr_map:0x5a08c) 32bit:
  20. 1:0 DIE_ID(R)
  21. 4:2 PKG_TYPE
  22. 5 SOCKET_ID(R)
  23. 7:6 PKG_SUBTYPE
  24.  
  25. SMUIO_MP_RESET_INTR (smn_addr_map:0x5a304,iod_smn_addr_map:0x5a304) 32bit:
  26. 0 SMUIO_MP_RESET_INTR(R)
  27.  
  28. SMUIO_NV_SAVE_N (smn_addr_map:0x5a310,iod_smn_addr_map:0x5a310) 32bit:
  29. 0 PU
  30. 1 PD
  31. 2 S0
  32. 3 S1
  33. 4 OE_OVERRIDE
  34. 5 OE
  35. 6 A_OVERRIDE
  36. 7 A
  37. 8 SCHMEN
  38. 9 Y(R)
  39.  
  40. SMUIO_PWRMGT (smn_addr_map:0x5a31c,iod_smn_addr_map:0x5a31c) 32bit:
  41. 0 i2c_clk_gate_en
  42. 4 i2c1_clk_gate_en
  43.  
  44. SMUIO_RESET_DELAY (smn_addr_map:0x5a318,iod_smn_addr_map:0x5a318) 32bit:
  45. 15:0 SMUIO_RESET_DELAY
  46.  
  47. SMUIO_RESET_SEL (smn_addr_map:0x5a300,iod_smn_addr_map:0x5a300) 32bit:
  48. 0 SMUIO_RESET_SEL
  49.  
  50. SMUIO_SOC_HALT (smn_addr_map:0x5a308,iod_smn_addr_map:0x5a308) 32bit:
  51. 2 WDT_FORCE_PWROK_EN
  52. 3 WDT_FORCE_RESETn_EN
  53.  
  54. SMUSVI0_MISC_VID_STATUS (smn_addr_map:0x5a028,iod_smn_addr_map:0x5a028) 32bit:
  55. 7:0 MAX_VID(R)
  56. 17:10 MIN_VID(R)
  57. 30:23 SVI0_PLANE0_PSI_VID
  58. 31 SVI0_PLANE0_PSI_VID_EN
  59.  
  60. SMUSVI0_PLANE0_CURRENTVID (smn_addr_map:0x5a050,iod_smn_addr_map:0x5a050) 32bit (R):
  61. 31:24 CURRENT_SVI0_PLANE0_VID
  62.  
  63. SMUSVI0_PLANE0_LOAD (smn_addr_map:0x5a004,iod_smn_addr_map:0x5a004) 32bit:
  64. 4:0 SVI0_LOADLINE_PLANE0
  65. 5 SVI0_PSI1_PLANE0
  66.  
  67. SMUSVI0_PLANE0_TEL_IDD_SUM (smn_addr_map:0x5a0a4,iod_smn_addr_map:0x5a0a4) 32bit (R):
  68. 17:0 SVI0_PLANE0_TEL_IDD_SUM
  69.  
  70. SMUSVI0_PLANE0_TEL_MAX (smn_addr_map:0x5a0b0,iod_smn_addr_map:0x5a0b0) 32bit (R):
  71. 7:0 SVI0_PLANE0_TEL_IDD_MAX
  72. 24:16 SVI0_PLANE0_TEL_VDD_MAX
  73.  
  74. SMUSVI0_PLANE0_TEL_MIN (smn_addr_map:0x5a0ac,iod_smn_addr_map:0x5a0ac) 32bit (R):
  75. 7:0 SVI0_PLANE0_TEL_IDD_MIN
  76. 24:16 SVI0_PLANE0_TEL_VDD_MIN
  77.  
  78. SMUSVI0_PLANE0_TEL_SAMPLE_CNT (smn_addr_map:0x5a0a0,iod_smn_addr_map:0x5a0a0) 32bit (R):
  79. 9:0 SVI0_PLANE0_TEL_SAMPLE_CNT
  80.  
  81. SMUSVI0_PLANE0_TEL_VDD_SUM (smn_addr_map:0x5a0a8,iod_smn_addr_map:0x5a0a8) 32bit (R):
  82. 18:0 SVI0_PLANE0_TEL_VDD_SUM
  83.  
  84. SMUSVI0_PLANE0_VIDCHGBUSY (smn_addr_map:0x5a040,iod_smn_addr_map:0x5a040) 32bit (R):
  85. 0 SVI0_PLANE0_VID_CHGBUSY
  86.  
  87. SMUSVI0_PLANE1_CURRENTVID (smn_addr_map:0x5a058,iod_smn_addr_map:0x5a058) 32bit (R):
  88. 31:24 CURRENT_SVI0_PLANE1_VID
  89.  
  90. SMUSVI0_PLANE1_LOAD (smn_addr_map:0x5a000,iod_smn_addr_map:0x5a000) 32bit:
  91. 4:0 SVI0_LOADLINE_PLANE1
  92. 5 SVI0_PSI1_PLANE1
  93. 8 SIDEBAND_PLANE0_CHGVID_EN
  94. 12 SIDEBAND_PLANE1_CHGVID_EN
  95. 16 SVI0_PLANE0_SIDEBAND_VID_CHGBUSY(R)
  96. 20 SVI0_PLANE1_SIDEBAND_VID_CHGBUSY(R)
  97. 24 SVI1_PLANE0_SIDEBAND_VID_CHGBUSY(R)
  98. 25 SVI1_PLANE1_SIDEBAND_VID_CHGBUSY(R)
  99. 26 SIDEBAND_OUTSTD_EN
  100. 29 WAITVIDCOMPDIS_SVI0
  101. 30 WAITVIDCOMPDIS_SVI1
  102. 31 SVIBUSY(R)
  103.  
  104. SMUSVI0_PLANE1_TEL_IDD_SUM (smn_addr_map:0x5a0b8,iod_smn_addr_map:0x5a0b8) 32bit (R):
  105. 17:0 SVI0_PLANE1_TEL_IDD_SUM
  106.  
  107. SMUSVI0_PLANE1_TEL_MAX (smn_addr_map:0x5a0c4,iod_smn_addr_map:0x5a0c4) 32bit (R):
  108. 7:0 SVI0_PLANE1_TEL_IDD_MAX
  109. 24:16 SVI0_PLANE1_TEL_VDD_MAX
  110.  
  111. SMUSVI0_PLANE1_TEL_MIN (smn_addr_map:0x5a0c0,iod_smn_addr_map:0x5a0c0) 32bit (R):
  112. 7:0 SVI0_PLANE1_TEL_IDD_MIN
  113. 24:16 SVI0_PLANE1_TEL_VDD_MIN
  114.  
  115. SMUSVI0_PLANE1_TEL_SAMPLE_CNT (smn_addr_map:0x5a0b4,iod_smn_addr_map:0x5a0b4) 32bit (R):
  116. 9:0 SVI0_PLANE1_TEL_SAMPLE_CNT
  117.  
  118. SMUSVI0_PLANE1_TEL_VDD_SUM (smn_addr_map:0x5a0bc,iod_smn_addr_map:0x5a0bc) 32bit (R):
  119. 18:0 SVI0_PLANE1_TEL_VDD_SUM
  120.  
  121. SMUSVI0_PLANE1_VIDCHGBUSY (smn_addr_map:0x5a044,iod_smn_addr_map:0x5a044) 32bit (R):
  122. 0 SVI0_PLANE1_VID_CHGBUSY
  123.  
  124. SMUSVI0_PLANE_VIDCHG (smn_addr_map:0x5a030,iod_smn_addr_map:0x5a030) 32bit:
  125. 1:0 SVI0_VIDPLANE
  126. 5 SVI0_VIDCHGZEROVID
  127. 6 SVI0_VIDCHGRAMP
  128. 9:7 SVI0_VSTIME
  129. 23:16 SVI0_VID
  130.  
  131. SMUSVI0_PWR_CTL_MISC (smn_addr_map:0x5a02c,iod_smn_addr_map:0x5a02c) 32bit:
  132. 6:0 SVI0_PLANE1_PSIVID
  133. 7 SVI0_PLANE1_PSIVIDEN
  134. 8 SVI0_PLANE1_PSIVID_HI
  135. 14 HIGHFREQSEL_SVI0
  136. 15 HIGHFREQSEL_SVI1
  137. 16 SVI0_SAMPLE_SVT_DLY_SEL
  138. 20 SVI1_SAMPLE_SVT_DLY_SEL
  139.  
  140. SMUSVI0_TEL_PLANE0 (smn_addr_map:0x5a010,iod_smn_addr_map:0x5a010) 32bit (R):
  141. 7:0 SVI0_PLANE0_IDDCOR
  142. 24:16 SVI0_PLANE0_VDDCOR
  143.  
  144. SMUSVI0_TEL_PLANE1 (smn_addr_map:0x5a00c,iod_smn_addr_map:0x5a00c) 32bit (R):
  145. 7:0 SVI0_PLANE1_IDDCOR
  146. 24:16 SVI0_PLANE1_VDDCOR
  147.  
  148. SMUSVI0_TFN (smn_addr_map:0x5a008,iod_smn_addr_map:0x5a008) 32bit:
  149. 0 SVI0_TFN_PLANE0
  150. 1 SVI0_TFN_PLANE1
  151.  
  152. SMUSVI1_LOAD (smn_addr_map:0x5a01c,iod_smn_addr_map:0x5a01c) 32bit:
  153. 4:0 SVI1_LOADLINE_PLANE0
  154. 8 SVI1_PSI1_PLANE0
  155. 16:12 SVI1_LOADLINE_PLANE1
  156. 20 SVI1_PSI1_PLANE1
  157. 31 SVIBUSY1(R)
  158.  
  159. SMUSVI1_PLANE0_CURRENTVID (smn_addr_map:0x5a054,iod_smn_addr_map:0x5a054) 32bit (R):
  160. 31:24 CURRENT_SVI1_PLANE0_VID
  161.  
  162. SMUSVI1_PLANE0_TEL_IDD_SUM (smn_addr_map:0x5a0cc,iod_smn_addr_map:0x5a0cc) 32bit (R):
  163. 17:0 SVI1_PLANE0_TEL_IDD_SUM
  164.  
  165. SMUSVI1_PLANE0_TEL_MAX (smn_addr_map:0x5a0d8,iod_smn_addr_map:0x5a0d8) 32bit (R):
  166. 7:0 SVI1_PLANE0_TEL_IDD_MAX
  167. 24:16 SVI1_PLANE0_TEL_VDD_MAX
  168.  
  169. SMUSVI1_PLANE0_TEL_MIN (smn_addr_map:0x5a0d4,iod_smn_addr_map:0x5a0d4) 32bit (R):
  170. 7:0 SVI1_PLANE0_TEL_IDD_MIN
  171. 24:16 SVI1_PLANE0_TEL_VDD_MIN
  172.  
  173. SMUSVI1_PLANE0_TEL_SAMPLE_CNT (smn_addr_map:0x5a0c8,iod_smn_addr_map:0x5a0c8) 32bit (R):
  174. 9:0 SVI1_PLANE0_TEL_SAMPLE_CNT
  175.  
  176. SMUSVI1_PLANE0_TEL_VDD_SUM (smn_addr_map:0x5a0d0,iod_smn_addr_map:0x5a0d0) 32bit (R):
  177. 18:0 SVI1_PLANE0_TEL_VDD_SUM
  178.  
  179. SMUSVI1_PLANE0_VIDCHGBUSY (smn_addr_map:0x5a048,iod_smn_addr_map:0x5a048) 32bit (R):
  180. 0 SVI1_PLANE0_VID_CHGBUSY
  181.  
  182. SMUSVI1_PLANE1_CURRENTVID (smn_addr_map:0x5a05c,iod_smn_addr_map:0x5a05c) 32bit (R):
  183. 31:24 CURRENT_SVI1_PLANE1_VID
  184.  
  185. SMUSVI1_PLANE1_TEL_IDD_SUM (smn_addr_map:0x5a0e0,iod_smn_addr_map:0x5a0e0) 32bit (R):
  186. 17:0 SVI1_PLANE1_TEL_IDD_SUM
  187.  
  188. SMUSVI1_PLANE1_TEL_MAX (smn_addr_map:0x5a0ec,iod_smn_addr_map:0x5a0ec) 32bit (R):
  189. 7:0 SVI1_PLANE1_TEL_IDD_MAX
  190. 24:16 SVI1_PLANE1_TEL_VDD_MAX
  191.  
  192. SMUSVI1_PLANE1_TEL_MIN (smn_addr_map:0x5a0e8,iod_smn_addr_map:0x5a0e8) 32bit (R):
  193. 7:0 SVI1_PLANE1_TEL_IDD_MIN
  194. 24:16 SVI1_PLANE1_TEL_VDD_MIN
  195.  
  196. SMUSVI1_PLANE1_TEL_SAMPLE_CNT (smn_addr_map:0x5a0dc,iod_smn_addr_map:0x5a0dc) 32bit (R):
  197. 9:0 SVI1_PLANE1_TEL_SAMPLE_CNT
  198.  
  199. SMUSVI1_PLANE1_TEL_VDD_SUM (smn_addr_map:0x5a0e4,iod_smn_addr_map:0x5a0e4) 32bit (R):
  200. 18:0 SVI1_PLANE1_TEL_VDD_SUM
  201.  
  202. SMUSVI1_PLANE1_VIDCHGBUSY (smn_addr_map:0x5a04c,iod_smn_addr_map:0x5a04c) 32bit (R):
  203. 0 SVI1_PLANE1_VID_CHGBUSY
  204.  
  205. SMUSVI1_PLANE_VIDCHG (smn_addr_map:0x5a034,iod_smn_addr_map:0x5a034) 32bit:
  206. 1:0 SVI1_VIDPLANE
  207. 5 SVI1_VIDCHGZEROVID
  208. 6 SVI1_VIDCHGRAMP
  209. 9:7 SVI1_VSTIME
  210. 23:16 SVI1_VID
  211.  
  212. SMUSVI1_PSI0 (smn_addr_map:0x5a024,iod_smn_addr_map:0x5a024) 32bit:
  213. 7:0 SVI1_PLANE0_PSI_VID
  214. 8 SVI1_PLANE0_PSI_VID_EN
  215. 19:12 SVI1_PLANE1_PSI_VID
  216. 20 SVI1_PLANE1_PSI_VID_EN
  217.  
  218. SMUSVI1_TEL_PLANE0 (smn_addr_map:0x5a014,iod_smn_addr_map:0x5a014) 32bit (R):
  219. 7:0 SVI1_PLANE0_IDDCOR
  220. 24:16 SVI1_PLANE0_VDDCOR
  221.  
  222. SMUSVI1_TEL_PLANE1 (smn_addr_map:0x5a018,iod_smn_addr_map:0x5a018) 32bit (R):
  223. 7:0 SVI1_PLANE1_IDDCOR
  224. 24:16 SVI1_PLANE1_VDDCOR
  225.  
  226. SMUSVI1_TFN (smn_addr_map:0x5a020,iod_smn_addr_map:0x5a020) 32bit:
  227. 0 SVI1_TFN_PLANE0
  228. 1 SVI1_TFN_PLANE1
  229.  
  230. SMUSVI_ALL_CPU_IN_CC6 (smn_addr_map:0x5a060,iod_smn_addr_map:0x5a060) 32bit:
  231. 0 ALL_CPU_IN_CC6
  232.  
  233. SMUSVI_BOOTVID (smn_addr_map:0x5a064,iod_smn_addr_map:0x5a064) 32bit (R):
  234. 0 BOOTSVD_VR0
  235. 1 BOOTSVC_VR0
  236. 2 BOOTSVD_VR1
  237. 3 BOOTSVC_VR1
  238. 8 SVI0_PLANE1_STARTUP_COMPL_EN
  239. 9 SVI0_PLANE0_STARTUP_COMPL_EN
  240. 10 SVI1_PLANE0_STARTUP_COMPL_EN
  241. 11 SVI1_PLANE1_STARTUP_COMPL_EN
  242.  
  243. SMUSVI_PLANE_MAP (smn_addr_map:0x5a090,iod_smn_addr_map:0x5a090) 32bit:
  244. 1:0 SVI0_PLANE0_MAP
  245. 5:4 SVI0_PLANE1_MAP
  246. 9:8 SVI1_PLANE0_MAP
  247. 13:12 SVI1_PLANE1_MAP
  248.  
  249. SMUSVI_PLANE_USAGE (smn_addr_map:0x5a088,iod_smn_addr_map:0x5a088) 32bit:
  250. 0 SVI0_PLANE0_USAGE
  251. 1 SVI0_PLANE1_USAGE
  252. 2 SVI1_PLANE0_USAGE
  253. 3 SVI1_PLANE1_USAGE
  254.  
  255. SMUSVI_STARTUP_VID_COMPLETE (smn_addr_map:0x5a068,iod_smn_addr_map:0x5a068) 32bit (R):
  256. 0 STARTUP_SVI1_PLANE0_COMPLETE
  257. 1 STARTUP_SVI0_PLANE0_COMPLETE
  258. 2 STARTUP_SVI0_PLANE1_COMPLETE
  259. 3 STARTUP_SVI1_PLANE1_COMPLETE
  260.  
  261. SMUSVI_STARTUP_VID_EN (smn_addr_map:0x5a0f0,iod_smn_addr_map:0x5a0f0) 32bit (R):
  262. 0 STARTUP_VID_SVI0_EN
  263. 4 STARTUP_VID_SVI1_EN
  264.  
  265. SMUSVI_STARTUP_VID_TRIGGER (smn_addr_map:0x5a0f4,iod_smn_addr_map:0x5a0f4) 32bit:
  266. 0 STARTUP_VID_SVI0_TRIGGER
  267. 4 STARTUP_VID_SVI1_TRIGGER
  268.  
  269. SMUSVI_SVC0 (smn_addr_map:0x5a070,iod_smn_addr_map:0x5a070) 32bit:
  270. 1 SCHMEN
  271. 2 PU
  272. 3 PD
  273. 6 S0
  274. 7 S1
  275. 17 OE_OVERRIDE
  276. 18 OE
  277. 19 A_OVERRIDE
  278. 20 A
  279. 31 Y(R)
  280.  
  281. SMUSVI_SVC1 (smn_addr_map:0x5a07c,iod_smn_addr_map:0x5a07c) 32bit:
  282. 1 SCHMEN
  283. 2 PU
  284. 3 PD
  285. 6 S0
  286. 7 S1
  287. 17 OE_OVERRIDE
  288. 18 OE
  289. 19 A_OVERRIDE
  290. 20 A
  291. 31 Y(R)
  292.  
  293. SMUSVI_SVD0 (smn_addr_map:0x5a074,iod_smn_addr_map:0x5a074) 32bit:
  294. 1 SCHMEN
  295. 2 PU
  296. 3 PD
  297. 6 S0
  298. 7 S1
  299. 17 OE_OVERRIDE
  300. 18 OE
  301. 19 A_OVERRIDE
  302. 20 A
  303. 31 Y(R)
  304.  
  305. SMUSVI_SVD1 (smn_addr_map:0x5a080,iod_smn_addr_map:0x5a080) 32bit:
  306. 1 SCHMEN
  307. 2 PU
  308. 3 PD
  309. 6 S0
  310. 7 S1
  311. 17 OE_OVERRIDE
  312. 18 OE
  313. 19 A_OVERRIDE
  314. 20 A
  315. 31 Y(R)
  316.  
  317. SMUSVI_SVT0 (smn_addr_map:0x5a078,iod_smn_addr_map:0x5a078) 32bit:
  318. 0 SCHMEN
  319. 1 OE
  320. 2 PU
  321. 3 PD
  322. 6 S0
  323. 7 S1
  324. 20 A
  325. 31 Y(R)
  326.  
  327. SMUSVI_SVT1 (smn_addr_map:0x5a084,iod_smn_addr_map:0x5a084) 32bit:
  328. 0 SCHMEN
  329. 1 OE
  330. 2 PU
  331. 3 PD
  332. 6 S0
  333. 7 S1
  334. 20 A
  335. 31 Y(R)
  336.  
  337. SMUSVI_TEL_AVRG_CTRL (smn_addr_map:0x5a094,iod_smn_addr_map:0x5a094) 32bit:
  338. 0 SVI0_PLANE0_TEL_AVRG_EN
  339. 4 SVI0_PLANE1_TEL_AVRG_EN
  340. 8 SVI1_PLANE0_TEL_AVRG_EN
  341. 12 SVI1_PLANE1_TEL_AVRG_EN
  342. 16 TEL_REFCLK_CNTEN
  343.  
  344. SMUSVI_TEL_AVRG_SAMPLE (smn_addr_map:0x5a098,iod_smn_addr_map:0x5a098) 32bit:
  345. 0 TEL_AVRG_SAMPLE
  346.  
  347. SMUSVI_TEL_REFCLK_CNT (smn_addr_map:0x5a09c,iod_smn_addr_map:0x5a09c) 32bit (R):
  348. 22:0 TEL_REFCLK_CNT
  349. 23 TEL_REFCLK_CNT_OVERFLOW
  350.  
  351. SMUSVI_WARMRESET_SEL (smn_addr_map:0x5a03c,iod_smn_addr_map:0x5a03c) 32bit:
  352. 1:0 SVI0_PLANE0_WARMRESET_SEL
  353. 3:2 SVI0_PLANE1_WARMRESET_SEL
  354. 5:4 SVI1_PLANE0_WARMRESET_SEL
  355. 7:6 SVI1_PLANE1_WARMRESET_SEL
  356.  
  357. SMUSVI_WARMRESET_TARGET_VID (smn_addr_map:0x5a038,iod_smn_addr_map:0x5a038) 32bit:
  358. 7:0 SVI0_PLANE0_WARMRESET_TAGET_VID
  359. 15:8 SVI0_PLANE1_WARMRESET_TAGET_VID
  360. 23:16 SVI1_PLANE0_WARMRESET_TAGET_VID
  361. 31:24 SVI1_PLANE1_WARMRESET_TAGET_VID
  362.  
  363. SMUSVI_WARM_RESET (smn_addr_map:0x5a06c,iod_smn_addr_map:0x5a06c) 32bit:
  364. 0 WARM_RESET_SVI0
  365. 4 WARM_RESET_SVI1
  366.  
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