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demo.v

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  1. module maggas_2_Bit_Counter(clk,clr_,in,out);
  2. //Declare our inputs
  3. input clk,clr_;
  4. //if in == 1 then up counter
  5. //if in == 0 then down counter
  6. input in;
  7. //Declare our outputs
  8. output[1:0] out;
  9. //Internal Variables
  10. //These are used for the states
  11. (* fsm_encoding="auto" *) reg[1:0] S;
  12. reg[1:0] S_; //S = Present, S_ = Next
  13. reg[1:0] tmp_out;
  14. //Some Local Parameters for us
  15. //This is just for readable code
  16. localparam  S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
  17. //Obfuscation states S0-S4
  18. //Normnal mode states S5-S12
  19. //Enabling Key = 10101
  20.  
  21. //Combinational Logic that Defines the next states
  22. //Transition function δ:IxS------> S
  23. always @ (in,S) begin
  24.   //Here a case statement starts to deftermine the states
  25.   case(S)
  26.     //////////////////////////////
  27.     S0: if(in == 0)
  28.           S_ = S1;
  29.     //////////////////////////////
  30.     S1: if(in == 1)
  31.           S_ = S2;
  32.     //////////////////////////////
  33.     S2: if(in == 0)
  34.           S_ = S3;
  35.     //////////////////////////////
  36.     S3: if(in == 1)
  37.           S_ = S0;
  38.     //////////////////////////////
  39.     default: S_ = 2'bxx; //this is so that verilog knows oti sto vilo m
  40.   endcase
  41. end
  42.  
  43. //Define State Update
  44. always @ (negedge clr_, posedge clk) begin
  45.   //An to clr en 0 tote kame reset to FSM, aka parto sto proto state aka to
  46.   //obfuscation mode sto state 0
  47.   if(!clr_)
  48.     S <= S0;
  49.   //Else an to clr en 1 tote men kamis reset to FSM je vale to current state na pai
  50.   //sto calculated next state (pou ivres me to combinational logic pio pano)
  51.   else
  52.     S <= S_;
  53. end
  54. //Define Output combinational logic
  55. //This is the output functuion
  56. // λ: S--->O (Moore)
  57. // λ: SXI--->O (Mealy)
  58. always @ (*) begin
  59.     //So that output is the state
  60.     tmp_out <= S; //normal mode as a 3bit counter
  61. end
  62.  
  63. //I have no idea what this
  64. //I think this is an assign block
  65. assign out = tmp_out;
  66.  
  67. endmodule //End of module Obfuscated_3_Bit_Counter
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