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  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company:
  4. // Engineer:
  5. //
  6. // Create Date: 30.08.2019 23:21:25
  7. // Design Name:
  8. // Module Name: user_pos_ctl
  9. // Project Name:
  10. // Target Devices:
  11. // Tool Versions:
  12. // Description:
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21.  
  22.  
  23. module user_pos_ctl(
  24.     input wire clk,
  25.     input wire rst,
  26.     input wire [3:0] keys,       // {keyU,keyD,keyR,keyL}
  27.     //input wire [17:0] st_obst_xy,       // st_obst_xy = {STAT_OBST_1_X,STAT_OBST_1_Y,STAT_OBST_2_X,STAT_OBST_2_Y,STAT_OBST_3_X,STAT_OBST_3_Y};
  28.    
  29.     output reg [11:0] xpos,
  30.     output reg [11:0] ypos
  31. );
  32.  
  33. reg [11:0] xpos_nxt, ypos_nxt;
  34.  
  35. always @(posedge clk) begin
  36.     if (rst) begin
  37.         xpos <= 0;
  38.         ypos <= 0;
  39.     end
  40.     else begin
  41.         xpos <= xpos_nxt;
  42.         ypos <= ypos_nxt;
  43.     end
  44. end  
  45.  
  46. always @* begin
  47.     if (keys[3]) begin
  48.         xpos_nxt = 300;
  49.         ypos_nxt = 300;
  50.     end  
  51.     else if (keys[2]) begin
  52.         xpos_nxt = 400;
  53.         ypos_nxt = 400;
  54.     end
  55.     else if (keys[1]) begin
  56.         xpos_nxt = 500;
  57.         ypos_nxt = 500;
  58.     end
  59.     else if (keys[0]) begin
  60.         xpos_nxt = 100;
  61.         ypos_nxt = 100;
  62.     end        
  63.     else begin
  64.         xpos_nxt = xpos;
  65.         ypos_nxt = ypos;
  66.     end
  67. end
  68. endmodule
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