API tools faq
paste
aidanozo

Untitled

aidanozo
Oct 23rd, 2024
696
0
Never
Add comment
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
VeriLog 0.13 KB | None | 0 0
raw download clone embed print report
  1. module led7(
  2.     output wire [6:0] o_w_7seg,    
  3.     input  wire [3:0] i_w_in
  4. );
  5.  
  6.     // Implementarea noastra
  7.    
  8. endmodule
Advertisement
Add Comment
Please, Sign In to add comment
Public Pastes
We use cookies for various purposes including analytics. By continuing to use Pastebin, you agree to our use of cookies as described in the Cookies Policy.  OK, I Understand
Not a member of Pastebin yet?
Sign Up, it unlocks many cool features!