Advertisement
Guest User

tinymembench on ODROID N1 / A72

a guest
Feb 16th, 2018
157
0
Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
text 7.22 KB | None | 0 0
  1. root@odroid:/home/odroid/tinymembench# taskset -c 5 ./tinymembench
  2. tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
  3.  
  4. ==========================================================================
  5. == Memory bandwidth tests ==
  6. == ==
  7. == Note 1: 1MB = 1000000 bytes ==
  8. == Note 2: Results for 'copy' tests show how many bytes can be ==
  9. == copied per second (adding together read and writen ==
  10. == bytes would have provided twice higher numbers) ==
  11. == Note 3: 2-pass copy means that we are using a small temporary buffer ==
  12. == to first fetch data into it, and only then write it to the ==
  13. == destination (source -> L1 cache, L1 cache -> destination) ==
  14. == Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
  15. == brackets ==
  16. ==========================================================================
  17.  
  18. C copy backwards : 2941.0 MB/s (0.8%)
  19. C copy backwards (32 byte blocks) : 2925.2 MB/s
  20. C copy backwards (64 byte blocks) : 2870.1 MB/s (0.7%)
  21. C copy : 2874.5 MB/s
  22. C copy prefetched (32 bytes step) : 2842.1 MB/s
  23. C copy prefetched (64 bytes step) : 2853.4 MB/s (0.7%)
  24. C 2-pass copy : 2590.6 MB/s
  25. C 2-pass copy prefetched (32 bytes step) : 2638.5 MB/s (0.6%)
  26. C 2-pass copy prefetched (64 bytes step) : 2625.2 MB/s
  27. C fill : 4868.7 MB/s (0.6%)
  28. C fill (shuffle within 16 byte blocks) : 4860.2 MB/s (0.5%)
  29. C fill (shuffle within 32 byte blocks) : 4857.8 MB/s (0.5%)
  30. C fill (shuffle within 64 byte blocks) : 4867.0 MB/s (0.4%)
  31. ---
  32. standard memcpy : 2929.1 MB/s (0.7%)
  33. standard memset : 4865.5 MB/s (0.5%)
  34. ---
  35. NEON LDP/STP copy : 2924.7 MB/s
  36. NEON LDP/STP copy pldl2strm (32 bytes step) : 2978.5 MB/s (0.9%)
  37. NEON LDP/STP copy pldl2strm (64 bytes step) : 2977.3 MB/s
  38. NEON LDP/STP copy pldl1keep (32 bytes step) : 2857.8 MB/s
  39. NEON LDP/STP copy pldl1keep (64 bytes step) : 2856.7 MB/s (0.7%)
  40. NEON LD1/ST1 copy : 2917.6 MB/s
  41. NEON STP fill : 4866.9 MB/s (0.5%)
  42. NEON STNP fill : 4791.6 MB/s (5.1%)
  43. ARM LDP/STP copy : 2930.2 MB/s (0.6%)
  44. ARM STP fill : 4862.4 MB/s (0.5%)
  45. ARM STNP fill : 4809.7 MB/s (5.0%)
  46.  
  47. ==========================================================================
  48. == Framebuffer read tests. ==
  49. == ==
  50. == Many ARM devices use a part of the system memory as the framebuffer, ==
  51. == typically mapped as uncached but with write-combining enabled. ==
  52. == Writes to such framebuffers are quite fast, but reads are much ==
  53. == slower and very sensitive to the alignment and the selection of ==
  54. == CPU instructions which are used for accessing memory. ==
  55. == ==
  56. == Many x86 systems allocate the framebuffer in the GPU memory, ==
  57. == accessible for the CPU via a relatively slow PCI-E bus. Moreover, ==
  58. == PCI-E is asymmetric and handles reads a lot worse than writes. ==
  59. == ==
  60. == If uncached framebuffer reads are reasonably fast (at least 100 MB/s ==
  61. == or preferably >300 MB/s), then using the shadow framebuffer layer ==
  62. == is not necessary in Xorg DDX drivers, resulting in a nice overall ==
  63. == performance improvement. For example, the xf86-video-fbturbo DDX ==
  64. == uses this trick. ==
  65. ==========================================================================
  66.  
  67. NEON LDP/STP copy (from framebuffer) : 660.9 MB/s (0.4%)
  68. NEON LDP/STP 2-pass copy (from framebuffer) : 594.7 MB/s (0.3%)
  69. NEON LD1/ST1 copy (from framebuffer) : 704.4 MB/s
  70. NEON LD1/ST1 2-pass copy (from framebuffer) : 642.4 MB/s (0.3%)
  71. ARM LDP/STP copy (from framebuffer) : 484.0 MB/s (0.3%)
  72. ARM LDP/STP 2-pass copy (from framebuffer) : 463.1 MB/s (0.3%)
  73.  
  74. ==========================================================================
  75. == Memory latency test ==
  76. == ==
  77. == Average time is measured for random memory accesses in the buffers ==
  78. == of different sizes. The larger is the buffer, the more significant ==
  79. == are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
  80. == accesses. For extremely large buffer sizes we are expecting to see ==
  81. == page table walk with several requests to SDRAM for almost every ==
  82. == memory access (though 64MiB is not nearly large enough to experience ==
  83. == this effect to its fullest). ==
  84. == ==
  85. == Note 1: All the numbers are representing extra time, which needs to ==
  86. == be added to L1 cache latency. The cycle timings for L1 cache ==
  87. == latency can be usually found in the processor documentation. ==
  88. == Note 2: Dual random read means that we are simultaneously performing ==
  89. == two independent memory accesses at a time. In the case if ==
  90. == the memory subsystem can't handle multiple outstanding ==
  91. == requests, dual random read has the same timings as two ==
  92. == single reads performed one after another. ==
  93. ==========================================================================
  94.  
  95. block size : single random read / dual random read
  96. 1024 : 0.0 ns / 0.0 ns
  97. 2048 : 0.0 ns / 0.0 ns
  98. 4096 : 0.0 ns / 0.0 ns
  99. 8192 : 0.0 ns / 0.0 ns
  100. 16384 : 0.0 ns / 0.0 ns
  101. 32768 : 0.0 ns / 0.0 ns
  102. 65536 : 4.1 ns / 6.5 ns
  103. 131072 : 6.2 ns / 8.7 ns
  104. 262144 : 8.9 ns / 11.6 ns
  105. 524288 : 10.3 ns / 13.3 ns
  106. 1048576 : 15.1 ns / 21.5 ns
  107. 2097152 : 105.5 ns / 160.5 ns
  108. 4194304 : 149.5 ns / 201.0 ns
  109. 8388608 : 176.0 ns / 221.3 ns
  110. 16777216 : 189.8 ns / 230.5 ns
  111. 33554432 : 196.8 ns / 235.8 ns
  112. 67108864 : 206.6 ns / 247.7 ns
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement