`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10/17/2019 12:56:53 PM
// Design Name:
// Module Name: Main_Game
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module Main_Game(
   // input reset,
    input  Button_X,
    input  Button_O,
   // input  Button_win,
    input  Button_display,
    input [8:0] player_X,
    //input [8:0] player_O,

  //  output reg [8:0] empty,
    output reg [1:0] winner,
   // reg illegal_counter

    );
    wire [8:0] xout,
    wire [8:0] Oout,
    wire [8:0] player_Xmoves;
    wire [8:0] player_Omoves;
    wire [8:0] legalmoves;
    wire[8:0] empty;
   // wire illegal_move;

    assign player_Xmoves =+ player_X;
    assign player_Omoves =+ player_X;
 //   assign legalmoves =  player_Xmoves + player_Omoves;

    always @* begin
        winner <= 9'b0;
        case({Button_X, Button_O, Button_display})
            3'b100: xout = player_Xmoves;  ///

            3'b010: Oout = player_Omoves;

            default: empty = 9'b0;
        endcase

       if(player_Xmoves == 9'b111xxxxxx ||player_Xmoves == 9'bxxx111xxx || player_Xmoves == 9'bxxxxxx111 || player_Xmoves == 9'b1xx1xx1xx ||
        player_Xmoves == 9'bx1xx1xx1x || player_Xmoves == 9'bxx1xx1xx1 || player_Xmoves == 9'b1xxx1xxx1 || player_Xmoves == 9'bxx1x1x1xx)
       begin
       xout <= 9'b0;
       Oout <= 9'b0;
      // empty <= 9'b0;
       winner <= 2'b10;
       end

       if(player_Omoves == 9'b111xxxxxx ||player_Omoves == 9'bxxx111xxx || player_Omoves == 9'bxxxxx111x || player_Omoves == 9'b1xx1xx1xx ||
        player_Omoves == 9'bx1xx1xx1x || player_Omoves == 9'bxx1xx1xx1 || player_Omoves == 9'b1xxx1xxx1 || player_Omoves == 9'bxx1x1x1xx)
       begin
       xout <= 9'b0;
       Oout <= 9'b0;
      // empty <= 9'b0;
       winner <= 2'b01;
       end
     end
endmodule