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DDR_Calibration_Arm_Speed_800MHz

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  1.  
  2. ============================================
  3.         DDR Stress Test (2.6.0)
  4.         Build: Aug  1 2017, 17:33:25
  5.         NXP Semiconductors.
  6. ============================================
  7.  
  8. ============================================
  9.         Chip ID
  10. CHIP ID = i.MX6 Dual/Quad (0x63)
  11. Internal Revision = TO1.2
  12. ============================================
  13.  
  14. ============================================
  15.         Boot Configuration
  16. SRC_SBMR1(0x020d8004) = 0x18000030
  17. SRC_SBMR2(0x020d801c) = 0x21000011
  18. ============================================
  19.  
  20. ARM Clock set to 800MHz
  21.  
  22. ============================================
  23.         DDR configuration
  24. BOOT_CFG3[5-4]: 0x00, Single DDR channel.
  25. DDR type is DDR3
  26. Data width: 64, bank num: 8
  27. Row size: 15, col size: 10
  28. Chip select CSD0 is used
  29. Density per chip select: 2048MB
  30. ============================================
  31.  
  32. Current Temperature: 36
  33. ============================================
  34.  
  35. DDR Freq: 396 MHz
  36.  
  37. ddr_mr1=0x00000004
  38. Start write leveling calibration...
  39. running Write level HW calibration
  40. Write leveling calibration completed, update the following registers in your initialization script
  41.     MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x001F0023
  42.     MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x002B001E
  43.     MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x0014001F
  44.     MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x00170027
  45. Write DQS delay result:
  46.    Write DQS0 delay: 35/256 CK
  47.    Write DQS1 delay: 31/256 CK
  48.    Write DQS2 delay: 30/256 CK
  49.    Write DQS3 delay: 43/256 CK
  50.    Write DQS4 delay: 31/256 CK
  51.    Write DQS5 delay: 20/256 CK
  52.    Write DQS6 delay: 39/256 CK
  53.    Write DQS7 delay: 23/256 CK
  54.  
  55. Starting DQS gating calibration
  56. . HC_DEL=0x00000000 result[00]=0x11111111
  57. . HC_DEL=0x00000001 result[01]=0x11111111
  58. . HC_DEL=0x00000002 result[02]=0x00000000
  59. . HC_DEL=0x00000003 result[03]=0x00000000
  60. . HC_DEL=0x00000004 result[04]=0x01000000
  61. . HC_DEL=0x00000005 result[05]=0x11111111
  62. . HC_DEL=0x00000006 result[06]=0x11111111
  63. . HC_DEL=0x00000007 result[07]=0x11111111
  64. . HC_DEL=0x00000008 result[08]=0x11111111
  65. . HC_DEL=0x00000009 result[09]=0x11111111
  66. . HC_DEL=0x0000000A result[0A]=0x11111111
  67. . HC_DEL=0x0000000B result[0B]=0x11111111
  68. . HC_DEL=0x0000000C result[0C]=0x11111111
  69. . HC_DEL=0x0000000D result[0D]=0x11111111
  70. DQS HC delay value low1 = 0x02020202, high1=0x04040404
  71. DQS HC delay value low2 = 0x02020202, high2=0x04030404
  72.  
  73. loop ABS offset to get HW_DG_LOW
  74. . ABS_OFFSET=0x00000000 result[00]=0x11111111
  75. . ABS_OFFSET=0x00000004 result[01]=0x11111111
  76. . ABS_OFFSET=0x00000008 result[02]=0x11111111
  77. . ABS_OFFSET=0x0000000C result[03]=0x11111111
  78. . ABS_OFFSET=0x00000010 result[04]=0x11111111
  79. . ABS_OFFSET=0x00000014 result[05]=0x11111111
  80. . ABS_OFFSET=0x00000018 result[06]=0x11111111
  81. . ABS_OFFSET=0x0000001C result[07]=0x11111111
  82. . ABS_OFFSET=0x00000020 result[08]=0x11111111
  83. . ABS_OFFSET=0x00000024 result[09]=0x11111111
  84. . ABS_OFFSET=0x00000028 result[0A]=0x11111111
  85. . ABS_OFFSET=0x0000002C result[0B]=0x11111111
  86. . ABS_OFFSET=0x00000030 result[0C]=0x11111111
  87. . ABS_OFFSET=0x00000034 result[0D]=0x10111111
  88. . ABS_OFFSET=0x00000038 result[0E]=0x10111111
  89. . ABS_OFFSET=0x0000003C result[0F]=0x10111111
  90. . ABS_OFFSET=0x00000040 result[10]=0x10111111
  91. . ABS_OFFSET=0x00000044 result[11]=0x10111111
  92. . ABS_OFFSET=0x00000048 result[12]=0x10111111
  93. . ABS_OFFSET=0x0000004C result[13]=0x10111111
  94. . ABS_OFFSET=0x00000050 result[14]=0x00110111
  95. . ABS_OFFSET=0x00000054 result[15]=0x00110111
  96. . ABS_OFFSET=0x00000058 result[16]=0x00110111
  97. . ABS_OFFSET=0x0000005C result[17]=0x00110011
  98. . ABS_OFFSET=0x00000060 result[18]=0x00110011
  99. . ABS_OFFSET=0x00000064 result[19]=0x00110011
  100. . ABS_OFFSET=0x00000068 result[1A]=0x00110001
  101. . ABS_OFFSET=0x0000006C result[1B]=0x00000000
  102. . ABS_OFFSET=0x00000070 result[1C]=0x00000000
  103. . ABS_OFFSET=0x00000074 result[1D]=0x00000000
  104. . ABS_OFFSET=0x00000078 result[1E]=0x00000000
  105. . ABS_OFFSET=0x0000007C result[1F]=0x00000000
  106.  
  107. loop ABS offset to get HW_DG_HIGH
  108. . ABS_OFFSET=0x00000000 result[00]=0x00000000
  109. . ABS_OFFSET=0x00000004 result[01]=0x00000000
  110. . ABS_OFFSET=0x00000008 result[02]=0x00000000
  111. . ABS_OFFSET=0x0000000C result[03]=0x00000000
  112. . ABS_OFFSET=0x00000010 result[04]=0x00000000
  113. . ABS_OFFSET=0x00000014 result[05]=0x00000000
  114. . ABS_OFFSET=0x00000018 result[06]=0x10000000
  115. . ABS_OFFSET=0x0000001C result[07]=0x10001100
  116. . ABS_OFFSET=0x00000020 result[08]=0x10001100
  117. . ABS_OFFSET=0x00000024 result[09]=0x10001100
  118. . ABS_OFFSET=0x00000028 result[0A]=0x10001100
  119. . ABS_OFFSET=0x0000002C result[0B]=0x10001100
  120. . ABS_OFFSET=0x00000030 result[0C]=0x10101111
  121. . ABS_OFFSET=0x00000034 result[0D]=0x10101111
  122. . ABS_OFFSET=0x00000038 result[0E]=0x10101111
  123. . ABS_OFFSET=0x0000003C result[0F]=0x10111111
  124. . ABS_OFFSET=0x00000040 result[10]=0x10111111
  125. . ABS_OFFSET=0x00000044 result[11]=0x11111111
  126. . ABS_OFFSET=0x00000048 result[12]=0x10111111
  127. . ABS_OFFSET=0x0000004C result[13]=0x10111111
  128. . ABS_OFFSET=0x00000050 result[14]=0x10111111
  129. . ABS_OFFSET=0x00000054 result[15]=0x10111111
  130. . ABS_OFFSET=0x00000058 result[16]=0x10111111
  131. . ABS_OFFSET=0x0000005C result[17]=0x10111111
  132. . ABS_OFFSET=0x00000060 result[18]=0x10111111
  133. . ABS_OFFSET=0x00000064 result[19]=0x10111111
  134. . ABS_OFFSET=0x00000068 result[1A]=0x10111111
  135. . ABS_OFFSET=0x0000006C result[1B]=0x11111111
  136. . ABS_OFFSET=0x00000070 result[1C]=0x11111111
  137. . ABS_OFFSET=0x00000074 result[1D]=0x11111111
  138. . ABS_OFFSET=0x00000078 result[1E]=0x11111111
  139. . ABS_OFFSET=0x0000007C result[1F]=0x11111111
  140.  
  141.  
  142. BYTE 0:
  143.     Start:       HC=0x01 ABS=0x6C
  144.     End:         HC=0x04 ABS=0x2C
  145.     Mean:        HC=0x03 ABS=0x0C
  146.     End-0.5*tCK:     HC=0x03 ABS=0x2C
  147.     Final:       HC=0x03 ABS=0x2C
  148. BYTE 1:
  149.     Start:       HC=0x01 ABS=0x68
  150.     End:         HC=0x04 ABS=0x2C
  151.     Mean:        HC=0x03 ABS=0x0A
  152.     End-0.5*tCK:     HC=0x03 ABS=0x2C
  153.     Final:       HC=0x03 ABS=0x2C
  154. BYTE 2:
  155.     Start:       HC=0x01 ABS=0x5C
  156.     End:         HC=0x04 ABS=0x18
  157.     Mean:        HC=0x02 ABS=0x79
  158.     End-0.5*tCK:     HC=0x03 ABS=0x18
  159.     Final:       HC=0x03 ABS=0x18
  160. BYTE 3:
  161.     Start:       HC=0x01 ABS=0x50
  162.     End:         HC=0x04 ABS=0x18
  163.     Mean:        HC=0x02 ABS=0x73
  164.     End-0.5*tCK:     HC=0x03 ABS=0x18
  165.     Final:       HC=0x03 ABS=0x18
  166. BYTE 4:
  167.     Start:       HC=0x01 ABS=0x6C
  168.     End:         HC=0x04 ABS=0x38
  169.     Mean:        HC=0x03 ABS=0x12
  170.     End-0.5*tCK:     HC=0x03 ABS=0x38
  171.     Final:       HC=0x03 ABS=0x38
  172. BYTE 5:
  173.     Start:       HC=0x01 ABS=0x6C
  174.     End:         HC=0x04 ABS=0x2C
  175.     Mean:        HC=0x03 ABS=0x0C
  176.     End-0.5*tCK:     HC=0x03 ABS=0x2C
  177.     Final:       HC=0x03 ABS=0x2C
  178. BYTE 6:
  179.     Start:       HC=0x01 ABS=0x34
  180.     End:         HC=0x03 ABS=0x40
  181.     Mean:        HC=0x02 ABS=0x3A
  182.     End-0.5*tCK:     HC=0x02 ABS=0x40
  183.     Final:       HC=0x02 ABS=0x40
  184. BYTE 7:
  185.     Start:       HC=0x01 ABS=0x50
  186.     End:         HC=0x04 ABS=0x14
  187.     Mean:        HC=0x02 ABS=0x71
  188.     End-0.5*tCK:     HC=0x03 ABS=0x14
  189.     Final:       HC=0x03 ABS=0x14
  190.  
  191. DQS calibration MMDC0 MPDGCTRL0 = 0x032C032C, MPDGCTRL1 = 0x03180318
  192.  
  193. DQS calibration MMDC1 MPDGCTRL0 = 0x032C0338, MPDGCTRL1 = 0x03140240
  194.  
  195. Note: Array result[] holds the DRAM test result of each byte.  
  196.       0: test pass.  1: test fail  
  197.       4 bits respresent the result of 1 byte.    
  198.       result 00000001:byte 0 fail.
  199.       result 00000011:byte 0, 1 fail.
  200.  
  201. Starting Read calibration...
  202.  
  203. ABS_OFFSET=0x00000000   result[00]=0x11111111
  204. ABS_OFFSET=0x04040404   result[01]=0x11111111
  205. ABS_OFFSET=0x08080808   result[02]=0x11111111
  206. ABS_OFFSET=0x0C0C0C0C   result[03]=0x11111111
  207. ABS_OFFSET=0x10101010   result[04]=0x11111111
  208. ABS_OFFSET=0x14141414   result[05]=0x11111111
  209. ABS_OFFSET=0x18181818   result[06]=0x11111111
  210. ABS_OFFSET=0x1C1C1C1C   result[07]=0x11111111
  211. ABS_OFFSET=0x20202020   result[08]=0x01111100
  212. ABS_OFFSET=0x24242424   result[09]=0x00011100
  213. ABS_OFFSET=0x28282828   result[0A]=0x00011000
  214. ABS_OFFSET=0x2C2C2C2C   result[0B]=0x00010000
  215. ABS_OFFSET=0x30303030   result[0C]=0x00000000
  216. ABS_OFFSET=0x34343434   result[0D]=0x00000000
  217. ABS_OFFSET=0x38383838   result[0E]=0x00000000
  218. ABS_OFFSET=0x3C3C3C3C   result[0F]=0x00000000
  219. ABS_OFFSET=0x40404040   result[10]=0x00000000
  220. ABS_OFFSET=0x44444444   result[11]=0x00000000
  221. ABS_OFFSET=0x48484848   result[12]=0x00000000
  222. ABS_OFFSET=0x4C4C4C4C   result[13]=0x00000000
  223. ABS_OFFSET=0x50505050   result[14]=0x00000000
  224. ABS_OFFSET=0x54545454   result[15]=0x00000000
  225. ABS_OFFSET=0x58585858   result[16]=0x00000000
  226. ABS_OFFSET=0x5C5C5C5C   result[17]=0x00000000
  227. ABS_OFFSET=0x60606060   result[18]=0x00000000
  228. ABS_OFFSET=0x64646464   result[19]=0x00000000
  229. ABS_OFFSET=0x68686868   result[1A]=0x00100000
  230. ABS_OFFSET=0x6C6C6C6C   result[1B]=0x00100111
  231. ABS_OFFSET=0x70707070   result[1C]=0x00100111
  232. ABS_OFFSET=0x74747474   result[1D]=0x00100111
  233. ABS_OFFSET=0x78787878   result[1E]=0x01111111
  234. ABS_OFFSET=0x7C7C7C7C   result[1F]=0x11111111
  235.  
  236. Byte 0: (0x20 - 0x68), middle value:0x44
  237. Byte 1: (0x20 - 0x68), middle value:0x44
  238. Byte 2: (0x28 - 0x68), middle value:0x48
  239. Byte 3: (0x2c - 0x74), middle value:0x50
  240. Byte 4: (0x30 - 0x74), middle value:0x52
  241. Byte 5: (0x24 - 0x64), middle value:0x44
  242. Byte 6: (0x24 - 0x74), middle value:0x4c
  243. Byte 7: (0x20 - 0x78), middle value:0x4c
  244.  
  245. MMDC0 MPRDDLCTL = 0x50484444, MMDC1 MPRDDLCTL = 0x4C4C4452
  246.  
  247. Starting Write calibration...
  248.  
  249. ABS_OFFSET=0x00000000   result[00]=0x11111111
  250. ABS_OFFSET=0x04040404   result[01]=0x11111111
  251. ABS_OFFSET=0x08080808   result[02]=0x11110111
  252. ABS_OFFSET=0x0C0C0C0C   result[03]=0x11110111
  253. ABS_OFFSET=0x10101010   result[04]=0x10110111
  254. ABS_OFFSET=0x14141414   result[05]=0x10100010
  255. ABS_OFFSET=0x18181818   result[06]=0x00000010
  256. ABS_OFFSET=0x1C1C1C1C   result[07]=0x00000000
  257. ABS_OFFSET=0x20202020   result[08]=0x00000000
  258. ABS_OFFSET=0x24242424   result[09]=0x00000000
  259. ABS_OFFSET=0x28282828   result[0A]=0x00000000
  260. ABS_OFFSET=0x2C2C2C2C   result[0B]=0x00000000
  261. ABS_OFFSET=0x30303030   result[0C]=0x00000000
  262. ABS_OFFSET=0x34343434   result[0D]=0x00000000
  263. ABS_OFFSET=0x38383838   result[0E]=0x00000000
  264. ABS_OFFSET=0x3C3C3C3C   result[0F]=0x00000000
  265. ABS_OFFSET=0x40404040   result[10]=0x00000000
  266. ABS_OFFSET=0x44444444   result[11]=0x11111111
  267. ABS_OFFSET=0x48484848   result[12]=0x00000000
  268. ABS_OFFSET=0x4C4C4C4C   result[13]=0x11111111
  269. ABS_OFFSET=0x50505050   result[14]=0x00000000
  270. ABS_OFFSET=0x54545454   result[15]=0x00000000
  271. ABS_OFFSET=0x58585858   result[16]=0x00000000
  272. ABS_OFFSET=0x5C5C5C5C   result[17]=0x00000000
  273. ABS_OFFSET=0x60606060   result[18]=0x00000000
  274. ABS_OFFSET=0x64646464   result[19]=0x00000000
  275. ABS_OFFSET=0x68686868   result[1A]=0x00001000
  276. ABS_OFFSET=0x6C6C6C6C   result[1B]=0x01001011
  277. ABS_OFFSET=0x70707070   result[1C]=0x01001111
  278. ABS_OFFSET=0x74747474   result[1D]=0x01001111
  279. ABS_OFFSET=0x78787878   result[1E]=0x11011111
  280. ABS_OFFSET=0x7C7C7C7C   result[1F]=0x11111111
  281.  
  282. Byte 0: (0x14 - 0x40), middle value:0x2a
  283. Byte 1: (0x1c - 0x40), middle value:0x2e
  284. Byte 4: (0x18 - 0x40), middle value:0x2c
  285. Byte 6: (0x10 - 0x40), middle value:0x28
  286. Byte 7: (0x18 - 0x40), middle value:0x2c
  287.  
  288. MMDC0 MPWRDLCTL = 0x242A2E2A,MMDC1 MPWRDLCTL = 0x2C282C2A
  289.  
  290.  
  291.    MMDC registers updated from calibration
  292.  
  293.    Write leveling calibration
  294.    MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x001F0023
  295.    MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x002B001E
  296.    MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x0014001F
  297.    MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x00170027
  298.  
  299.    Read DQS Gating calibration
  300.    MPDGCTRL0 PHY0 (0x021b083c) = 0x032C032C
  301.    MPDGCTRL1 PHY0 (0x021b0840) = 0x03180318
  302.    MPDGCTRL0 PHY1 (0x021b483c) = 0x032C0338
  303.    MPDGCTRL1 PHY1 (0x021b4840) = 0x03140240
  304.  
  305.    Read calibration
  306.    MPRDDLCTL PHY0 (0x021b0848) = 0x50484444
  307.    MPRDDLCTL PHY1 (0x021b4848) = 0x4C4C4452
  308.  
  309.    Write calibration
  310.    MPWRDLCTL PHY0 (0x021b0850) = 0x242A2E2A
  311.    MPWRDLCTL PHY1 (0x021b4850) = 0x2C282C2A
  312.  
  313.  
  314. Success: DDR calibration completed!!!
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