module LogicalOperationsByBuildInPrimitives(sw,led);
	input [6:0] sw; 	// "[6:0]" means bus. From sw[0] to sw[6] is defined for input.
	output [3:0] led;       // From led[0] to led[3] is defined.
	wire w_and,w_or,w_not,w_xor; // To define the wire for inner crossline.

	and(w_and, sw[0], sw[1]); // "&" -> and().
	or(w_or, sw[2], sw[3]);   // "|" -> or().
	not(w_not, sw[4]);        // "~" -> not().
	xor(w_xor, sw[5], sw[6]); // "^" -> xor().

	// {} is Linking Operator. (RENKETSU in Japanese)
	assign led={w_xor,w_not,w_or,w_and}; // assign led[3]=w_xor; assign led[2]=w_not; assign led[1]=w_or; assign led[0]=w_and;
endmodule