LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY LogicalStep_Lab5_top IS
   PORT
	(
   clkin_50		: in	std_logic;							-- The 50 MHz FPGA Clockinput
	rst_n			: in	std_logic;							-- The RESET input (ACTIVE LOW)
	pb				: in	std_logic_vector(3 downto 0); -- The push-button inputs (ACTIVE LOW)
 	sw   			: in  std_logic_vector(7 downto 0); -- The switch inputs
   leds			: out std_logic_vector(7 downto 0);	-- for displaying the switch content
   seg7_data 	: out std_logic_vector(6 downto 0); -- 7-bit outputs to a 7-segment
	seg7_char1  : out	std_logic;							-- seg7 digi selectors
	seg7_char2  : out	std_logic							-- seg7 digi selectors
	);
END LogicalStep_Lab5_top;

ARCHITECTURE SimpleCircuit OF LogicalStep_Lab5_top IS


   component cycle_generator port (
          clkin      		: in  std_logic;--input clock
			 rst_n				: in  std_logic;--reset
			 modulo 				: in  integer;	-- the modulo value that determines output clock speed
			 strobe_out			: out	std_logic;--strobe out
			 full_cycle_out	: out std_logic --full cycle out
			);
   end component;

   component segment7_mux port (
          clk        : in  std_logic := '0';--input clock
			 DIN0 		: in  std_logic_vector(6 downto 0);	--input dig0
			 DIN1 		: in  std_logic_vector(6 downto 0);-- input dig1
			 DOUT			: out	std_logic_vector(6 downto 0);
			 DIG1			: out	std_logic;--output0
			 DIG2			: out	std_logic--output1
				);
   end component;

	component Moore_SM
		port (
			 rst_n: in std_logic;
			 clkin: in	std_logic; --input clock
			 skipNS: in std_logic; --if NS sensor triggered
			 skipEW: in std_logic; -- if EW sensor triggered
			 nightMode : in std_logic; --if nightmode active
			 reducedMode: in std_logic; --if reduced mode active
			 outputState : OUT std_logic_vector(4 downto 0) --4 bit out
			);
		end component;

	component BasicSynchronizer
		port (
			DATA_INPUT:  in std_logic; -- input
			CLOCK : in std_logic; --clock to synchronize to
			DATA_OUTPUT : out std_logic -- sychronized output
			);
		end component;

	component Latch1
		port(
		synchronized_Input: in std_logic;--latch input
		LATCH_CLEAR : in std_logic; --if latch is to be cleared
		CLOCK: in std_logic; --input clock
		enable : in std_logic;--if latch enabled
		LatchOut : out std_logic-- latch output
		);
		end component;
----------------------------------------------------------------------------------------------------
	CONSTANT	SIM							:  boolean := False;
	CONSTANT CLK_DIV_SIZE				: 	INTEGER := 24;

	SIGNAL 	Main_CLK						:  STD_LOGIC;
	SIGNAL 	bin_counter					:  UNSIGNED(CLK_DIV_SIZE-1 downto 0);


	CONSTANT CNTR1_modulo				: 	integer := 25000000;    	-- modulo count for cycle generator 1 with 50Mhz clocking input
   CONSTANT CNTR2_modulo				: 	integer :=  5000000;    	-- modulo count for cycle generator 2 with 50Mhz clocking input
   CONSTANT CNTR1_modulo_sim			: 	integer := 200;   			-- modulo count for cycle generator 1 during simulation
   CONSTANT CNTR2_modulo_sim			: 	integer :=  40;   			-- modulo count for cycle generator 2 during simulation

   SIGNAL CNTR1_modulo_value			: 	integer ;   					-- modulo count for cycle generator 1
   SIGNAL CNTR2_modulo_value			: 	integer ;   					-- modulo count for cycle generator 2

   SIGNAL clken1,clken2					:  STD_LOGIC; 						-- clock enables 1 & 2

	SIGNAL strobe1, strobe2				:  std_logic;						-- strobes 1 & 2 with each one being 50% Duty Cycle


	SIGNAL EW	 							: STD_LOGIC_VECTOR(6 downto 0);
	Signal lightStatus					:  STD_LOGIC_VECTOR(4 downto 0); -- signals for inputs into seg7_mux.
	signal NS 								: STD_LOGIC_VECTOR (6 downto 0);


	signal current 						: std_logic_Vector(6 downto 0); --current state

	signal basicOutputNS 					: std_logic;--synchronizer output for NS
	signal basicOutputEW 					: std_logic;-- synchronizer output for EW
	signal clearNS : std_logic; --if clear NS
	signal clearEW: std_logic; -- if clear EW
	signal latchNSOut : std_logic; --latch outputs
	signal latchEWOut : std_logic; --latch outputs

	---------------------------------------
	signal temp:std_logic_vector(6 downto 0); --temp to store data for latch boolean equations

BEGIN
----------------------------------------------------------------------------------------------------
BinCLK: PROCESS(clkin_50, rst_n) is
   BEGIN
		IF (rising_edge(clkin_50)) THEN -- binary counter increments on rising clock edge
         bin_counter <= bin_counter + 1;
      END IF;
   END PROCESS;

Clock_Source:
				Main_Clk <=
				clkin_50 when sim = TRUE else				-- for simulations only
				std_logic(bin_counter(23));



MODULO_1_SELECTION:	CnTR1_modulo_value <= CNTR1_modulo when SIM = FALSE else CNTR1_modulo_sim;

MODULO_2_SELECTION:	CNTR2_modulo_value <= CNTR2_modulo when SIM = FALSE else CNTR2_modulo_sim;


----------------------------------------------------------------------------------------------------
-- Component Hook-up:

GEN1: 	cycle_generator port map(clkin_50, rst_n, CNTR1_modulo_value, strobe1, clken1);

GEN2: 	cycle_generator port map(clkin_50, rst_n, CNTR2_modulo_value, strobe2, clken2);





--create instance ofinput synchronizer
InputSyncNS: BasicSynchronizer port map (not pb(0),clkin_50,basicOutputNS);
InputSyncEW: BasicSynchronizer port map (not pb(1),clkin_50,basicOutputEW);

--clear at 14 on nS and 6 at EW
with lightStatus select
	clearNS <='1' when "01110",
	'0' when others;

with lightStatus select
	clearEW <='1' when "00110",
	'0' when others;

	--create latches for NW and EW
LatchNS: Latch1 port map (basicOutputNS,clearNS,clkin_50,clken2,latchNSOut);


LatchEW: Latch1 port map (basicOutputEW,clearEW,clkin_50,clken2,latchEWOut);


--night sw 0
--reduced mode sw 1
SM: Moore_SM port map(rst_n, strobe1, latchNSOut,latchEWOut,sw(0),sw(1), lightStatus);


--convert state machine output to seven seg signals
with lightStatus select			-----------------------------------G flash
					NS  	<= 	"000"& strobe2 &"000" when "00000",     -- [0]
									"000"& strobe2 &"000" when "00001",      -- [1]
									--------------------------------------G solid
									"0001000" when "00010",      -- [2]
									"0001000" when "00011",    -- [3]
									"0001000" when "00100",     -- [4]
									"0001000" when "00101",     -- [5]
									--------------------------------------A solid
									"1000000" when "00110",    	 -- [6]
									"1000000" when "00111",    -- [7]
									----------------------------R Solid
									"0000001" when "01000",    -- [8]
									"0000001" when "01001",  	 -- [9]
									"0000001" when "01010",   		 -- [A]
									"0000001" when "01011",    	 -- [b]
									"0000001" when "01100",     	 -- [c]
									"0000001" when "01101",     	 -- [d]
									"0000001" when "01110",    	 -- [E]
									"0000001" when "01111",    	 -- [F]
									"0001000" WHEN "10000",
									strobe1 & "000000" WHEN others; --"10001";

with lightStatus select		----------------------------R Solid
					EW  	<= 	"0000001" when "00000",     -- [0]
									"0000001" when "00001",      -- [1]
									"0000001" when "00010",      -- [2]
									"0000001" when "00011",    -- [3]
									"0000001" when "00100",     -- [4]
									"0000001" when "00101",     -- [5]
									"0000001" when "00110",    	 -- [6]
									"0000001" when "00111",    -- [7]
								-----------------------------------G flash
									"000"& strobe2 & "000" when "01000",    -- [8]
									"000"& strobe2 & "000" when "01001",  	 -- [9]
									--------------------------------------G solid
									"0001000" when "01010",   		 -- [A]
									"0001000" when "01011",    	 -- [b]
									"0001000" when "01100",     	 -- [c]
									"0001000" when "01101",     	 -- [d]
									--------------------------------------A solid
									"1000000" when "01110",    	 -- [E]
									"1000000" when "01111",    	 -- [F]
									"0000001" WHEN "10000",
									"000000" & strobe1 when others;--"10001";

--mux for seven seg
MUX: segment7_mux port map(clkin_50, NS,EW, seg7_data, seg7_char1, seg7_char2);


--output for the leds
leds(0) <= Strobe2;
leds(1) <= Strobe1;
leds(5 downto 2)<=lightStatus(3 downto 0);
leds (6)<= sw(0) or sw(1);
leds (7)<= latchNSOut or latchEWOut;


-- used for simulations
--	leds(0) <= clken1;
--	leds(1) <= Strobe1;
--	leds(2) <= clken2;
--	leds(3) <= Strobe2;
--	leds(7 downto 4) <= Stae Machine state numbers


END SimpleCircuit;