module comp(a, b, A_gt_B, A_eq_B, A_lt_B);
    input [1:0] a, b;
    output A_gt_B, A_eq_B, A_lt_B;
    function [2:0] judge;
        input [1:0] a, b;
        begin
            if(a == b)
                judge = 3'b010;
            else
                if(a < b)
                    judge = 3'b001;
                else
                    judge = 3'b100;
        end
    endfunction
    assign A_gt_B = (judge(a, b) >> 2) & 1'b1;
    assign A_eq_B = (judge(a, b) >> 1) & 1'b1;
    assign A_lt_B = judge(a, b) & 1'b1;
endmodule
module main;
    reg[1:0] a, b;
    wire A_gt_B, A_eq_B, A_lt_B;
    initial
    begin
        $dumpfile("comp_vcd");
        $dumpvars(0, main);
        $monitor("%t: a:%b b:%b A > B:%b A = B:%b A < B:%b", $time, a, b, A_gt_B, A_eq_B, A_lt_B);
        a <= 0;
        b <= 0;
        #16
        $finish;
    end
    always #1
        a<=a+1;
    always #4
    b<=b+1;
    comp inst0 (a, b, A_gt_B, A_eq_B, A_lt_B);
endmodule