From: https://archive.rebeccablacktech.com/g/thread/66677606

In Short:
Intel management wanted a massive shrink that would ensure their domination of the process market and attract customers to their fabs. The load combined with budget cuts and layoffs in the manufacturing group killed 10nm.


In Long:
There were three primary mistakes Intel made, Cobalt Metal Layers, Contact Over Active Gate (COAG), and plain ole hubris.

In 2013, Intel was late. The Self Aligned Dual Patterning (SADP) required by the feature size of 14nm had a bad learning curve, yields were very bad at first, to the point where Broadwell was mostly a paper launch in 2014, 2 quarters behind schedule. This was not a critical problem and it was fixed gradually, such that Skylake was not delayed. Behind the scenes though, the long ramp time created a problem. As Intel has only a single (large) process development team, not leapfrogging teams, the 14nm delay led to a delay of 10nm. The specifications it would shoot for were not set in stone until 2014.

Managers gave them a difficult task. To win mobile they had to be power efficient and dense. To win desktop they needed to be fast. To win servers they needed excellent yields. And above all they needed to be better than the competition to attract new customers.
Inorder to reach the goals set by management, the manufacturing group had to get creative. To that end a number of techniques never put into a production process before were adopted. COAG, SAQP, Cobalt, Ruthenium Liners, Tungsten contacts, single dummy gate, etc. This push is directly what led to the death of the process. Of those, only really COAG and Cobalt are causing the issues. I'll go into the specific problems next post.

If anyone is to blame, its the management, and their firing of the CEO with a bullshit reason shows the board will not accept responsibility for the companies failings. They will not come clean in the foreseeable future. Their foundries are virtually dead after all the firings and cost cutting.

^^Cobalt contacts (to replace tungsten ones)****

The idea with Contact Over Active Gate is that instead of extending a gate such that it connects up with a contact to the side (thus using space on the side), the Contact stretches directly from the metal layer to the gate, rather than laying ontop the substrate. This means there is NO room for error on manufacturing. The slightest misalignment leads to fucked contacts. Thermal expansion, microvibrations from people walking nearby, changes in air pressure, imagine a cause, and it'll affect yields. I bet you the bloody position of the Moon can affect it.
This kills the yields.

To hit the targets Intel set, a minimum metal pitch of 36nm was selected. When you have Copper wires on a process they need to have a liner around them, this prevents diffusion, electromigration, and other nasty electrical fun. But this liner needs to be a certain thickness, so when the overall size of the wire gets smaller, the liner takes up a larger portion of it. Below 40nm it was thought that Cobalt would have superior electrical properities, despite it having a higher bulk electrical resistance. Its far more resistant to electromigration and needs a miniscule barrier to prevent it, while its resistance decreases at a slower rate as the wire size gets smaller.
However, Intel overlooked two key problems: ductility/malleability, and thermal conductivity. Even at those tiny levels, Copper wires would be able to handle thermal expansion mechanical loads, bending and stretching ever so slightly as a processor made its rounds. And copper is Very good at transferring heat, letting the lower metal layers sink heat into the upper ones. Meanwhile Cobalt is hilariously brittle and has a sixth the thermal conductivity as Copper. On operation hot spots start to form, heat can't get away, brittle nature creates microfractures, and higher voltage to cross the fracture boundaries. Means the voltage/frequency curve is hilariously bad.
This kills the performance and power usage.

So where does it leave us at?
10nm was meant to launch end of 2015, after 14nm this was pushed to 2016. It is now Q3 2018 and the only 10nm chip is a minuscule dual core made in a one-off batch of 100k units that took 6 months to assemble. Yields are sub 1%, the GPU doesn't function, and power usage is higher than 22nm.

TSMC and GloFlo are both ramping their 7nm processes, and while they're comparable to the 10nm in density, they actually fucking work. They both are using SAQP for the transistors, but the choice of 40nm metal pitch allowed for SADP for that particular layer. GloFlo is using Copper with a Cobalt/Tantalum liner while TSMC is using straight Copper/Tantalum. Neither fucked with COAG or Single Dummy, but GloFlo is using Cobalt contacts.

TSMC 7nm is in volume production now, GloFlo will enter it in a few months. Consumer products on both of them will enter the market in mid-2019. They're both going to outperform Intel's 10nm. Their manufacturing group failed at all levels. To make matters worse they didn't even bother backporting their improved cores to 14nm. Icelake has been inhouse since early 2017. The design is finalized, they just can't make the damn thing and didn't backport it. Management thought they couldn't fail.