reg [7:0] counter;

wire [8:0] subtract = { 1'b0, counter[7:0] } - 1'b1;
...
counter[7:0] <= 8'h02;    // initialize counter somewhere in always construct: wire[8] will get set on second cycle and catched on 3rd
...
counter[7:0] <= subtract[7:0]; // update counter at every clock

wire [8:0] add = { 1'b0, counter[7:0] } + 1'b1;
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counter[7:0] <= 8'hfd;    // initialize counter somewhere in always construct: wire[8] will get set on second cycle and catched on 3rd
...
counter[7:0] <= add[7:0]; // update counter at every clock