module seg7(

	input clk,
	input [3:0] addra,
	output reg [7:0] an,
	output reg [6:0] SEG

    );

	 initial an = 8'b11111110;

	 wire [3:0] douta;

	 reg [3:0] count;
	 reg [24:0] count_en;
	 wire ce;

	 always @(posedge clk)
	 begin

		if(count_en == 20000000) count_en <= 0;
		else count_en <= count_en + 1;

	 end

	 assign ce = (count_en == 20000000) ? 1'b1 : 1'b0;



	 reg [16:0] dynamic_count;
	 wire dyn_ce;


	 always @(posedge clk)
	 begin

		if(dynamic_count == 100000) dynamic_count <= 0;
		else dynamic_count <= dynamic_count + 1;

	 end

	 assign dyn_ce = (dynamic_count == 100000) ? 1'b1 : 1'b0;

	 always @(posedge clk)
	 begin

	 if(dyn_ce)
	 begin
	 an[7:1] = an[6:0];
	 an[0] = an[7];
	 end
	 end

/*
	always @(posedge clk)
	begin

		if(ce)
		begin
			if(count < 9) count <= count + 1'b1;
			else count <= 1'b0;
		end

	end
*/
	  always @(douta)
      case (douta)
			 4'b0000 : SEG = 7'b1000000;   // 0
          4'b0001 : SEG = 7'b1111001;   // 1
          4'b0010 : SEG = 7'b0100100;   // 2
          4'b0011 : SEG = 7'b0110000;   // 3
          4'b0100 : SEG = 7'b0011001;   // 4
          4'b0101 : SEG = 7'b0010010;   // 5
          4'b0110 : SEG = 7'b0000010;   // 6
          4'b0111 : SEG = 7'b1111000;   // 7
          4'b1000 : SEG = 7'b0000000;   // 8
          4'b1001 : SEG = 7'b0010000;   // 9
          4'b1010 : SEG = 7'b0001000;   // A
          4'b1011 : SEG = 7'b0000011;   // b
          4'b1100 : SEG = 7'b1000110;   // C
          4'b1101 : SEG = 7'b0100001;   // d
          4'b1110 : SEG = 7'b0000110;   // E
          4'b1111 : SEG = 7'b0001110;   // F
          default : SEG = 7'b1000000;   // 0
      endcase


	bram instancja (
  .clka(clk), // input clka
  .addra(addra), // input [3 : 0] addra
  .douta(douta) // output [3 : 0] douta
);






endmodule