****************************************
Report : timing
        -path full
        -delay max
        -max_paths 1
Design : FFT64
Version: C-2009.06-SP5
Date   : Wed Apr 26 22:17:19 2017
****************************************

 # A fanout number of 1000 was used for high fanout net computations.

Operating Conditions: typical   Library: typical
Wire Load Model Mode: top

  Startpoint: In0[0] (input port)
  Endpoint: U1/U_00/Out_reg[0]
            (rising edge-triggered flip-flop clocked by clk)
  Path Group: clk
  Path Type: max

  Point                                                   Incr       Path
  --------------------------------------------------------------------------
  clock (input port clock) (rise edge)                    0.00       0.00
  input external delay                                    0.00       0.00 r
  In0[0] (in)                                             0.00       0.00 r
  U1/U_00/Out_reg[0]/next_state (**SEQGEN**)              0.00       0.00 r
  data arrival time                                                  0.00

  clock clk (rise edge)                                  10.00      10.00
  clock network delay (ideal)                             0.00      10.00
  U1/U_00/Out_reg[0]/clocked_on (**SEQGEN**)              0.00      10.00 r
  library setup time                                      0.00      10.00
  data required time                                                10.00
  --------------------------------------------------------------------------
  data required time                                                10.00
  data arrival time                                                  0.00
  --------------------------------------------------------------------------
  slack (MET)                                                       10.00


  Startpoint: U180/Out0_reg[0]
              (rising edge-triggered flip-flop clocked by clk)
  Endpoint: Out0[0] (output port)
  Path Group: default
  Path Type: max

  Point                                                   Incr       Path
  --------------------------------------------------------------------------
  U180/Out0_reg[0]/clocked_on (**SEQGEN**)                0.00 #     0.00 r
  U180/Out0_reg[0]/Q (**SEQGEN**)                         0.00       0.00 r
  Out0[0] (out)                                           0.00       0.00 r
  data arrival time                                                  0.00

  max_delay                                               0.00       0.00
  output external delay                                   0.00       0.00
  data required time                                                 0.00
  --------------------------------------------------------------------------
  data required time                                                 0.00
  data arrival time                                                  0.00
  --------------------------------------------------------------------------
  slack (MET)                                                        0.00


1