u-boot dsi tegra

U-Boot 2020.01-rc5-00019-g0696dc055c-dirty (Jun 03 2020 - 06:53:36 +0300)

SoC: tegra124
Reset cause: SW_MAIN
Model: XIAOMI MOCHA
Board: Xiaomi/NVIDIA mocha
DRAM:  2 GiB
tegra124_dc_bind: Frame buffer size 600000
tegra124_dc_bind: Frame buffer size 600000

dc: print panel config
timing->hactive.typ = 1536
timing->vactive.typ = 2048
timing->pixelclock.typ = 214824960
timing->hfront_porch.typ = 136
timing->hsync_len.typ = 28
timing->hback_porch.typ = 28
timing->vfront_porch.typ  14
timing->vsync_len.typ = 2
timing->vback_porch.typ = 8
panel_bits_per_pixel = 18

dc: init done
update_display_shift_clock_divider: ShiftClockDiv=1
dc: done to configure display mode
tegra_dsi_probe: probe 54300000
tegra_dsi_probe: probe 54400000
tegra_ganged: master = 54400000, slave = 54300000
tegra MIPI probe complete
MIPI calibration done
tegra_dsi_attach: link1 inited
MIPI calibration done
clock_set_display_rate: PLLD=645000000 ref=12000000, m/n/p/cpcon=4/215/0/3
update_display_shift_clock_divider: ShiftClockDiv=1
tegra_dsi_attach: link2 inited
sharp_power_init: Start
sharp_power_init: Find PMIC I2C chip
sharp_power_init: PMU i2c_read 81<-00 returned 0
sharp_power_init: PMU i2c_read 82<-00 returned 0
sharp_power_init: power init complete
DSI LINK1: OK
DSI LINK2: OK
Display init complete
Non-burst video mode with sync events
Non-burst video mode with sync events
display_panel_dsi_init: success
dc: update window sucessfull
display_init: ready
tegra124_dc_init: done
DC init took 728 ms