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Mikek_GodTEc

Fairwaves_compile

Mikek_GodTEc
Dec 19th, 2021
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  1. (Litex_venv) mikek@mikek-M6700:~/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets$
  2. (Litex_venv) mikek@mikek-M6700:~/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets$
  3. (Litex_venv) mikek@mikek-M6700:~/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets$ ./fairwaves_xtrx.py --build
  4. INFO:SoC: __ _ __ _ __
  5. INFO:SoC: / / (_) /____ | |/_/
  6. INFO:SoC: / /__/ / __/ -_)> <
  7. INFO:SoC: /____/_/\__/\__/_/|_|
  8. INFO:SoC: Build your hardware, easily!
  9. INFO:SoC:--------------------------------------------------------------------------------
  10. INFO:SoC:Creating SoC... (2021-12-19 18:45:35)
  11. INFO:SoC:--------------------------------------------------------------------------------
  12. INFO:SoC:FPGA device : xc7a50tcpg236-2.
  13. INFO:SoC:System clock: 125.000MHz.
  14. INFO:SoCBusHandler:Creating Bus Handler...
  15. INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
  16. INFO:SoCBusHandler:Adding reserved Bus Regions...
  17. INFO:SoCBusHandler:Bus Handler created.
  18. INFO:SoCCSRHandler:Creating CSR Handler...
  19. INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
  20. INFO:SoCCSRHandler:Adding reserved CSRs...
  21. INFO:SoCCSRHandler:CSR Handler created.
  22. INFO:SoCIRQHandler:Creating IRQ Handler...
  23. INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
  24. INFO:SoCIRQHandler:Adding reserved IRQs...
  25. INFO:SoCIRQHandler:IRQ Handler created.
  26. INFO:SoC:--------------------------------------------------------------------------------
  27. INFO:SoC:Initial SoC:
  28. INFO:SoC:--------------------------------------------------------------------------------
  29. INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
  30. INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
  31. INFO:SoC:IRQ Handler (up to 32 Locations).
  32. INFO:SoC:--------------------------------------------------------------------------------
  33. INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False.
  34. INFO:SoC:CPU overriding rom mapping from 0x0 to 0x0.
  35. INFO:SoC:CPU overriding sram mapping from 0x1000000 to 0x10000000.
  36. INFO:SoC:CPU overriding main_ram mapping from 0x40000000 to 0x40000000.
  37. INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
  38. INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
  39. INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00020000, Mode: R, Cached: True Linker: False.
  40. INFO:SoCBusHandler:rom added as Bus Slave.
  41. INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00020000, Mode: R, Cached: True Linker: False.
  42. INFO:SoCBusHandler:sram Region added at Origin: 0x10000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
  43. INFO:SoCBusHandler:sram added as Bus Slave.
  44. INFO:SoC:RAM sram added Origin: 0x10000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
  45. INFO:SoCIRQHandler:uart IRQ allocated at Location 0.
  46. INFO:SoCIRQHandler:timer0 IRQ allocated at Location 1.
  47. INFO:S7PLL:Creating S7PLL, speedgrade -2.
  48. INFO:S7PLL:Registering Single Ended ClkIn of 60.00MHz.
  49. INFO:S7PLL:Creating ClkOut0 sys of 125.00MHz (+-10000.00ppm).
  50. INFO:S7PLL:Config:
  51. divclk_divide : 1
  52. clkout0_freq : 124.00MHz
  53. clkout0_divide: 15
  54. clkout0_phase : 0.00°
  55. vco : 1860.00MHz
  56. clkfbout_mult : 31
  57. INFO:SoCBusHandler:csr Region added at Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False.
  58. INFO:SoCBusHandler:csr added as Bus Slave.
  59. INFO:SoCCSRHandler:bridge added as CSR Master.
  60. INFO:SoCBusHandler:Interconnect: InterconnectShared (2 <-> 3).
  61. INFO:SoCCSRHandler:ctrl CSR allocated at Location 0.
  62. INFO:SoCCSRHandler:identifier_mem CSR allocated at Location 1.
  63. INFO:SoCCSRHandler:leds CSR allocated at Location 2.
  64. INFO:SoCCSRHandler:timer0 CSR allocated at Location 3.
  65. INFO:SoCCSRHandler:uart CSR allocated at Location 4.
  66. INFO:SoC:--------------------------------------------------------------------------------
  67. INFO:SoC:Finalized SoC:
  68. INFO:SoC:--------------------------------------------------------------------------------
  69. INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
  70. IO Regions: (1)
  71. io0 : Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False
  72. Bus Regions: (3)
  73. rom : Origin: 0x00000000, Size: 0x00020000, Mode: R, Cached: True Linker: False
  74. sram : Origin: 0x10000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False
  75. csr : Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False
  76. Bus Masters: (2)
  77. - cpu_bus0
  78. - cpu_bus1
  79. Bus Slaves: (3)
  80. - rom
  81. - sram
  82. - csr
  83. INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
  84. CSR Locations: (5)
  85. - ctrl : 0
  86. - identifier_mem : 1
  87. - leds : 2
  88. - timer0 : 3
  89. - uart : 4
  90. INFO:SoC:IRQ Handler (up to 32 Locations).
  91. IRQ Locations: (2)
  92. - uart : 0
  93. - timer0 : 1
  94. INFO:SoC:--------------------------------------------------------------------------------
  95. make: Entering directory '/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/libc'
  96. make: Nothing to be done for 'all'.
  97. make: Leaving directory '/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/libc'
  98. make: Entering directory '/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/libcompiler_rt'
  99. make: Nothing to be done for 'all'.
  100. make: Leaving directory '/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/libcompiler_rt'
  101. make: Entering directory '/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/libbase'
  102. CC console.o
  103. CC system.o
  104. CC memtest.o
  105. CC uart.o
  106. CC spiflash.o
  107. CC i2c.o
  108. AR libbase.a
  109. make: Leaving directory '/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/libbase'
  110. make: Entering directory '/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/libfatfs'
  111. make: Nothing to be done for 'all'.
  112. make: Leaving directory '/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/libfatfs'
  113. make: Entering directory '/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/liblitespi'
  114. CC spiflash.o
  115. AR liblitespi.a
  116. make: Leaving directory '/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/liblitespi'
  117. make: Entering directory '/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/liblitedram'
  118. CC sdram.o
  119. CC bist.o
  120. CC sdram_dbg.o
  121. AR liblitedram.a
  122. make: Leaving directory '/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/liblitedram'
  123. make: Entering directory '/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/libliteeth'
  124. CC udp.o
  125. CC mdio.o
  126. AR libliteeth.a
  127. make: Leaving directory '/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/libliteeth'
  128. make: Entering directory '/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/liblitesdcard'
  129. CC sdcard.o
  130. CC spisdcard.o
  131. AR liblitesdcard.a
  132. make: Leaving directory '/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/liblitesdcard'
  133. make: Entering directory '/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/liblitesata'
  134. CC sata.o
  135. AR liblitesata.a
  136. make: Leaving directory '/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/liblitesata'
  137. make: Entering directory '/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/bios'
  138. CC isr.o
  139. CC boot.o
  140. CC cmd_bios.o
  141. CC cmd_mem.o
  142. CC cmd_boot.o
  143. CC cmd_i2c.o
  144. CC cmd_spiflash.o
  145. CC cmd_litedram.o
  146. CC cmd_liteeth.o
  147. CC cmd_litesdcard.o
  148. CC cmd_litesata.o
  149. CC sim_debug.o
  150. CC main.o
  151. CC bios.elf
  152. chmod -x bios.elf
  153. OBJCOPY bios.bin
  154. chmod -x bios.bin
  155. python3 -m litex.soc.software.mkmscimg bios.bin --little
  156. python3 -m litex.soc.software.memusage bios.elf /home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/bios/../include/generated/regions.ld riscv64-unknown-elf
  157.  
  158. ROM usage: 20.07KiB (15.68%)
  159. RAM usage: 1.60KiB (20.02%)
  160.  
  161. make: Leaving directory '/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/bios'
  162. INFO:SoC:Initializing ROM rom with contents (Size: 0x5058).
  163. INFO:SoC:Auto-Resizing ROM rom from 0x20000 to 0x5058.
  164.  
  165. ****** Vivado v2021.2 (64-bit)
  166. **** SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
  167. **** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
  168. ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
  169.  
  170. source fairwaves_xtrx.tcl
  171. # create_project -force -name fairwaves_xtrx -part xc7a50tcpg236-2
  172. create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2600.227 ; gain = 3.992 ; free physical = 1990 ; free virtual = 12240
  173. # set_msg_config -id {Common 17-55} -new_severity {Warning}
  174. # read_verilog {/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v}
  175. # read_verilog {/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v}
  176. # read_xdc fairwaves_xtrx.xdc
  177. # set_property PROCESSING_ORDER EARLY [get_files fairwaves_xtrx.xdc]
  178. # synth_design -directive default -top fairwaves_xtrx -part xc7a50tcpg236-2
  179. Command: synth_design -directive default -top fairwaves_xtrx -part xc7a50tcpg236-2
  180. Starting synth_design
  181. Attempting to get a license for feature 'Synthesis' and/or device 'xc7a50t'
  182. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a50t'
  183. INFO: [Device 21-403] Loading part xc7a50tcpg236-2
  184. INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
  185. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
  186. INFO: [Synth 8-7075] Helper process launched with PID 79650
  187. ---------------------------------------------------------------------------------
  188. Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2600.406 ; gain = 0.000 ; free physical = 330 ; free virtual = 10619
  189. ---------------------------------------------------------------------------------
  190. INFO: [Synth 8-6157] synthesizing module 'fairwaves_xtrx' [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:20]
  191. INFO: [Synth 8-3876] $readmem data file 'mem.init' is read successfully [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1753]
  192. INFO: [Synth 8-3876] $readmem data file 'mem_1.init' is read successfully [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1768]
  193. INFO: [Synth 8-3876] $readmem data file 'mem_2.init' is read successfully [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1791]
  194. INFO: [Synth 8-155] case statement is not full and has no default [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1494]
  195. INFO: [Synth 8-155] case statement is not full and has no default [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1518]
  196. INFO: [Synth 8-155] case statement is not full and has no default [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1530]
  197. INFO: [Synth 8-155] case statement is not full and has no default [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1585]
  198. INFO: [Synth 8-6157] synthesizing module 'BUFG' [/home/mikek/Documents/Xilinx/tools/Vivado/2021.2/scripts/rt/data/unisim_comp.v:1083]
  199. INFO: [Synth 8-6155] done synthesizing module 'BUFG' (1#1) [/home/mikek/Documents/Xilinx/tools/Vivado/2021.2/scripts/rt/data/unisim_comp.v:1083]
  200. INFO: [Synth 8-6157] synthesizing module 'VexRiscv' [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:46]
  201. INFO: [Synth 8-6157] synthesizing module 'InstructionCache' [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:6025]
  202. WARNING: [Synth 8-6014] Unused sequential element decodeStage_mmuRsp_isIoAccess_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:6302]
  203. WARNING: [Synth 8-6014] Unused sequential element decodeStage_mmuRsp_allowRead_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:6304]
  204. WARNING: [Synth 8-6014] Unused sequential element decodeStage_mmuRsp_allowWrite_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:6305]
  205. WARNING: [Synth 8-6014] Unused sequential element decodeStage_mmuRsp_bypassTranslation_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:6309]
  206. INFO: [Synth 8-6155] done synthesizing module 'InstructionCache' (2#1) [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:6025]
  207. INFO: [Synth 8-6157] synthesizing module 'DataCache' [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:5194]
  208. WARNING: [Synth 8-6014] Unused sequential element tagsWriteLastCmd_valid_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:5899]
  209. WARNING: [Synth 8-6014] Unused sequential element tagsWriteLastCmd_payload_way_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:5900]
  210. WARNING: [Synth 8-6014] Unused sequential element tagsWriteLastCmd_payload_address_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:5901]
  211. WARNING: [Synth 8-6014] Unused sequential element tagsWriteLastCmd_payload_data_valid_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:5902]
  212. WARNING: [Synth 8-6014] Unused sequential element tagsWriteLastCmd_payload_data_error_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:5903]
  213. WARNING: [Synth 8-6014] Unused sequential element tagsWriteLastCmd_payload_data_address_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:5904]
  214. WARNING: [Synth 8-6014] Unused sequential element stageA_request_totalyConsistent_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:5908]
  215. WARNING: [Synth 8-6014] Unused sequential element stageB_request_totalyConsistent_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:5922]
  216. WARNING: [Synth 8-6014] Unused sequential element stageB_mmuRsp_allowExecute_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:5930]
  217. WARNING: [Synth 8-6014] Unused sequential element stageB_mmuRsp_bypassTranslation_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:5933]
  218. WARNING: [Synth 8-6014] Unused sequential element stageB_tagsReadRsp_0_valid_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:5936]
  219. WARNING: [Synth 8-6014] Unused sequential element stageB_tagsReadRsp_0_address_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:5938]
  220. WARNING: [Synth 8-3848] Net io_cpu_writeBack_exclusiveOk in module/entity DataCache does not have driver. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:5236]
  221. INFO: [Synth 8-6155] done synthesizing module 'DataCache' (3#1) [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:5194]
  222. WARNING: [Synth 8-6014] Unused sequential element IBusCachedPlugin_fetchPc_correctionReg_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:2953]
  223. WARNING: [Synth 8-6014] Unused sequential element IBusCachedPlugin_injector_nextPcCalc_valids_2_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:3061]
  224. WARNING: [Synth 8-6014] Unused sequential element IBusCachedPlugin_injector_nextPcCalc_valids_3_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:3062]
  225. WARNING: [Synth 8-6014] Unused sequential element IBusCachedPlugin_injector_nextPcCalc_valids_4_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:3063]
  226. WARNING: [Synth 8-6014] Unused sequential element IBusCachedPlugin_rspCounter_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:4599]
  227. WARNING: [Synth 8-6014] Unused sequential element DBusCachedPlugin_rspCounter_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:4603]
  228. WARNING: [Synth 8-6014] Unused sequential element execute_CsrPlugin_wfiWake_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:4622]
  229. WARNING: [Synth 8-6014] Unused sequential element dataCache_1_io_mem_cmd_rData_uncached_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:3257]
  230. WARNING: [Synth 8-6014] Unused sequential element dataCache_1_io_mem_cmd_rData_last_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:3262]
  231. WARNING: [Synth 8-6014] Unused sequential element dataCache_1_io_mem_cmd_s2mPipe_rData_uncached_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:3273]
  232. WARNING: [Synth 8-6014] Unused sequential element dataCache_1_io_mem_cmd_s2mPipe_rData_last_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:3278]
  233. WARNING: [Synth 8-6014] Unused sequential element CsrPlugin_mcycle_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:4885]
  234. WARNING: [Synth 8-6014] Unused sequential element CsrPlugin_minstret_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:4887]
  235. WARNING: [Synth 8-6014] Unused sequential element decode_to_execute_FORMAL_PC_NEXT_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:2492]
  236. WARNING: [Synth 8-6014] Unused sequential element execute_to_memory_FORMAL_PC_NEXT_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:2491]
  237. WARNING: [Synth 8-6014] Unused sequential element memory_to_writeBack_FORMAL_PC_NEXT_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:2490]
  238. WARNING: [Synth 8-6014] Unused sequential element decode_to_execute_CSR_READ_OPCODE_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:2505]
  239. WARNING: [Synth 8-6014] Unused sequential element CsrPlugin_mtvec_mode_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:5179]
  240. WARNING: [Synth 8-3848] Net IBusCachedPlugin_cache_io_cpu_fetch_isRemoved in module/entity VexRiscv does not have driver. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:80]
  241. WARNING: [Synth 8-3848] Net IBusCachedPlugin_mmuBus_rsp_bypassTranslation in module/entity VexRiscv does not have driver. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:643]
  242. WARNING: [Synth 8-3848] Net DBusCachedPlugin_mmuBus_rsp_bypassTranslation in module/entity VexRiscv does not have driver. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:671]
  243. WARNING: [Synth 8-3848] Net dataCache_1_io_cpu_writeBack_fence_SW in module/entity VexRiscv does not have driver. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:94]
  244. WARNING: [Synth 8-3848] Net dataCache_1_io_cpu_writeBack_fence_SR in module/entity VexRiscv does not have driver. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:95]
  245. WARNING: [Synth 8-3848] Net dataCache_1_io_cpu_writeBack_fence_SO in module/entity VexRiscv does not have driver. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:96]
  246. WARNING: [Synth 8-3848] Net dataCache_1_io_cpu_writeBack_fence_SI in module/entity VexRiscv does not have driver. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:97]
  247. WARNING: [Synth 8-3848] Net dataCache_1_io_cpu_writeBack_fence_PW in module/entity VexRiscv does not have driver. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:98]
  248. WARNING: [Synth 8-3848] Net dataCache_1_io_cpu_writeBack_fence_PR in module/entity VexRiscv does not have driver. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:99]
  249. WARNING: [Synth 8-3848] Net dataCache_1_io_cpu_writeBack_fence_PO in module/entity VexRiscv does not have driver. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:100]
  250. WARNING: [Synth 8-3848] Net dataCache_1_io_cpu_writeBack_fence_PI in module/entity VexRiscv does not have driver. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:101]
  251. WARNING: [Synth 8-3848] Net dataCache_1_io_cpu_writeBack_fence_FM in module/entity VexRiscv does not have driver. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:102]
  252. WARNING: [Synth 8-3848] Net dBus_rsp_payload_last in module/entity VexRiscv does not have driver. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:656]
  253. INFO: [Synth 8-6155] done synthesizing module 'VexRiscv' (4#1) [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:46]
  254. INFO: [Synth 8-6157] synthesizing module 'FD' [/home/mikek/Documents/Xilinx/tools/Vivado/2021.2/scripts/rt/data/unisim_comp.v:27596]
  255. INFO: [Synth 8-6155] done synthesizing module 'FD' (5#1) [/home/mikek/Documents/Xilinx/tools/Vivado/2021.2/scripts/rt/data/unisim_comp.v:27596]
  256. INFO: [Synth 8-6157] synthesizing module 'PLLE2_ADV' [/home/mikek/Documents/Xilinx/tools/Vivado/2021.2/scripts/rt/data/unisim_comp.v:89397]
  257. Parameter CLKFBOUT_MULT bound to: 31 - type: integer
  258. Parameter CLKIN1_PERIOD bound to: 16.666667 - type: double
  259. Parameter CLKOUT0_DIVIDE bound to: 15 - type: integer
  260. Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double
  261. Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
  262. Parameter REF_JITTER1 bound to: 0.010000 - type: double
  263. Parameter STARTUP_WAIT bound to: FALSE - type: string
  264. INFO: [Synth 8-6155] done synthesizing module 'PLLE2_ADV' (6#1) [/home/mikek/Documents/Xilinx/tools/Vivado/2021.2/scripts/rt/data/unisim_comp.v:89397]
  265. WARNING: [Synth 8-7071] port 'CLKOUT1' of module 'PLLE2_ADV' is unconnected for instance 'PLLE2_ADV' [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1955]
  266. WARNING: [Synth 8-7071] port 'CLKOUT2' of module 'PLLE2_ADV' is unconnected for instance 'PLLE2_ADV' [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1955]
  267. WARNING: [Synth 8-7071] port 'CLKOUT3' of module 'PLLE2_ADV' is unconnected for instance 'PLLE2_ADV' [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1955]
  268. WARNING: [Synth 8-7071] port 'CLKOUT4' of module 'PLLE2_ADV' is unconnected for instance 'PLLE2_ADV' [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1955]
  269. WARNING: [Synth 8-7071] port 'CLKOUT5' of module 'PLLE2_ADV' is unconnected for instance 'PLLE2_ADV' [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1955]
  270. WARNING: [Synth 8-7071] port 'DO' of module 'PLLE2_ADV' is unconnected for instance 'PLLE2_ADV' [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1955]
  271. WARNING: [Synth 8-7071] port 'DRDY' of module 'PLLE2_ADV' is unconnected for instance 'PLLE2_ADV' [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1955]
  272. WARNING: [Synth 8-7071] port 'CLKIN2' of module 'PLLE2_ADV' is unconnected for instance 'PLLE2_ADV' [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1955]
  273. WARNING: [Synth 8-7071] port 'CLKINSEL' of module 'PLLE2_ADV' is unconnected for instance 'PLLE2_ADV' [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1955]
  274. WARNING: [Synth 8-7071] port 'DADDR' of module 'PLLE2_ADV' is unconnected for instance 'PLLE2_ADV' [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1955]
  275. WARNING: [Synth 8-7071] port 'DCLK' of module 'PLLE2_ADV' is unconnected for instance 'PLLE2_ADV' [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1955]
  276. WARNING: [Synth 8-7071] port 'DEN' of module 'PLLE2_ADV' is unconnected for instance 'PLLE2_ADV' [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1955]
  277. WARNING: [Synth 8-7071] port 'DI' of module 'PLLE2_ADV' is unconnected for instance 'PLLE2_ADV' [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1955]
  278. WARNING: [Synth 8-7071] port 'DWE' of module 'PLLE2_ADV' is unconnected for instance 'PLLE2_ADV' [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1955]
  279. WARNING: [Synth 8-7023] instance 'PLLE2_ADV' of module 'PLLE2_ADV' has 21 connections declared, but only 7 given [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1955]
  280. INFO: [Synth 8-6157] synthesizing module 'FDPE' [/home/mikek/Documents/Xilinx/tools/Vivado/2021.2/scripts/rt/data/unisim_comp.v:27777]
  281. Parameter INIT bound to: 1'b1
  282. INFO: [Synth 8-6155] done synthesizing module 'FDPE' (7#1) [/home/mikek/Documents/Xilinx/tools/Vivado/2021.2/scripts/rt/data/unisim_comp.v:27777]
  283. WARNING: [Synth 8-6014] Unused sequential element main_basesoc_scratch_re_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1513]
  284. WARNING: [Synth 8-6014] Unused sequential element main_basesoc_bus_errors_re_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1514]
  285. WARNING: [Synth 8-6014] Unused sequential element main_basesoc_load_re_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1560]
  286. WARNING: [Synth 8-6014] Unused sequential element main_basesoc_reload_re_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1564]
  287. WARNING: [Synth 8-6014] Unused sequential element main_basesoc_en_re_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1568]
  288. WARNING: [Synth 8-6014] Unused sequential element main_basesoc_value_re_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1573]
  289. WARNING: [Synth 8-6014] Unused sequential element main_basesoc_status_re_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1574]
  290. WARNING: [Synth 8-6014] Unused sequential element main_basesoc_enable_re_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1582]
  291. WARNING: [Synth 8-6014] Unused sequential element main_basesoc_uartcrossover_txfull_re_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1636]
  292. WARNING: [Synth 8-6014] Unused sequential element main_basesoc_uartcrossover_rxempty_re_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1637]
  293. WARNING: [Synth 8-6014] Unused sequential element main_basesoc_uartcrossover_status_re_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1638]
  294. WARNING: [Synth 8-6014] Unused sequential element main_basesoc_uartcrossover_enable_re_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1646]
  295. WARNING: [Synth 8-6014] Unused sequential element main_basesoc_uartcrossover_txempty_re_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1647]
  296. WARNING: [Synth 8-6014] Unused sequential element main_basesoc_uartcrossover_rxfull_re_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1648]
  297. WARNING: [Synth 8-6014] Unused sequential element main_basesoc_xover_txfull_re_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1649]
  298. WARNING: [Synth 8-6014] Unused sequential element main_basesoc_xover_rxempty_re_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1650]
  299. WARNING: [Synth 8-6014] Unused sequential element main_basesoc_xover_status_re_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1651]
  300. WARNING: [Synth 8-6014] Unused sequential element main_basesoc_xover_enable_re_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1659]
  301. WARNING: [Synth 8-6014] Unused sequential element main_basesoc_xover_txempty_re_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1660]
  302. WARNING: [Synth 8-6014] Unused sequential element main_basesoc_xover_rxfull_re_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1661]
  303. WARNING: [Synth 8-6014] Unused sequential element storage_dat0_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1811]
  304. WARNING: [Synth 8-6014] Unused sequential element storage_1_dat0_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1832]
  305. WARNING: [Synth 8-6014] Unused sequential element storage_2_dat0_reg was removed. [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1853]
  306. INFO: [Synth 8-6155] done synthesizing module 'fairwaves_xtrx' (8#1) [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:20]
  307. WARNING: [Synth 8-7129] Port io_cpu_writeBack_exclusiveOk in module DataCache is either unconnected or has no load
  308. WARNING: [Synth 8-7129] Port io_cpu_execute_address[31] in module DataCache is either unconnected or has no load
  309. WARNING: [Synth 8-7129] Port io_cpu_execute_address[30] in module DataCache is either unconnected or has no load
  310. WARNING: [Synth 8-7129] Port io_cpu_execute_address[29] in module DataCache is either unconnected or has no load
  311. WARNING: [Synth 8-7129] Port io_cpu_execute_address[28] in module DataCache is either unconnected or has no load
  312. WARNING: [Synth 8-7129] Port io_cpu_execute_address[27] in module DataCache is either unconnected or has no load
  313. WARNING: [Synth 8-7129] Port io_cpu_execute_address[26] in module DataCache is either unconnected or has no load
  314. WARNING: [Synth 8-7129] Port io_cpu_execute_address[25] in module DataCache is either unconnected or has no load
  315. WARNING: [Synth 8-7129] Port io_cpu_execute_address[24] in module DataCache is either unconnected or has no load
  316. WARNING: [Synth 8-7129] Port io_cpu_execute_address[23] in module DataCache is either unconnected or has no load
  317. WARNING: [Synth 8-7129] Port io_cpu_execute_address[22] in module DataCache is either unconnected or has no load
  318. WARNING: [Synth 8-7129] Port io_cpu_execute_address[21] in module DataCache is either unconnected or has no load
  319. WARNING: [Synth 8-7129] Port io_cpu_execute_address[20] in module DataCache is either unconnected or has no load
  320. WARNING: [Synth 8-7129] Port io_cpu_execute_address[19] in module DataCache is either unconnected or has no load
  321. WARNING: [Synth 8-7129] Port io_cpu_execute_address[18] in module DataCache is either unconnected or has no load
  322. WARNING: [Synth 8-7129] Port io_cpu_execute_address[17] in module DataCache is either unconnected or has no load
  323. WARNING: [Synth 8-7129] Port io_cpu_execute_address[16] in module DataCache is either unconnected or has no load
  324. WARNING: [Synth 8-7129] Port io_cpu_execute_address[15] in module DataCache is either unconnected or has no load
  325. WARNING: [Synth 8-7129] Port io_cpu_execute_address[14] in module DataCache is either unconnected or has no load
  326. WARNING: [Synth 8-7129] Port io_cpu_execute_address[13] in module DataCache is either unconnected or has no load
  327. WARNING: [Synth 8-7129] Port io_cpu_execute_address[12] in module DataCache is either unconnected or has no load
  328. WARNING: [Synth 8-7129] Port io_cpu_execute_args_totalyConsistent in module DataCache is either unconnected or has no load
  329. WARNING: [Synth 8-7129] Port io_cpu_memory_address[31] in module DataCache is either unconnected or has no load
  330. WARNING: [Synth 8-7129] Port io_cpu_memory_address[30] in module DataCache is either unconnected or has no load
  331. WARNING: [Synth 8-7129] Port io_cpu_memory_address[29] in module DataCache is either unconnected or has no load
  332. WARNING: [Synth 8-7129] Port io_cpu_memory_address[28] in module DataCache is either unconnected or has no load
  333. WARNING: [Synth 8-7129] Port io_cpu_memory_address[27] in module DataCache is either unconnected or has no load
  334. WARNING: [Synth 8-7129] Port io_cpu_memory_address[26] in module DataCache is either unconnected or has no load
  335. WARNING: [Synth 8-7129] Port io_cpu_memory_address[25] in module DataCache is either unconnected or has no load
  336. WARNING: [Synth 8-7129] Port io_cpu_memory_address[24] in module DataCache is either unconnected or has no load
  337. WARNING: [Synth 8-7129] Port io_cpu_memory_address[23] in module DataCache is either unconnected or has no load
  338. WARNING: [Synth 8-7129] Port io_cpu_memory_address[22] in module DataCache is either unconnected or has no load
  339. WARNING: [Synth 8-7129] Port io_cpu_memory_address[21] in module DataCache is either unconnected or has no load
  340. WARNING: [Synth 8-7129] Port io_cpu_memory_address[20] in module DataCache is either unconnected or has no load
  341. WARNING: [Synth 8-7129] Port io_cpu_memory_address[19] in module DataCache is either unconnected or has no load
  342. WARNING: [Synth 8-7129] Port io_cpu_memory_address[18] in module DataCache is either unconnected or has no load
  343. WARNING: [Synth 8-7129] Port io_cpu_memory_address[17] in module DataCache is either unconnected or has no load
  344. WARNING: [Synth 8-7129] Port io_cpu_memory_address[16] in module DataCache is either unconnected or has no load
  345. WARNING: [Synth 8-7129] Port io_cpu_memory_address[15] in module DataCache is either unconnected or has no load
  346. WARNING: [Synth 8-7129] Port io_cpu_memory_address[14] in module DataCache is either unconnected or has no load
  347. WARNING: [Synth 8-7129] Port io_cpu_memory_address[13] in module DataCache is either unconnected or has no load
  348. WARNING: [Synth 8-7129] Port io_cpu_memory_address[12] in module DataCache is either unconnected or has no load
  349. WARNING: [Synth 8-7129] Port io_cpu_memory_mmuRsp_allowExecute in module DataCache is either unconnected or has no load
  350. WARNING: [Synth 8-7129] Port io_cpu_memory_mmuRsp_bypassTranslation in module DataCache is either unconnected or has no load
  351. WARNING: [Synth 8-7129] Port io_cpu_writeBack_isUser in module DataCache is either unconnected or has no load
  352. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[31] in module DataCache is either unconnected or has no load
  353. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[30] in module DataCache is either unconnected or has no load
  354. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[29] in module DataCache is either unconnected or has no load
  355. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[28] in module DataCache is either unconnected or has no load
  356. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[27] in module DataCache is either unconnected or has no load
  357. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[26] in module DataCache is either unconnected or has no load
  358. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[25] in module DataCache is either unconnected or has no load
  359. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[24] in module DataCache is either unconnected or has no load
  360. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[23] in module DataCache is either unconnected or has no load
  361. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[22] in module DataCache is either unconnected or has no load
  362. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[21] in module DataCache is either unconnected or has no load
  363. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[20] in module DataCache is either unconnected or has no load
  364. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[19] in module DataCache is either unconnected or has no load
  365. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[18] in module DataCache is either unconnected or has no load
  366. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[17] in module DataCache is either unconnected or has no load
  367. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[16] in module DataCache is either unconnected or has no load
  368. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[15] in module DataCache is either unconnected or has no load
  369. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[14] in module DataCache is either unconnected or has no load
  370. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[13] in module DataCache is either unconnected or has no load
  371. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[12] in module DataCache is either unconnected or has no load
  372. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[11] in module DataCache is either unconnected or has no load
  373. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[10] in module DataCache is either unconnected or has no load
  374. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[9] in module DataCache is either unconnected or has no load
  375. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[8] in module DataCache is either unconnected or has no load
  376. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[7] in module DataCache is either unconnected or has no load
  377. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[6] in module DataCache is either unconnected or has no load
  378. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[5] in module DataCache is either unconnected or has no load
  379. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[4] in module DataCache is either unconnected or has no load
  380. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[3] in module DataCache is either unconnected or has no load
  381. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[2] in module DataCache is either unconnected or has no load
  382. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[1] in module DataCache is either unconnected or has no load
  383. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[0] in module DataCache is either unconnected or has no load
  384. WARNING: [Synth 8-7129] Port io_cpu_writeBack_fence_SW in module DataCache is either unconnected or has no load
  385. WARNING: [Synth 8-7129] Port io_cpu_writeBack_fence_SR in module DataCache is either unconnected or has no load
  386. WARNING: [Synth 8-7129] Port io_cpu_writeBack_fence_SO in module DataCache is either unconnected or has no load
  387. WARNING: [Synth 8-7129] Port io_cpu_writeBack_fence_SI in module DataCache is either unconnected or has no load
  388. WARNING: [Synth 8-7129] Port io_cpu_writeBack_fence_PW in module DataCache is either unconnected or has no load
  389. WARNING: [Synth 8-7129] Port io_cpu_writeBack_fence_PR in module DataCache is either unconnected or has no load
  390. WARNING: [Synth 8-7129] Port io_cpu_writeBack_fence_PO in module DataCache is either unconnected or has no load
  391. WARNING: [Synth 8-7129] Port io_cpu_writeBack_fence_PI in module DataCache is either unconnected or has no load
  392. WARNING: [Synth 8-7129] Port io_cpu_writeBack_fence_FM[3] in module DataCache is either unconnected or has no load
  393. WARNING: [Synth 8-7129] Port io_cpu_writeBack_fence_FM[2] in module DataCache is either unconnected or has no load
  394. WARNING: [Synth 8-7129] Port io_cpu_writeBack_fence_FM[1] in module DataCache is either unconnected or has no load
  395. WARNING: [Synth 8-7129] Port io_cpu_writeBack_fence_FM[0] in module DataCache is either unconnected or has no load
  396. WARNING: [Synth 8-7129] Port io_mem_rsp_payload_last in module DataCache is either unconnected or has no load
  397. WARNING: [Synth 8-7129] Port io_cpu_prefetch_isValid in module InstructionCache is either unconnected or has no load
  398. WARNING: [Synth 8-7129] Port io_cpu_prefetch_pc[31] in module InstructionCache is either unconnected or has no load
  399. WARNING: [Synth 8-7129] Port io_cpu_prefetch_pc[30] in module InstructionCache is either unconnected or has no load
  400. WARNING: [Synth 8-7129] Port io_cpu_prefetch_pc[29] in module InstructionCache is either unconnected or has no load
  401. WARNING: [Synth 8-7129] Port io_cpu_prefetch_pc[28] in module InstructionCache is either unconnected or has no load
  402. WARNING: [Synth 8-7129] Port io_cpu_prefetch_pc[27] in module InstructionCache is either unconnected or has no load
  403. WARNING: [Synth 8-7129] Port io_cpu_prefetch_pc[26] in module InstructionCache is either unconnected or has no load
  404. WARNING: [Synth 8-7129] Port io_cpu_prefetch_pc[25] in module InstructionCache is either unconnected or has no load
  405. WARNING: [Synth 8-7129] Port io_cpu_prefetch_pc[24] in module InstructionCache is either unconnected or has no load
  406. WARNING: [Synth 8-7129] Port io_cpu_prefetch_pc[23] in module InstructionCache is either unconnected or has no load
  407. INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
  408. ---------------------------------------------------------------------------------
  409. Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2600.406 ; gain = 0.000 ; free physical = 1283 ; free virtual = 11576
  410. ---------------------------------------------------------------------------------
  411. ---------------------------------------------------------------------------------
  412. Start Handling Custom Attributes
  413. ---------------------------------------------------------------------------------
  414. ---------------------------------------------------------------------------------
  415. Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 2600.406 ; gain = 0.000 ; free physical = 1281 ; free virtual = 11574
  416. ---------------------------------------------------------------------------------
  417. ---------------------------------------------------------------------------------
  418. Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 2600.406 ; gain = 0.000 ; free physical = 1281 ; free virtual = 11574
  419. ---------------------------------------------------------------------------------
  420. Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2600.406 ; gain = 0.000 ; free physical = 1273 ; free virtual = 11566
  421. INFO: [Netlist 29-17] Analyzing 9 Unisim elements for replacement
  422. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
  423. INFO: [Project 1-570] Preparing netlist for logic optimization
  424.  
  425. Processing XDC Constraints
  426. Initializing timing engine
  427. Parsing XDC File [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc]
  428. WARNING: [Vivado 12-1023] No nets matched for command 'get_nets -hierarchical -filter {mr_ff == TRUE}'. [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc:28]
  429. Finished Parsing XDC File [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc]
  430. INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fairwaves_xtrx_propImpl.xdc].
  431. Resolution: To avoid this warning, move constraints listed in [.Xil/fairwaves_xtrx_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
  432. INFO: [Timing 38-2] Deriving generated clocks
  433. Completed Processing XDC Constraints
  434.  
  435. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2664.258 ; gain = 0.000 ; free physical = 1151 ; free virtual = 11465
  436. INFO: [Project 1-111] Unisim Transformation Summary:
  437. A total of 8 instances were transformed.
  438. FD => FDRE: 8 instances
  439.  
  440. Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2664.258 ; gain = 0.000 ; free physical = 1151 ; free virtual = 11465
  441. ---------------------------------------------------------------------------------
  442. Finished Constraint Validation : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2664.258 ; gain = 63.852 ; free physical = 1202 ; free virtual = 11515
  443. ---------------------------------------------------------------------------------
  444. ---------------------------------------------------------------------------------
  445. Start Loading Part and Timing Information
  446. ---------------------------------------------------------------------------------
  447. Loading part: xc7a50tcpg236-2
  448. ---------------------------------------------------------------------------------
  449. Finished Loading Part and Timing Information : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2664.258 ; gain = 63.852 ; free physical = 1202 ; free virtual = 11515
  450. ---------------------------------------------------------------------------------
  451. ---------------------------------------------------------------------------------
  452. Start Applying 'set_property' XDC Constraints
  453. ---------------------------------------------------------------------------------
  454. ---------------------------------------------------------------------------------
  455. Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2664.258 ; gain = 63.852 ; free physical = 1204 ; free virtual = 11515
  456. ---------------------------------------------------------------------------------
  457. WARNING: [Synth 8-3936] Found unconnected internal register 'memory_to_writeBack_INSTRUCTION_reg' and it is trimmed from '32' to '30' bits. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:2725]
  458. WARNING: [Synth 8-3936] Found unconnected internal register 'execute_to_memory_INSTRUCTION_reg' and it is trimmed from '32' to '30' bits. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:2530]
  459. WARNING: [Synth 8-3936] Found unconnected internal register 'storage_2_dat1_reg' and it is trimmed from '10' to '8' bits. [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1857]
  460. WARNING: [Synth 8-3936] Found unconnected internal register 'storage_1_dat1_reg' and it is trimmed from '10' to '8' bits. [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:1836]
  461. ---------------------------------------------------------------------------------
  462. Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 2664.258 ; gain = 63.852 ; free physical = 1217 ; free virtual = 11531
  463. ---------------------------------------------------------------------------------
  464. ---------------------------------------------------------------------------------
  465. Start RTL Component Statistics
  466. ---------------------------------------------------------------------------------
  467. Detailed RTL Component Info :
  468. +---Adders :
  469. 2 Input 64 Bit Adders := 1
  470. 3 Input 52 Bit Adders := 1
  471. 2 Input 33 Bit Adders := 1
  472. 3 Input 33 Bit Adders := 1
  473. 2 Input 32 Bit Adders := 6
  474. 3 Input 32 Bit Adders := 1
  475. 2 Input 8 Bit Adders := 2
  476. 2 Input 6 Bit Adders := 1
  477. 2 Input 5 Bit Adders := 3
  478. 2 Input 4 Bit Adders := 10
  479. 2 Input 3 Bit Adders := 4
  480. 2 Input 1 Bit Adders := 1
  481. +---XORs :
  482. 2 Input 32 Bit XORs := 1
  483. 2 Input 1 Bit XORs := 2
  484. +---Registers :
  485. 65 Bit Registers := 1
  486. 52 Bit Registers := 1
  487. 34 Bit Registers := 1
  488. 33 Bit Registers := 1
  489. 32 Bit Registers := 46
  490. 30 Bit Registers := 3
  491. 22 Bit Registers := 2
  492. 11 Bit Registers := 1
  493. 10 Bit Registers := 1
  494. 8 Bit Registers := 9
  495. 6 Bit Registers := 2
  496. 5 Bit Registers := 4
  497. 4 Bit Registers := 13
  498. 3 Bit Registers := 7
  499. 2 Bit Registers := 19
  500. 1 Bit Registers := 144
  501. +---RAMs :
  502. 64K Bit (2048 X 32 bit) RAMs := 1
  503. 32K Bit (1024 X 32 bit) RAMs := 1
  504. 8K Bit (1024 X 8 bit) RAMs := 4
  505. 2K Bit (128 X 22 bit) RAMs := 2
  506. 1024 Bit (32 X 32 bit) RAMs := 1
  507. 160 Bit (16 X 10 bit) RAMs := 3
  508. +---ROMs :
  509. ROMs := 1
  510. +---Muxes :
  511. 2 Input 33 Bit Muxes := 3
  512. 2 Input 32 Bit Muxes := 85
  513. 3 Input 32 Bit Muxes := 3
  514. 4 Input 32 Bit Muxes := 4
  515. 2 Input 30 Bit Muxes := 1
  516. 2 Input 25 Bit Muxes := 1
  517. 2 Input 14 Bit Muxes := 2
  518. 2 Input 10 Bit Muxes := 1
  519. 4 Input 8 Bit Muxes := 1
  520. 2 Input 8 Bit Muxes := 4
  521. 2 Input 7 Bit Muxes := 2
  522. 2 Input 5 Bit Muxes := 3
  523. 4 Input 4 Bit Muxes := 3
  524. 2 Input 4 Bit Muxes := 8
  525. 5 Input 4 Bit Muxes := 1
  526. 6 Input 4 Bit Muxes := 1
  527. 3 Input 4 Bit Muxes := 1
  528. 2 Input 3 Bit Muxes := 7
  529. 3 Input 3 Bit Muxes := 1
  530. 2 Input 2 Bit Muxes := 9
  531. 2 Input 1 Bit Muxes := 138
  532. 3 Input 1 Bit Muxes := 2
  533. 4 Input 1 Bit Muxes := 2
  534. ---------------------------------------------------------------------------------
  535. Finished RTL Component Statistics
  536. ---------------------------------------------------------------------------------
  537. ---------------------------------------------------------------------------------
  538. Start Part Resource Summary
  539. ---------------------------------------------------------------------------------
  540. Part Resources:
  541. DSPs: 120 (col length:60)
  542. BRAMs: 150 (col length: RAMB18 60 RAMB36 30)
  543. ---------------------------------------------------------------------------------
  544. Finished Part Resource Summary
  545. ---------------------------------------------------------------------------------
  546. ---------------------------------------------------------------------------------
  547. Start Cross Boundary and Area Optimization
  548. ---------------------------------------------------------------------------------
  549. WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
  550. WARNING: [Synth 8-3936] Found unconnected internal register 'memory_to_writeBack_MUL_HH_reg' and it is trimmed from '34' to '32' bits. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:2500]
  551. WARNING: [Synth 8-3936] Found unconnected internal register 'execute_to_memory_MUL_HH_reg' and it is trimmed from '34' to '32' bits. [/home/mikek/Documents/Cyclone_5/Litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:2444]
  552. DSP Report: Generating DSP memory_to_writeBack_MUL_HH_reg, operation Mode is: (A*B)'.
  553. DSP Report: register memory_to_writeBack_MUL_HH_reg is absorbed into DSP memory_to_writeBack_MUL_HH_reg.
  554. DSP Report: register execute_to_memory_MUL_HH_reg is absorbed into DSP memory_to_writeBack_MUL_HH_reg.
  555. DSP Report: operator execute_MUL_HH is absorbed into DSP memory_to_writeBack_MUL_HH_reg.
  556. DSP Report: Generating DSP execute_to_memory_MUL_LH_reg, operation Mode is: (A*B)'.
  557. DSP Report: register execute_to_memory_MUL_LH_reg is absorbed into DSP execute_to_memory_MUL_LH_reg.
  558. DSP Report: operator execute_MUL_LH is absorbed into DSP execute_to_memory_MUL_LH_reg.
  559. DSP Report: Generating DSP execute_to_memory_MUL_HL_reg, operation Mode is: (A*B)'.
  560. DSP Report: register execute_to_memory_MUL_HL_reg is absorbed into DSP execute_to_memory_MUL_HL_reg.
  561. DSP Report: operator execute_MUL_HL is absorbed into DSP execute_to_memory_MUL_HL_reg.
  562. DSP Report: Generating DSP execute_to_memory_MUL_LL_reg, operation Mode is: (A*B)'.
  563. DSP Report: register execute_to_memory_MUL_LL_reg is absorbed into DSP execute_to_memory_MUL_LL_reg.
  564. DSP Report: operator execute_MUL_LL is absorbed into DSP execute_to_memory_MUL_LL_reg.
  565. INFO: [Synth 8-3971] The signal "VexRiscv/RegFilePlugin_regFile_reg" was recognized as a true dual port RAM template.
  566. RAM Pipeline Warning: Read Address Register Found For RAM mem_1_reg. We will not be able to pipeline it. This may degrade performance.
  567. RAM Pipeline Warning: Read Address Register Found For RAM mem_1_reg. We will not be able to pipeline it. This may degrade performance.
  568. RAM Pipeline Warning: Read Address Register Found For RAM mem_1_reg. We will not be able to pipeline it. This may degrade performance.
  569. WARNING: [Synth 8-3332] Sequential element (FD) is unused and will be removed from module fairwaves_xtrx.
  570. WARNING: [Synth 8-3332] Sequential element (FD_1) is unused and will be removed from module fairwaves_xtrx.
  571. WARNING: [Synth 8-3332] Sequential element (FD_2) is unused and will be removed from module fairwaves_xtrx.
  572. WARNING: [Synth 8-3332] Sequential element (FD_3) is unused and will be removed from module fairwaves_xtrx.
  573. WARNING: [Synth 8-3332] Sequential element (FD_4) is unused and will be removed from module fairwaves_xtrx.
  574. WARNING: [Synth 8-3332] Sequential element (FD_5) is unused and will be removed from module fairwaves_xtrx.
  575. WARNING: [Synth 8-3332] Sequential element (FD_6) is unused and will be removed from module fairwaves_xtrx.
  576. WARNING: [Synth 8-3332] Sequential element (FD_7) is unused and will be removed from module fairwaves_xtrx.
  577. ---------------------------------------------------------------------------------
  578. Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:57 ; elapsed = 00:00:58 . Memory (MB): peak = 2664.258 ; gain = 63.852 ; free physical = 1151 ; free virtual = 11483
  579. ---------------------------------------------------------------------------------
  580. ---------------------------------------------------------------------------------
  581. Start ROM, RAM, DSP, Shift Register and Retiming Reporting
  582. ---------------------------------------------------------------------------------
  583.  
  584. ROM: Preliminary Mapping Report
  585. +---------------+--------------+---------------+----------------+
  586. |Module Name | RTL Object | Depth x Width | Implemented As |
  587. +---------------+--------------+---------------+----------------+
  588. |fairwaves_xtrx | mem_2 | 64x8 | LUT |
  589. |fairwaves_xtrx | p_0_out | 64x8 | LUT |
  590. |fairwaves_xtrx | mem_dat0_reg | 8192x32 | Block RAM |
  591. +---------------+--------------+---------------+----------------+
  592.  
  593.  
  594. Block RAM: Preliminary Mapping Report (see note below)
  595. +--------------------------------+-------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
  596. |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
  597. +--------------------------------+-------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
  598. |VexRiscv/IBusCachedPlugin_cache | banks_0_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 |
  599. |VexRiscv/IBusCachedPlugin_cache | ways_0_tags_reg | 128 x 22(READ_FIRST) | W | | 128 x 22(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
  600. |VexRiscv/dataCache_1 | ways_0_tags_reg | 128 x 22(READ_FIRST) | W | | 128 x 22(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
  601. |VexRiscv/dataCache_1 | ways_0_data_symbol0_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
  602. |VexRiscv/dataCache_1 | ways_0_data_symbol1_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
  603. |VexRiscv/dataCache_1 | ways_0_data_symbol2_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
  604. |VexRiscv/dataCache_1 | ways_0_data_symbol3_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
  605. |fairwaves_xtrx | mem_1_reg | 2 K x 32(WRITE_FIRST) | W | R | | | | Port A | 0 | 2 |
  606. +--------------------------------+-------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
  607.  
  608. Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once.
  609.  
  610. Distributed RAM: Preliminary Mapping Report (see note below)
  611. +---------------+---------------+-----------+----------------------+-------------+
  612. |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
  613. +---------------+---------------+-----------+----------------------+-------------+
  614. |fairwaves_xtrx | storage_1_reg | Implied | 16 x 10 | RAM32M x 2 |
  615. |fairwaves_xtrx | storage_reg | Implied | 16 x 8 | RAM32M x 2 |
  616. |fairwaves_xtrx | storage_2_reg | Implied | 16 x 10 | RAM32M x 2 |
  617. +---------------+---------------+-----------+----------------------+-------------+
  618.  
  619. Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
  620.  
  621. DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)
  622. +------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
  623. |Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
  624. +------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
  625. |VexRiscv | (A*B)' | 17 | 17 | - | - | 34 | 0 | 0 | - | - | - | 1 | 1 |
  626. |VexRiscv | (A*B)' | 17 | 17 | - | - | 34 | 0 | 0 | - | - | - | 1 | 0 |
  627. |VexRiscv | (A*B)' | 17 | 17 | - | - | 34 | 0 | 0 | - | - | - | 1 | 0 |
  628. |VexRiscv | (A*B)' | 16 | 16 | - | - | 32 | 0 | 0 | - | - | - | 1 | 0 |
  629. +------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
  630.  
  631. Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
  632. ---------------------------------------------------------------------------------
  633. Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
  634. ---------------------------------------------------------------------------------
  635. ---------------------------------------------------------------------------------
  636. Start Applying XDC Timing Constraints
  637. ---------------------------------------------------------------------------------
  638. ---------------------------------------------------------------------------------
  639. Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:05 ; elapsed = 00:01:06 . Memory (MB): peak = 2664.258 ; gain = 63.852 ; free physical = 1000 ; free virtual = 11336
  640. ---------------------------------------------------------------------------------
  641. ---------------------------------------------------------------------------------
  642. Start Timing Optimization
  643. ---------------------------------------------------------------------------------
  644. ---------------------------------------------------------------------------------
  645. Finished Timing Optimization : Time (s): cpu = 00:01:08 ; elapsed = 00:01:10 . Memory (MB): peak = 2664.258 ; gain = 63.852 ; free physical = 960 ; free virtual = 11300
  646. ---------------------------------------------------------------------------------
  647. ---------------------------------------------------------------------------------
  648. Start ROM, RAM, DSP, Shift Register and Retiming Reporting
  649. ---------------------------------------------------------------------------------
  650.  
  651. Block RAM: Final Mapping Report
  652. +--------------------------------+-------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
  653. |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
  654. +--------------------------------+-------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
  655. |VexRiscv/IBusCachedPlugin_cache | banks_0_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 |
  656. |VexRiscv/IBusCachedPlugin_cache | ways_0_tags_reg | 128 x 22(READ_FIRST) | W | | 128 x 22(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
  657. |VexRiscv/dataCache_1 | ways_0_tags_reg | 128 x 22(READ_FIRST) | W | | 128 x 22(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
  658. |VexRiscv/dataCache_1 | ways_0_data_symbol0_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
  659. |VexRiscv/dataCache_1 | ways_0_data_symbol1_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
  660. |VexRiscv/dataCache_1 | ways_0_data_symbol2_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
  661. |VexRiscv/dataCache_1 | ways_0_data_symbol3_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
  662. |fairwaves_xtrx | mem_1_reg | 2 K x 32(WRITE_FIRST) | W | R | | | | Port A | 0 | 2 |
  663. +--------------------------------+-------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
  664.  
  665.  
  666. Distributed RAM: Final Mapping Report
  667. +---------------+---------------+-----------+----------------------+-------------+
  668. |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
  669. +---------------+---------------+-----------+----------------------+-------------+
  670. |fairwaves_xtrx | storage_1_reg | Implied | 16 x 10 | RAM32M x 2 |
  671. |fairwaves_xtrx | storage_reg | Implied | 16 x 8 | RAM32M x 2 |
  672. |fairwaves_xtrx | storage_2_reg | Implied | 16 x 10 | RAM32M x 2 |
  673. +---------------+---------------+-----------+----------------------+-------------+
  674.  
  675. ---------------------------------------------------------------------------------
  676. Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
  677. ---------------------------------------------------------------------------------
  678. ---------------------------------------------------------------------------------
  679. Start Technology Mapping
  680. ---------------------------------------------------------------------------------
  681. INFO: [Synth 8-7052] The timing for the instance VexRiscv/IBusCachedPlugin_cache/banks_0_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  682. INFO: [Synth 8-7052] The timing for the instance VexRiscv/IBusCachedPlugin_cache/ways_0_tags_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  683. INFO: [Synth 8-7052] The timing for the instance VexRiscv/dataCache_1/ways_0_tags_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  684. INFO: [Synth 8-7052] The timing for the instance VexRiscv/RegFilePlugin_regFile_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  685. INFO: [Synth 8-7052] The timing for the instance VexRiscv/RegFilePlugin_regFile_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  686. INFO: [Synth 8-7052] The timing for the instance mem_1_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  687. INFO: [Synth 8-7052] The timing for the instance mem_1_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  688. INFO: [Synth 8-7052] The timing for the instance mem_dat0_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  689. INFO: [Synth 8-7052] The timing for the instance mem_dat0_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  690. INFO: [Synth 8-7052] The timing for the instance mem_dat0_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  691. INFO: [Synth 8-7052] The timing for the instance mem_dat0_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  692. INFO: [Synth 8-7052] The timing for the instance mem_dat0_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  693. INFO: [Synth 8-7052] The timing for the instance mem_dat0_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  694. INFO: [Synth 8-7052] The timing for the instance mem_dat0_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  695. INFO: [Synth 8-7052] The timing for the instance mem_dat0_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  696. ---------------------------------------------------------------------------------
  697. Finished Technology Mapping : Time (s): cpu = 00:01:11 ; elapsed = 00:01:13 . Memory (MB): peak = 2664.258 ; gain = 63.852 ; free physical = 953 ; free virtual = 11291
  698. ---------------------------------------------------------------------------------
  699. ---------------------------------------------------------------------------------
  700. Start IO Insertion
  701. ---------------------------------------------------------------------------------
  702. ---------------------------------------------------------------------------------
  703. Start Flattening Before IO Insertion
  704. ---------------------------------------------------------------------------------
  705. ---------------------------------------------------------------------------------
  706. Finished Flattening Before IO Insertion
  707. ---------------------------------------------------------------------------------
  708. ---------------------------------------------------------------------------------
  709. Start Final Netlist Cleanup
  710. ---------------------------------------------------------------------------------
  711. ---------------------------------------------------------------------------------
  712. Finished Final Netlist Cleanup
  713. ---------------------------------------------------------------------------------
  714. ---------------------------------------------------------------------------------
  715. Finished IO Insertion : Time (s): cpu = 00:01:15 ; elapsed = 00:01:17 . Memory (MB): peak = 2664.258 ; gain = 63.852 ; free physical = 918 ; free virtual = 11256
  716. ---------------------------------------------------------------------------------
  717. ---------------------------------------------------------------------------------
  718. Start Renaming Generated Instances
  719. ---------------------------------------------------------------------------------
  720. ---------------------------------------------------------------------------------
  721. Finished Renaming Generated Instances : Time (s): cpu = 00:01:15 ; elapsed = 00:01:17 . Memory (MB): peak = 2664.258 ; gain = 63.852 ; free physical = 918 ; free virtual = 11256
  722. ---------------------------------------------------------------------------------
  723. ---------------------------------------------------------------------------------
  724. Start Rebuilding User Hierarchy
  725. ---------------------------------------------------------------------------------
  726. ---------------------------------------------------------------------------------
  727. Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:16 ; elapsed = 00:01:18 . Memory (MB): peak = 2664.258 ; gain = 63.852 ; free physical = 915 ; free virtual = 11255
  728. ---------------------------------------------------------------------------------
  729. ---------------------------------------------------------------------------------
  730. Start Renaming Generated Ports
  731. ---------------------------------------------------------------------------------
  732. ---------------------------------------------------------------------------------
  733. Finished Renaming Generated Ports : Time (s): cpu = 00:01:16 ; elapsed = 00:01:18 . Memory (MB): peak = 2664.258 ; gain = 63.852 ; free physical = 915 ; free virtual = 11255
  734. ---------------------------------------------------------------------------------
  735. ---------------------------------------------------------------------------------
  736. Start Handling Custom Attributes
  737. ---------------------------------------------------------------------------------
  738. ---------------------------------------------------------------------------------
  739. Finished Handling Custom Attributes : Time (s): cpu = 00:01:16 ; elapsed = 00:01:18 . Memory (MB): peak = 2664.258 ; gain = 63.852 ; free physical = 915 ; free virtual = 11255
  740. ---------------------------------------------------------------------------------
  741. ---------------------------------------------------------------------------------
  742. Start Renaming Generated Nets
  743. ---------------------------------------------------------------------------------
  744. ---------------------------------------------------------------------------------
  745. Finished Renaming Generated Nets : Time (s): cpu = 00:01:16 ; elapsed = 00:01:18 . Memory (MB): peak = 2664.258 ; gain = 63.852 ; free physical = 915 ; free virtual = 11255
  746. ---------------------------------------------------------------------------------
  747. ---------------------------------------------------------------------------------
  748. Start Writing Synthesis Report
  749. ---------------------------------------------------------------------------------
  750.  
  751. Report BlackBoxes:
  752. +-+--------------+----------+
  753. | |BlackBox name |Instances |
  754. +-+--------------+----------+
  755. +-+--------------+----------+
  756.  
  757. Report Cell Usage:
  758. +------+----------+------+
  759. | |Cell |Count |
  760. +------+----------+------+
  761. |1 |BUFG | 1|
  762. |2 |CARRY4 | 120|
  763. |3 |DSP48E1 | 4|
  764. |5 |LUT1 | 121|
  765. |6 |LUT2 | 289|
  766. |7 |LUT3 | 324|
  767. |8 |LUT4 | 438|
  768. |9 |LUT5 | 444|
  769. |10 |LUT6 | 879|
  770. |11 |PLLE2_ADV | 1|
  771. |12 |RAM32M | 3|
  772. |13 |RAM32X1D | 6|
  773. |14 |RAMB18E1 | 8|
  774. |16 |RAMB36E1 | 11|
  775. |26 |FDPE | 2|
  776. |27 |FDRE | 1620|
  777. |28 |FDSE | 70|
  778. |29 |IBUF | 1|
  779. |30 |OBUF | 1|
  780. +------+----------+------+
  781. ---------------------------------------------------------------------------------
  782. Finished Writing Synthesis Report : Time (s): cpu = 00:01:16 ; elapsed = 00:01:18 . Memory (MB): peak = 2664.258 ; gain = 63.852 ; free physical = 915 ; free virtual = 11255
  783. ---------------------------------------------------------------------------------
  784. Synthesis finished with 0 errors, 0 critical warnings and 201 warnings.
  785. Synthesis Optimization Runtime : Time (s): cpu = 00:01:13 ; elapsed = 00:01:15 . Memory (MB): peak = 2664.258 ; gain = 0.000 ; free physical = 977 ; free virtual = 11317
  786. Synthesis Optimization Complete : Time (s): cpu = 00:01:16 ; elapsed = 00:01:18 . Memory (MB): peak = 2664.258 ; gain = 63.852 ; free physical = 977 ; free virtual = 11317
  787. INFO: [Project 1-571] Translating synthesized netlist
  788. Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2664.258 ; gain = 0.000 ; free physical = 1067 ; free virtual = 11407
  789. INFO: [Netlist 29-17] Analyzing 153 Unisim elements for replacement
  790. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
  791. INFO: [Project 1-570] Preparing netlist for logic optimization
  792. Parsing XDC File [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc]
  793. WARNING: [Vivado 12-1023] No nets matched for command 'get_nets -hierarchical -filter {mr_ff == TRUE}'. [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc:28]
  794. Finished Parsing XDC File [/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc]
  795. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  796. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2664.258 ; gain = 0.000 ; free physical = 1030 ; free virtual = 11369
  797. INFO: [Project 1-111] Unisim Transformation Summary:
  798. A total of 9 instances were transformed.
  799. RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 3 instances
  800. RAM32X1D => RAM32X1D (RAMD32(x2)): 6 instances
  801.  
  802. Synth Design complete, checksum: 9ec779f8
  803. INFO: [Common 17-83] Releasing license: Synthesis
  804. 58 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered.
  805. synth_design completed successfully
  806. synth_design: Time (s): cpu = 00:01:28 ; elapsed = 00:01:26 . Memory (MB): peak = 2664.258 ; gain = 64.031 ; free physical = 1271 ; free virtual = 11611
  807. # report_timing_summary -file fairwaves_xtrx_timing_synth.rpt
  808. INFO: [Timing 38-35] Done setting XDC timing constraints.
  809. INFO: [Timing 38-2] Deriving generated clocks
  810. INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
  811. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
  812. # report_utilization -hierarchical -file fairwaves_xtrx_utilization_hierarchical_synth.rpt
  813. # report_utilization -file fairwaves_xtrx_utilization_synth.rpt
  814. # opt_design -directive default
  815. Command: opt_design -directive default
  816. INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: default
  817. Attempting to get a license for feature 'Implementation' and/or device 'xc7a50t'
  818. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a50t'
  819. Running DRC as a precondition to command opt_design
  820.  
  821. Starting DRC Task
  822. INFO: [DRC 23-27] Running DRC with 8 threads
  823. INFO: [Project 1-461] DRC finished with 0 Errors
  824. INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
  825.  
  826. Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.96 . Memory (MB): peak = 2878.957 ; gain = 89.812 ; free physical = 978 ; free virtual = 11330
  827.  
  828. Starting Cache Timing Information Task
  829. Ending Cache Timing Information Task | Checksum: 24dee3e9b
  830.  
  831. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2878.957 ; gain = 0.000 ; free physical = 978 ; free virtual = 11330
  832.  
  833. Starting Logic Optimization Task
  834.  
  835. Phase 1 Retarget
  836. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/CsrPlugin_mtvec_base[1]_i_1 into driver instance VexRiscv/CsrPlugin_mtvec_base[1]_i_2, which resulted in an inversion of 5 pins
  837. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[10]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_46, which resulted in an inversion of 4 pins
  838. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[14]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_45, which resulted in an inversion of 4 pins
  839. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[16]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_64, which resulted in an inversion of 4 pins
  840. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[17]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_63, which resulted in an inversion of 4 pins
  841. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[18]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_62, which resulted in an inversion of 4 pins
  842. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[19]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_61, which resulted in an inversion of 4 pins
  843. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[1]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_48, which resulted in an inversion of 4 pins
  844. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[20]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_60, which resulted in an inversion of 4 pins
  845. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[21]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_59, which resulted in an inversion of 4 pins
  846. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[22]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_58, which resulted in an inversion of 4 pins
  847. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[23]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_57, which resulted in an inversion of 4 pins
  848. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[24]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_56, which resulted in an inversion of 4 pins
  849. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[25]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_55, which resulted in an inversion of 4 pins
  850. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[26]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_54, which resulted in an inversion of 4 pins
  851. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[27]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_53, which resulted in an inversion of 4 pins
  852. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[28]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_52, which resulted in an inversion of 4 pins
  853. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[29]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_51, which resulted in an inversion of 4 pins
  854. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[30]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_50, which resulted in an inversion of 4 pins
  855. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[31]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_49, which resulted in an inversion of 4 pins
  856. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[9]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_47, which resulted in an inversion of 4 pins
  857. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/ways_0_data_symbol0_reg_i_2 into driver instance VexRiscv/dataCache_1/ways_0_data_symbol0_reg_i_18, which resulted in an inversion of 9 pins
  858. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  859. INFO: [Opt 31-49] Retargeted 0 cell(s).
  860. Phase 1 Retarget | Checksum: 204bf6aaa
  861.  
  862. Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.24 . Memory (MB): peak = 3026.941 ; gain = 0.000 ; free physical = 780 ; free virtual = 11130
  863. INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 24 cells
  864. INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
  865.  
  866. Phase 2 Constant propagation
  867. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  868. Phase 2 Constant propagation | Checksum: 205ce4887
  869.  
  870. Time (s): cpu = 00:00:00.50 ; elapsed = 00:00:00.30 . Memory (MB): peak = 3026.941 ; gain = 0.000 ; free physical = 780 ; free virtual = 11130
  871. INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 2 cells
  872.  
  873. Phase 3 Sweep
  874. Phase 3 Sweep | Checksum: 1ecbf0c76
  875.  
  876. Time (s): cpu = 00:00:00.60 ; elapsed = 00:00:00.39 . Memory (MB): peak = 3026.941 ; gain = 0.000 ; free physical = 779 ; free virtual = 11130
  877. INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 3 cells
  878. INFO: [Opt 31-1021] In phase Sweep, 2 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
  879.  
  880. Phase 4 BUFG optimization
  881. Phase 4 BUFG optimization | Checksum: 1ecbf0c76
  882.  
  883. Time (s): cpu = 00:00:00.66 ; elapsed = 00:00:00.46 . Memory (MB): peak = 3026.941 ; gain = 0.000 ; free physical = 779 ; free virtual = 11130
  884. INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
  885. INFO: [Opt 31-1021] In phase BUFG optimization, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
  886.  
  887. Phase 5 Shift Register Optimization
  888. INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
  889. Phase 5 Shift Register Optimization | Checksum: 1ecbf0c76
  890.  
  891. Time (s): cpu = 00:00:00.67 ; elapsed = 00:00:00.47 . Memory (MB): peak = 3026.941 ; gain = 0.000 ; free physical = 779 ; free virtual = 11130
  892. INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
  893.  
  894. Phase 6 Post Processing Netlist
  895. Phase 6 Post Processing Netlist | Checksum: 1ecbf0c76
  896.  
  897. Time (s): cpu = 00:00:00.69 ; elapsed = 00:00:00.48 . Memory (MB): peak = 3026.941 ; gain = 0.000 ; free physical = 779 ; free virtual = 11130
  898. INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
  899. Opt_design Change Summary
  900. =========================
  901.  
  902.  
  903. -------------------------------------------------------------------------------------------------------------------------
  904. | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
  905. -------------------------------------------------------------------------------------------------------------------------
  906. | Retarget | 0 | 24 | 1 |
  907. | Constant propagation | 0 | 2 | 0 |
  908. | Sweep | 0 | 3 | 2 |
  909. | BUFG optimization | 0 | 0 | 1 |
  910. | Shift Register Optimization | 0 | 0 | 0 |
  911. | Post Processing Netlist | 0 | 0 | 0 |
  912. -------------------------------------------------------------------------------------------------------------------------
  913.  
  914.  
  915.  
  916. Starting Connectivity Check Task
  917.  
  918. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3026.941 ; gain = 0.000 ; free physical = 778 ; free virtual = 11130
  919. Ending Logic Optimization Task | Checksum: 1c0ed7cdd
  920.  
  921. Time (s): cpu = 00:00:00.82 ; elapsed = 00:00:00.60 . Memory (MB): peak = 3026.941 ; gain = 0.000 ; free physical = 778 ; free virtual = 11130
  922.  
  923. Starting Power Optimization Task
  924. INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
  925. INFO: [Timing 38-35] Done setting XDC timing constraints.
  926. Running Vector-less Activity Propagation...
  927.  
  928. Finished Running Vector-less Activity Propagation
  929. INFO: [Pwropt 34-9] Applying IDT optimizations ...
  930. INFO: [Pwropt 34-10] Applying ODC optimizations ...
  931.  
  932.  
  933. Starting PowerOpt Patch Enables Task
  934. INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 19 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
  935. INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
  936. Number of BRAM Ports augmented: 5 newly gated: 1 Total Ports: 38
  937. Ending PowerOpt Patch Enables Task | Checksum: 19c8c7eb3
  938.  
  939. Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 931 ; free virtual = 11293
  940. Ending Power Optimization Task | Checksum: 19c8c7eb3
  941.  
  942. Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 3243.031 ; gain = 216.090 ; free physical = 937 ; free virtual = 11299
  943.  
  944. Starting Final Cleanup Task
  945. Ending Final Cleanup Task | Checksum: 19c8c7eb3
  946.  
  947. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 937 ; free virtual = 11299
  948.  
  949. Starting Netlist Obfuscation Task
  950. Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 937 ; free virtual = 11298
  951. Ending Netlist Obfuscation Task | Checksum: 18f409dd4
  952.  
  953. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 937 ; free virtual = 11298
  954. INFO: [Common 17-83] Releasing license: Implementation
  955. 47 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
  956. opt_design completed successfully
  957. opt_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 3243.031 ; gain = 453.887 ; free physical = 937 ; free virtual = 11298
  958. # place_design -directive default
  959. Command: place_design -directive default
  960. Attempting to get a license for feature 'Implementation' and/or device 'xc7a50t'
  961. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a50t'
  962. INFO: [Timing 38-35] Done setting XDC timing constraints.
  963. INFO: [DRC 23-27] Running DRC with 8 threads
  964. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
  965. INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
  966. Running DRC as a precondition to command place_design
  967. INFO: [DRC 23-27] Running DRC with 8 threads
  968. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
  969. INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
  970.  
  971. Starting Placer Task
  972. INFO: [Place 46-5] The placer was invoked with the 'default' directive.
  973. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
  974.  
  975. Phase 1 Placer Initialization
  976.  
  977. Phase 1.1 Placer Initialization Netlist Sorting
  978. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 916 ; free virtual = 11278
  979. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fb162e28
  980.  
  981. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.06 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 915 ; free virtual = 11278
  982. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 915 ; free virtual = 11278
  983.  
  984. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
  985. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 101efcae6
  986.  
  987. Time (s): cpu = 00:00:00.82 ; elapsed = 00:00:00.53 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 924 ; free virtual = 11290
  988.  
  989. Phase 1.3 Build Placer Netlist Model
  990. Phase 1.3 Build Placer Netlist Model | Checksum: 12fd25bd8
  991.  
  992. Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 923 ; free virtual = 11290
  993.  
  994. Phase 1.4 Constrain Clocks/Macros
  995. Phase 1.4 Constrain Clocks/Macros | Checksum: 12fd25bd8
  996.  
  997. Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 923 ; free virtual = 11290
  998. Phase 1 Placer Initialization | Checksum: 12fd25bd8
  999.  
  1000. Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 923 ; free virtual = 11290
  1001.  
  1002. Phase 2 Global Placement
  1003.  
  1004. Phase 2.1 Floorplanning
  1005. Phase 2.1 Floorplanning | Checksum: 1d94f4327
  1006.  
  1007. Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 917 ; free virtual = 11285
  1008.  
  1009. Phase 2.2 Update Timing before SLR Path Opt
  1010. Phase 2.2 Update Timing before SLR Path Opt | Checksum: 14d8584f1
  1011.  
  1012. Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 949 ; free virtual = 11317
  1013.  
  1014. Phase 2.3 Post-Processing in Floorplanning
  1015. Phase 2.3 Post-Processing in Floorplanning | Checksum: 14d8584f1
  1016.  
  1017. Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 949 ; free virtual = 11317
  1018.  
  1019. Phase 2.4 Global Placement Core
  1020.  
  1021. Phase 2.4.1 Physical Synthesis In Placer
  1022. INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 306 LUT instances to create LUTNM shape
  1023. INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
  1024. INFO: [Physopt 32-1138] End 1 Pass. Optimized 90 nets or LUTs. Breaked 0 LUT, combined 90 existing LUTs and moved 0 existing LUT
  1025. INFO: [Physopt 32-65] No nets found for high-fanout optimization.
  1026. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
  1027. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
  1028. INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
  1029. INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
  1030. INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
  1031. INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
  1032. INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
  1033. INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
  1034. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
  1035. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 935 ; free virtual = 11300
  1036.  
  1037. Summary of Physical Synthesis Optimizations
  1038. ============================================
  1039.  
  1040.  
  1041. -----------------------------------------------------------------------------------------------------------------------------------------------------------
  1042. | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
  1043. -----------------------------------------------------------------------------------------------------------------------------------------------------------
  1044. | LUT Combining | 0 | 90 | 90 | 0 | 1 | 00:00:00 |
  1045. | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
  1046. | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
  1047. | DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
  1048. | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
  1049. | Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
  1050. | BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
  1051. | URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
  1052. | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
  1053. | Total | 0 | 90 | 90 | 0 | 4 | 00:00:00 |
  1054. -----------------------------------------------------------------------------------------------------------------------------------------------------------
  1055.  
  1056.  
  1057. Phase 2.4.1 Physical Synthesis In Placer | Checksum: 16deeec3e
  1058.  
  1059. Time (s): cpu = 00:00:14 ; elapsed = 00:00:05 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 936 ; free virtual = 11299
  1060. Phase 2.4 Global Placement Core | Checksum: 1f489d388
  1061.  
  1062. Time (s): cpu = 00:00:15 ; elapsed = 00:00:05 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 936 ; free virtual = 11299
  1063. Phase 2 Global Placement | Checksum: 1f489d388
  1064.  
  1065. Time (s): cpu = 00:00:15 ; elapsed = 00:00:05 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 937 ; free virtual = 11300
  1066.  
  1067. Phase 3 Detail Placement
  1068.  
  1069. Phase 3.1 Commit Multi Column Macros
  1070. Phase 3.1 Commit Multi Column Macros | Checksum: 13096306a
  1071.  
  1072. Time (s): cpu = 00:00:16 ; elapsed = 00:00:06 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 937 ; free virtual = 11300
  1073.  
  1074. Phase 3.2 Commit Most Macros & LUTRAMs
  1075. Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1423f28a1
  1076.  
  1077. Time (s): cpu = 00:00:17 ; elapsed = 00:00:06 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 936 ; free virtual = 11299
  1078.  
  1079. Phase 3.3 Area Swap Optimization
  1080. Phase 3.3 Area Swap Optimization | Checksum: 188099576
  1081.  
  1082. Time (s): cpu = 00:00:17 ; elapsed = 00:00:06 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 936 ; free virtual = 11299
  1083.  
  1084. Phase 3.4 Pipeline Register Optimization
  1085. Phase 3.4 Pipeline Register Optimization | Checksum: 16c27dd58
  1086.  
  1087. Time (s): cpu = 00:00:17 ; elapsed = 00:00:06 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 936 ; free virtual = 11299
  1088.  
  1089. Phase 3.5 Small Shape Detail Placement
  1090. Phase 3.5 Small Shape Detail Placement | Checksum: 12b021017
  1091.  
  1092. Time (s): cpu = 00:00:19 ; elapsed = 00:00:07 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 927 ; free virtual = 11295
  1093.  
  1094. Phase 3.6 Re-assign LUT pins
  1095. Phase 3.6 Re-assign LUT pins | Checksum: 107a83e96
  1096.  
  1097. Time (s): cpu = 00:00:19 ; elapsed = 00:00:08 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 927 ; free virtual = 11295
  1098.  
  1099. Phase 3.7 Pipeline Register Optimization
  1100. Phase 3.7 Pipeline Register Optimization | Checksum: f3c1f674
  1101.  
  1102. Time (s): cpu = 00:00:19 ; elapsed = 00:00:08 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 927 ; free virtual = 11295
  1103. Phase 3 Detail Placement | Checksum: f3c1f674
  1104.  
  1105. Time (s): cpu = 00:00:19 ; elapsed = 00:00:08 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 927 ; free virtual = 11295
  1106.  
  1107. Phase 4 Post Placement Optimization and Clean-Up
  1108.  
  1109. Phase 4.1 Post Commit Optimization
  1110. INFO: [Timing 38-35] Done setting XDC timing constraints.
  1111.  
  1112. Phase 4.1.1 Post Placement Optimization
  1113. Post Placement Optimization Initialization | Checksum: 1a1d3c974
  1114.  
  1115. Phase 4.1.1.1 BUFG Insertion
  1116.  
  1117. Starting Physical Synthesis Task
  1118.  
  1119. Phase 1 Physical Synthesis Initialization
  1120. INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
  1121. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.750 | TNS=0.000 |
  1122. Phase 1 Physical Synthesis Initialization | Checksum: 1ef73af3d
  1123.  
  1124. Time (s): cpu = 00:00:00.58 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 924 ; free virtual = 11294
  1125. INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0.
  1126. Ending Physical Synthesis Task | Checksum: 1694dab4b
  1127.  
  1128. Time (s): cpu = 00:00:00.60 ; elapsed = 00:00:00.14 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 924 ; free virtual = 11294
  1129. Phase 4.1.1.1 BUFG Insertion | Checksum: 1a1d3c974
  1130.  
  1131. Time (s): cpu = 00:00:23 ; elapsed = 00:00:09 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 924 ; free virtual = 11294
  1132.  
  1133. Phase 4.1.1.2 Post Placement Timing Optimization
  1134. INFO: [Place 30-746] Post Placement Timing Summary WNS=0.750. For the most accurate timing information please run report_timing.
  1135. Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 163f42a00
  1136.  
  1137. Time (s): cpu = 00:00:23 ; elapsed = 00:00:09 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 924 ; free virtual = 11294
  1138.  
  1139. Time (s): cpu = 00:00:23 ; elapsed = 00:00:09 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 924 ; free virtual = 11294
  1140. Phase 4.1 Post Commit Optimization | Checksum: 163f42a00
  1141.  
  1142. Time (s): cpu = 00:00:23 ; elapsed = 00:00:09 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 924 ; free virtual = 11294
  1143.  
  1144. Phase 4.2 Post Placement Cleanup
  1145. Phase 4.2 Post Placement Cleanup | Checksum: 163f42a00
  1146.  
  1147. Time (s): cpu = 00:00:23 ; elapsed = 00:00:09 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 925 ; free virtual = 11295
  1148.  
  1149. Phase 4.3 Placer Reporting
  1150.  
  1151. Phase 4.3.1 Print Estimated Congestion
  1152. INFO: [Place 30-612] Post-Placement Estimated Congestion
  1153. ____________________________________________________
  1154. | | Global Congestion | Short Congestion |
  1155. | Direction | Region Size | Region Size |
  1156. |___________|___________________|___________________|
  1157. | North| 1x1| 2x2|
  1158. |___________|___________________|___________________|
  1159. | South| 1x1| 1x1|
  1160. |___________|___________________|___________________|
  1161. | East| 1x1| 1x1|
  1162. |___________|___________________|___________________|
  1163. | West| 1x1| 1x1|
  1164. |___________|___________________|___________________|
  1165.  
  1166. Phase 4.3.1 Print Estimated Congestion | Checksum: 163f42a00
  1167.  
  1168. Time (s): cpu = 00:00:23 ; elapsed = 00:00:09 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 925 ; free virtual = 11295
  1169. Phase 4.3 Placer Reporting | Checksum: 163f42a00
  1170.  
  1171. Time (s): cpu = 00:00:23 ; elapsed = 00:00:09 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 924 ; free virtual = 11294
  1172.  
  1173. Phase 4.4 Final Placement Cleanup
  1174. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 924 ; free virtual = 11294
  1175.  
  1176. Time (s): cpu = 00:00:23 ; elapsed = 00:00:09 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 924 ; free virtual = 11294
  1177. Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1cc16e359
  1178.  
  1179. Time (s): cpu = 00:00:23 ; elapsed = 00:00:09 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 924 ; free virtual = 11294
  1180. Ending Placer Task | Checksum: 13d45f4f8
  1181.  
  1182. Time (s): cpu = 00:00:23 ; elapsed = 00:00:09 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 924 ; free virtual = 11294
  1183. INFO: [Common 17-83] Releasing license: Implementation
  1184. 30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
  1185. place_design completed successfully
  1186. place_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:10 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 935 ; free virtual = 11304
  1187. # report_utilization -hierarchical -file fairwaves_xtrx_utilization_hierarchical_place.rpt
  1188. # report_utilization -file fairwaves_xtrx_utilization_place.rpt
  1189. # report_io -file fairwaves_xtrx_io.rpt
  1190. report_io: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.19 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 930 ; free virtual = 11299
  1191. # report_control_sets -verbose -file fairwaves_xtrx_control_sets.rpt
  1192. report_control_sets: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.15 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 933 ; free virtual = 11302
  1193. # report_clock_utilization -file fairwaves_xtrx_clock_utilization.rpt
  1194. # route_design -directive default
  1195. Command: route_design -directive default
  1196. Attempting to get a license for feature 'Implementation' and/or device 'xc7a50t'
  1197. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a50t'
  1198. Running DRC as a precondition to command route_design
  1199. INFO: [DRC 23-27] Running DRC with 8 threads
  1200. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
  1201. INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
  1202.  
  1203.  
  1204. Starting Routing Task
  1205. INFO: [Route 35-270] Using Router directive 'default'.
  1206. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
  1207.  
  1208. Phase 1 Build RT Design
  1209. Checksum: PlaceDB: 468a89e3 ConstDB: 0 ShapeSum: f6bb6b15 RouteDB: 0
  1210. Post Restoration Checksum: NetGraph: 9eb37d21 NumContArr: cc2b28b2 Constraints: 0 Timing: 0
  1211. Phase 1 Build RT Design | Checksum: 16adea5d3
  1212.  
  1213. Time (s): cpu = 00:00:20 ; elapsed = 00:00:17 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 764 ; free virtual = 11132
  1214.  
  1215. Phase 2 Router Initialization
  1216.  
  1217. Phase 2.1 Create Timer
  1218. Phase 2.1 Create Timer | Checksum: 16adea5d3
  1219.  
  1220. Time (s): cpu = 00:00:20 ; elapsed = 00:00:17 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 764 ; free virtual = 11133
  1221.  
  1222. Phase 2.2 Fix Topology Constraints
  1223. Phase 2.2 Fix Topology Constraints | Checksum: 16adea5d3
  1224.  
  1225. Time (s): cpu = 00:00:20 ; elapsed = 00:00:17 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 731 ; free virtual = 11100
  1226.  
  1227. Phase 2.3 Pre Route Cleanup
  1228. Phase 2.3 Pre Route Cleanup | Checksum: 16adea5d3
  1229.  
  1230. Time (s): cpu = 00:00:20 ; elapsed = 00:00:17 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 731 ; free virtual = 11100
  1231. Number of Nodes with overlaps = 0
  1232.  
  1233. Phase 2.4 Update Timing
  1234. Phase 2.4 Update Timing | Checksum: 20db4becb
  1235.  
  1236. Time (s): cpu = 00:00:24 ; elapsed = 00:00:19 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 683 ; free virtual = 11057
  1237. INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.824 | TNS=0.000 | WHS=-0.231 | THS=-83.127|
  1238.  
  1239.  
  1240. Router Utilization Summary
  1241. Global Vertical Routing Utilization = 0 %
  1242. Global Horizontal Routing Utilization = 0 %
  1243. Routable Net Status*
  1244. *Does not include unroutable nets such as driverless and loadless.
  1245. Run report_route_status for detailed report.
  1246. Number of Failed Nets = 3757
  1247. (Failed Nets is the sum of unrouted and partially routed nets)
  1248. Number of Unrouted Nets = 3757
  1249. Number of Partially Routed Nets = 0
  1250. Number of Node Overlaps = 0
  1251.  
  1252. Phase 2 Router Initialization | Checksum: 229d1739c
  1253.  
  1254. Time (s): cpu = 00:00:25 ; elapsed = 00:00:19 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 675 ; free virtual = 11049
  1255.  
  1256. Phase 3 Initial Routing
  1257.  
  1258. Phase 3.1 Global Routing
  1259. Phase 3.1 Global Routing | Checksum: 229d1739c
  1260.  
  1261. Time (s): cpu = 00:00:25 ; elapsed = 00:00:19 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 675 ; free virtual = 11049
  1262. Phase 3 Initial Routing | Checksum: 1a0fc617a
  1263.  
  1264. Time (s): cpu = 00:00:29 ; elapsed = 00:00:20 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 665 ; free virtual = 11038
  1265.  
  1266. Phase 4 Rip-up And Reroute
  1267.  
  1268. Phase 4.1 Global Iteration 0
  1269. Number of Nodes with overlaps = 654
  1270. Number of Nodes with overlaps = 132
  1271. Number of Nodes with overlaps = 36
  1272. Number of Nodes with overlaps = 13
  1273. Number of Nodes with overlaps = 5
  1274. Number of Nodes with overlaps = 4
  1275. Number of Nodes with overlaps = 1
  1276. Number of Nodes with overlaps = 0
  1277. INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.904 | TNS=0.000 | WHS=N/A | THS=N/A |
  1278.  
  1279. Phase 4.1 Global Iteration 0 | Checksum: 13eb918c0
  1280.  
  1281. Time (s): cpu = 00:00:37 ; elapsed = 00:00:25 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 722 ; free virtual = 11095
  1282. Phase 4 Rip-up And Reroute | Checksum: 13eb918c0
  1283.  
  1284. Time (s): cpu = 00:00:37 ; elapsed = 00:00:25 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 722 ; free virtual = 11096
  1285.  
  1286. Phase 5 Delay and Skew Optimization
  1287.  
  1288. Phase 5.1 Delay CleanUp
  1289. Phase 5.1 Delay CleanUp | Checksum: 13eb918c0
  1290.  
  1291. Time (s): cpu = 00:00:37 ; elapsed = 00:00:25 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 722 ; free virtual = 11096
  1292.  
  1293. Phase 5.2 Clock Skew Optimization
  1294. Phase 5.2 Clock Skew Optimization | Checksum: 13eb918c0
  1295.  
  1296. Time (s): cpu = 00:00:37 ; elapsed = 00:00:25 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 722 ; free virtual = 11096
  1297. Phase 5 Delay and Skew Optimization | Checksum: 13eb918c0
  1298.  
  1299. Time (s): cpu = 00:00:37 ; elapsed = 00:00:25 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 722 ; free virtual = 11096
  1300.  
  1301. Phase 6 Post Hold Fix
  1302.  
  1303. Phase 6.1 Hold Fix Iter
  1304.  
  1305. Phase 6.1.1 Update Timing
  1306. Phase 6.1.1 Update Timing | Checksum: 192342ab8
  1307.  
  1308. Time (s): cpu = 00:00:38 ; elapsed = 00:00:25 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 721 ; free virtual = 11095
  1309. INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.986 | TNS=0.000 | WHS=0.033 | THS=0.000 |
  1310.  
  1311. Phase 6.1 Hold Fix Iter | Checksum: 1203fd2b0
  1312.  
  1313. Time (s): cpu = 00:00:38 ; elapsed = 00:00:25 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 721 ; free virtual = 11095
  1314. Phase 6 Post Hold Fix | Checksum: 1203fd2b0
  1315.  
  1316. Time (s): cpu = 00:00:38 ; elapsed = 00:00:25 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 721 ; free virtual = 11095
  1317.  
  1318. Phase 7 Route finalize
  1319.  
  1320. Router Utilization Summary
  1321. Global Vertical Routing Utilization = 1.2977 %
  1322. Global Horizontal Routing Utilization = 1.75469 %
  1323. Routable Net Status*
  1324. *Does not include unroutable nets such as driverless and loadless.
  1325. Run report_route_status for detailed report.
  1326. Number of Failed Nets = 0
  1327. (Failed Nets is the sum of unrouted and partially routed nets)
  1328. Number of Unrouted Nets = 0
  1329. Number of Partially Routed Nets = 0
  1330. Number of Node Overlaps = 0
  1331.  
  1332. Phase 7 Route finalize | Checksum: 1e34ae569
  1333.  
  1334. Time (s): cpu = 00:00:38 ; elapsed = 00:00:25 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 721 ; free virtual = 11094
  1335.  
  1336. Phase 8 Verifying routed nets
  1337.  
  1338. Verification completed successfully
  1339. Phase 8 Verifying routed nets | Checksum: 1e34ae569
  1340.  
  1341. Time (s): cpu = 00:00:38 ; elapsed = 00:00:25 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 719 ; free virtual = 11093
  1342.  
  1343. Phase 9 Depositing Routes
  1344. Phase 9 Depositing Routes | Checksum: 1cd678062
  1345.  
  1346. Time (s): cpu = 00:00:38 ; elapsed = 00:00:26 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 720 ; free virtual = 11093
  1347.  
  1348. Phase 10 Post Router Timing
  1349. INFO: [Route 35-57] Estimated Timing Summary | WNS=0.986 | TNS=0.000 | WHS=0.033 | THS=0.000 |
  1350.  
  1351. INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
  1352. Phase 10 Post Router Timing | Checksum: 1cd678062
  1353.  
  1354. Time (s): cpu = 00:00:39 ; elapsed = 00:00:26 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 720 ; free virtual = 11093
  1355. INFO: [Route 35-16] Router Completed Successfully
  1356.  
  1357. Time (s): cpu = 00:00:39 ; elapsed = 00:00:26 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 756 ; free virtual = 11129
  1358.  
  1359. Routing Is Done.
  1360. INFO: [Common 17-83] Releasing license: Implementation
  1361. 13 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
  1362. route_design completed successfully
  1363. route_design: Time (s): cpu = 00:00:43 ; elapsed = 00:00:27 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 756 ; free virtual = 11129
  1364. # phys_opt_design -directive default
  1365. Command: phys_opt_design -directive default
  1366. Attempting to get a license for feature 'Implementation' and/or device 'xc7a50t'
  1367. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a50t'
  1368. INFO: [Vivado_Tcl 4-241] Physical synthesis in post route mode ( 100.0% nets are fully routed)
  1369. INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: default
  1370. INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations.
  1371. INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
  1372. INFO: [Common 17-83] Releasing license: Implementation
  1373. 6 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
  1374. phys_opt_design completed successfully
  1375. # write_checkpoint -force fairwaves_xtrx_route.dcp
  1376. INFO: [Timing 38-480] Writing timing data to binary archive.
  1377. Writing placer database...
  1378. Writing XDEF routing.
  1379. Writing XDEF routing logical nets.
  1380. Writing XDEF routing special nets.
  1381. Write XDEF Complete: Time (s): cpu = 00:00:00.97 ; elapsed = 00:00:00.30 . Memory (MB): peak = 3243.031 ; gain = 0.000 ; free physical = 746 ; free virtual = 11124
  1382. INFO: [Common 17-1381] The checkpoint '/home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx_route.dcp' has been generated.
  1383. # report_timing_summary -no_header -no_detailed_paths
  1384. INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
  1385. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
  1386. ------------------------------------------------------------------------------------------------
  1387. | Timer Settings
  1388. | --------------
  1389. ------------------------------------------------------------------------------------------------
  1390.  
  1391. Enable Multi Corner Analysis : Yes
  1392. Enable Pessimism Removal : Yes
  1393. Pessimism Removal Resolution : Nearest Common Node
  1394. Enable Input Delay Default Clock : No
  1395. Enable Preset / Clear Arcs : No
  1396. Disable Flight Delays : No
  1397. Ignore I/O Paths : No
  1398. Timing Early Launch at Borrowing Latches : No
  1399. Borrow Time for Max Delay Exceptions : Yes
  1400. Merge Timing Exceptions : Yes
  1401.  
  1402. Corner Analyze Analyze
  1403. Name Max Paths Min Paths
  1404. ------ --------- ---------
  1405. Slow Yes Yes
  1406. Fast Yes Yes
  1407.  
  1408.  
  1409. ------------------------------------------------------------------------------------------------
  1410. | Report Methodology
  1411. | ------------------
  1412. ------------------------------------------------------------------------------------------------
  1413.  
  1414. No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.
  1415.  
  1416.  
  1417.  
  1418. check_timing report
  1419.  
  1420. Table of Contents
  1421. -----------------
  1422. 1. checking no_clock (0)
  1423. 2. checking constant_clock (0)
  1424. 3. checking pulse_width_clock (0)
  1425. 4. checking unconstrained_internal_endpoints (0)
  1426. 5. checking no_input_delay (0)
  1427. 6. checking no_output_delay (1)
  1428. 7. checking multiple_clock (0)
  1429. 8. checking generated_clocks (0)
  1430. 9. checking loops (0)
  1431. 10. checking partial_input_delay (0)
  1432. 11. checking partial_output_delay (0)
  1433. 12. checking latch_loops (0)
  1434.  
  1435. 1. checking no_clock (0)
  1436. ------------------------
  1437. There are 0 register/latch pins with no clock.
  1438.  
  1439.  
  1440. 2. checking constant_clock (0)
  1441. ------------------------------
  1442. There are 0 register/latch pins with constant_clock.
  1443.  
  1444.  
  1445. 3. checking pulse_width_clock (0)
  1446. ---------------------------------
  1447. There are 0 register/latch pins which need pulse_width check
  1448.  
  1449.  
  1450. 4. checking unconstrained_internal_endpoints (0)
  1451. ------------------------------------------------
  1452. There are 0 pins that are not constrained for maximum delay.
  1453.  
  1454. There are 0 pins that are not constrained for maximum delay due to constant clock.
  1455.  
  1456.  
  1457. 5. checking no_input_delay (0)
  1458. ------------------------------
  1459. There are 0 input ports with no input delay specified.
  1460.  
  1461. There are 0 input ports with no input delay but user has a false path constraint.
  1462.  
  1463.  
  1464. 6. checking no_output_delay (1)
  1465. -------------------------------
  1466. There is 1 port with no output delay specified. (HIGH)
  1467.  
  1468. There are 0 ports with no output delay but user has a false path constraint
  1469.  
  1470. There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
  1471.  
  1472.  
  1473. 7. checking multiple_clock (0)
  1474. ------------------------------
  1475. There are 0 register/latch pins with multiple clocks.
  1476.  
  1477.  
  1478. 8. checking generated_clocks (0)
  1479. --------------------------------
  1480. There are 0 generated clocks that are not connected to a clock source.
  1481.  
  1482.  
  1483. 9. checking loops (0)
  1484. ---------------------
  1485. There are 0 combinational loops in the design.
  1486.  
  1487.  
  1488. 10. checking partial_input_delay (0)
  1489. ------------------------------------
  1490. There are 0 input ports with partial input delay specified.
  1491.  
  1492.  
  1493. 11. checking partial_output_delay (0)
  1494. -------------------------------------
  1495. There are 0 ports with partial output delay specified.
  1496.  
  1497.  
  1498. 12. checking latch_loops (0)
  1499. ----------------------------
  1500. There are 0 combinational latch loops in the design through latch input
  1501.  
  1502.  
  1503.  
  1504. ------------------------------------------------------------------------------------------------
  1505. | Design Timing Summary
  1506. | ---------------------
  1507. ------------------------------------------------------------------------------------------------
  1508.  
  1509. WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
  1510. ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
  1511. 1.009 0.000 0 4516 0.036 0.000 0 4516 2.902 0.000 0 1760
  1512.  
  1513.  
  1514. All user specified timing constraints are met.
  1515.  
  1516.  
  1517. ------------------------------------------------------------------------------------------------
  1518. | Clock Summary
  1519. | -------------
  1520. ------------------------------------------------------------------------------------------------
  1521.  
  1522. Clock Waveform(ns) Period(ns) Frequency(MHz)
  1523. ----- ------------ ---------- --------------
  1524. clk60 {0.000 8.333} 16.666 60.002
  1525. builder_pll_fb {0.000 8.333} 16.666 60.002
  1526. main_crg_clkout {0.000 4.032} 8.064 124.005
  1527.  
  1528.  
  1529. ------------------------------------------------------------------------------------------------
  1530. | Intra Clock Table
  1531. | -----------------
  1532. ------------------------------------------------------------------------------------------------
  1533.  
  1534. Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
  1535. ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
  1536. clk60 5.333 0.000 0 1
  1537. builder_pll_fb 15.417 0.000 0 2
  1538. main_crg_clkout 1.009 0.000 0 4516 0.036 0.000 0 4516 2.902 0.000 0 1757
  1539.  
  1540.  
  1541. ------------------------------------------------------------------------------------------------
  1542. | Inter Clock Table
  1543. | -----------------
  1544. ------------------------------------------------------------------------------------------------
  1545.  
  1546. From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
  1547. ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
  1548.  
  1549.  
  1550. ------------------------------------------------------------------------------------------------
  1551. | Other Path Groups Table
  1552. | -----------------------
  1553. ------------------------------------------------------------------------------------------------
  1554.  
  1555. Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
  1556. ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
  1557.  
  1558.  
  1559. # report_route_status -file fairwaves_xtrx_route_status.rpt
  1560. # report_drc -file fairwaves_xtrx_drc.rpt
  1561. Command: report_drc -file fairwaves_xtrx_drc.rpt
  1562. INFO: [IP_Flow 19-234] Refreshing IP repositories
  1563. INFO: [IP_Flow 19-1704] No user IP repositories specified
  1564. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/mikek/Documents/Xilinx/tools/Vivado/2021.2/data/ip'.
  1565. INFO: [DRC 23-27] Running DRC with 8 threads
  1566. INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/mikek/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx_drc.rpt.
  1567. report_drc completed successfully
  1568. # report_timing_summary -datasheet -max_paths 10 -file fairwaves_xtrx_timing.rpt
  1569. INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
  1570. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
  1571. # report_power -file fairwaves_xtrx_power.rpt
  1572. Command: report_power -file fairwaves_xtrx_power.rpt
  1573. Running Vector-less Activity Propagation...
  1574.  
  1575. Finished Running Vector-less Activity Propagation
  1576. WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
  1577. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
  1578. 0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
  1579. report_power completed successfully
  1580. # set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
  1581. # set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]
  1582. # set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
  1583. # write_bitstream -force fairwaves_xtrx.bit
  1584. Command: write_bitstream -force fairwaves_xtrx.bit
  1585. Attempting to get a license for feature 'Implementation' and/or device 'xc7a50t'
  1586. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a50t'
  1587. Running DRC as a precondition to command write_bitstream
  1588. INFO: [IP_Flow 19-1839] IP Catalog is up to date.
  1589. INFO: [DRC 23-27] Running DRC with 8 threads
  1590. WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
  1591.  
  1592. set_property CFGBVS value1 [current_design]
  1593. #where value1 is either VCCO or GND
  1594.  
  1595. set_property CONFIG_VOLTAGE value2 [current_design]
  1596. #where value2 is the voltage provided to configuration bank 0
  1597.  
  1598. Refer to the device configuration user guide for more information.
  1599. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_HL_reg input VexRiscv/execute_to_memory_MUL_HL_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
  1600. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_HL_reg input VexRiscv/execute_to_memory_MUL_HL_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
  1601. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_LH_reg input VexRiscv/execute_to_memory_MUL_LH_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
  1602. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_LH_reg input VexRiscv/execute_to_memory_MUL_LH_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
  1603. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_LL_reg input VexRiscv/execute_to_memory_MUL_LL_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
  1604. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_LL_reg input VexRiscv/execute_to_memory_MUL_LL_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
  1605. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/memory_to_writeBack_MUL_HH_reg input VexRiscv/memory_to_writeBack_MUL_HH_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
  1606. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/memory_to_writeBack_MUL_HH_reg input VexRiscv/memory_to_writeBack_MUL_HH_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
  1607. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP VexRiscv/execute_to_memory_MUL_HL_reg multiplier stage VexRiscv/execute_to_memory_MUL_HL_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
  1608. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP VexRiscv/execute_to_memory_MUL_LH_reg multiplier stage VexRiscv/execute_to_memory_MUL_LH_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
  1609. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP VexRiscv/execute_to_memory_MUL_LL_reg multiplier stage VexRiscv/execute_to_memory_MUL_LL_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
  1610. INFO: [Vivado 12-3199] DRC finished with 0 Errors, 12 Warnings
  1611. INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
  1612. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
  1613. Loading data files...
  1614. Loading site data...
  1615. Loading route data...
  1616. Processing options...
  1617. Creating bitmap...
  1618. Creating bitstream...
  1619. Bitstream compression saved 12578816 bits.
  1620. Writing bitstream ./fairwaves_xtrx.bit...
  1621. INFO: [Vivado 12-1842] Bitgen Completed Successfully.
  1622. INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
  1623. INFO: [Common 17-83] Releasing license: Implementation
  1624. 9 Infos, 12 Warnings, 0 Critical Warnings and 0 Errors encountered.
  1625. write_bitstream completed successfully
  1626. write_bitstream: Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 3344.648 ; gain = 101.617 ; free physical = 575 ; free virtual = 10964
  1627. # write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit "up 0x0 fairwaves_xtrx.bit" -file fairwaves_xtrx.bin
  1628. Command: write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit {up 0x0 fairwaves_xtrx.bit} -file fairwaves_xtrx.bin
  1629. Creating config memory files...
  1630. Creating bitstream load up from address 0x00000000
  1631. Loading bitfile fairwaves_xtrx.bit
  1632. Writing file ./fairwaves_xtrx.bin
  1633. Writing log file ./fairwaves_xtrx.prm
  1634. ===================================
  1635. Configuration Memory information
  1636. ===================================
  1637. File Format BIN
  1638. Interface SPIX4
  1639. Size 16M
  1640. Start Address 0x00000000
  1641. End Address 0x00FFFFFF
  1642.  
  1643. Addr1 Addr2 Date File(s)
  1644. 0x00000000 0x00097487 Dec 19 18:48:27 2021 fairwaves_xtrx.bit
  1645. 0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
  1646. write_cfgmem completed successfully
  1647. # set_property BITSTREAM.CONFIG.TIMER_CFG 0x0001fbd0 [current_design]
  1648. # set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design]
  1649. # write_bitstream -force fairwaves_xtrx_operational.bit
  1650. Command: write_bitstream -force fairwaves_xtrx_operational.bit
  1651. Attempting to get a license for feature 'Implementation' and/or device 'xc7a50t'
  1652. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a50t'
  1653. Running DRC as a precondition to command write_bitstream
  1654. INFO: [IP_Flow 19-1839] IP Catalog is up to date.
  1655. INFO: [DRC 23-27] Running DRC with 8 threads
  1656. WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
  1657.  
  1658. set_property CFGBVS value1 [current_design]
  1659. #where value1 is either VCCO or GND
  1660.  
  1661. set_property CONFIG_VOLTAGE value2 [current_design]
  1662. #where value2 is the voltage provided to configuration bank 0
  1663.  
  1664. Refer to the device configuration user guide for more information.
  1665. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_HL_reg input VexRiscv/execute_to_memory_MUL_HL_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
  1666. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_HL_reg input VexRiscv/execute_to_memory_MUL_HL_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
  1667. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_LH_reg input VexRiscv/execute_to_memory_MUL_LH_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
  1668. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_LH_reg input VexRiscv/execute_to_memory_MUL_LH_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
  1669. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_LL_reg input VexRiscv/execute_to_memory_MUL_LL_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
  1670. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_LL_reg input VexRiscv/execute_to_memory_MUL_LL_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
  1671. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/memory_to_writeBack_MUL_HH_reg input VexRiscv/memory_to_writeBack_MUL_HH_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
  1672. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/memory_to_writeBack_MUL_HH_reg input VexRiscv/memory_to_writeBack_MUL_HH_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
  1673. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP VexRiscv/execute_to_memory_MUL_HL_reg multiplier stage VexRiscv/execute_to_memory_MUL_HL_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
  1674. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP VexRiscv/execute_to_memory_MUL_LH_reg multiplier stage VexRiscv/execute_to_memory_MUL_LH_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
  1675. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP VexRiscv/execute_to_memory_MUL_LL_reg multiplier stage VexRiscv/execute_to_memory_MUL_LL_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
  1676. INFO: [Vivado 12-3199] DRC finished with 0 Errors, 12 Warnings
  1677. INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
  1678. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
  1679. Loading data files...
  1680. Loading site data...
  1681. Loading route data...
  1682. Processing options...
  1683. Creating bitmap...
  1684. Creating bitstream...
  1685. Bitstream compression saved 12578816 bits.
  1686. Writing bitstream ./fairwaves_xtrx_operational.bit...
  1687. INFO: [Vivado 12-1842] Bitgen Completed Successfully.
  1688. INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
  1689. INFO: [Common 17-83] Releasing license: Implementation
  1690. 9 Infos, 12 Warnings, 0 Critical Warnings and 0 Errors encountered.
  1691. write_bitstream completed successfully
  1692. write_bitstream: Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 3376.664 ; gain = 32.016 ; free physical = 695 ; free virtual = 11082
  1693. # write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit "up 0x0 fairwaves_xtrx_operational.bit" -file fairwaves_xtrx_operational.bin
  1694. Command: write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit {up 0x0 fairwaves_xtrx_operational.bit} -file fairwaves_xtrx_operational.bin
  1695. Creating config memory files...
  1696. Creating bitstream load up from address 0x00000000
  1697. Loading bitfile fairwaves_xtrx_operational.bit
  1698. Writing file ./fairwaves_xtrx_operational.bin
  1699. Writing log file ./fairwaves_xtrx_operational.prm
  1700. ===================================
  1701. Configuration Memory information
  1702. ===================================
  1703. File Format BIN
  1704. Interface SPIX4
  1705. Size 16M
  1706. Start Address 0x00000000
  1707. End Address 0x00FFFFFF
  1708.  
  1709. Addr1 Addr2 Date File(s)
  1710. 0x00000000 0x00097487 Dec 19 18:48:36 2021 fairwaves_xtrx_operational.bit
  1711. 0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
  1712. write_cfgmem completed successfully
  1713. # set_property BITSTREAM.CONFIG.NEXT_CONFIG_ADDR 0x00400000 [current_design]
  1714. # write_bitstream -force fairwaves_xtrx_fallback.bit
  1715. Command: write_bitstream -force fairwaves_xtrx_fallback.bit
  1716. Attempting to get a license for feature 'Implementation' and/or device 'xc7a50t'
  1717. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a50t'
  1718. Running DRC as a precondition to command write_bitstream
  1719. INFO: [IP_Flow 19-1839] IP Catalog is up to date.
  1720. INFO: [DRC 23-27] Running DRC with 8 threads
  1721. WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
  1722.  
  1723. set_property CFGBVS value1 [current_design]
  1724. #where value1 is either VCCO or GND
  1725.  
  1726. set_property CONFIG_VOLTAGE value2 [current_design]
  1727. #where value2 is the voltage provided to configuration bank 0
  1728.  
  1729. Refer to the device configuration user guide for more information.
  1730. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_HL_reg input VexRiscv/execute_to_memory_MUL_HL_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
  1731. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_HL_reg input VexRiscv/execute_to_memory_MUL_HL_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
  1732. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_LH_reg input VexRiscv/execute_to_memory_MUL_LH_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
  1733. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_LH_reg input VexRiscv/execute_to_memory_MUL_LH_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
  1734. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_LL_reg input VexRiscv/execute_to_memory_MUL_LL_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
  1735. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_LL_reg input VexRiscv/execute_to_memory_MUL_LL_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
  1736. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/memory_to_writeBack_MUL_HH_reg input VexRiscv/memory_to_writeBack_MUL_HH_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
  1737. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/memory_to_writeBack_MUL_HH_reg input VexRiscv/memory_to_writeBack_MUL_HH_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
  1738. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP VexRiscv/execute_to_memory_MUL_HL_reg multiplier stage VexRiscv/execute_to_memory_MUL_HL_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
  1739. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP VexRiscv/execute_to_memory_MUL_LH_reg multiplier stage VexRiscv/execute_to_memory_MUL_LH_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
  1740. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP VexRiscv/execute_to_memory_MUL_LL_reg multiplier stage VexRiscv/execute_to_memory_MUL_LL_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
  1741. INFO: [Vivado 12-3199] DRC finished with 0 Errors, 12 Warnings
  1742. INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
  1743. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
  1744. Loading data files...
  1745. Loading site data...
  1746. Loading route data...
  1747. Processing options...
  1748. Creating bitmap...
  1749. Creating bitstream...
  1750. Bitstream compression saved 12578816 bits.
  1751. Writing bitstream ./fairwaves_xtrx_fallback.bit...
  1752. INFO: [Vivado 12-1842] Bitgen Completed Successfully.
  1753. INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
  1754. INFO: [Common 17-83] Releasing license: Implementation
  1755. 9 Infos, 12 Warnings, 0 Critical Warnings and 0 Errors encountered.
  1756. write_bitstream completed successfully
  1757. write_bitstream: Time (s): cpu = 00:00:14 ; elapsed = 00:00:09 . Memory (MB): peak = 3376.664 ; gain = 0.000 ; free physical = 645 ; free virtual = 11039
  1758. # write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit "up 0x0 fairwaves_xtrx_fallback.bit" -file fairwaves_xtrx_fallback.bin
  1759. Command: write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit {up 0x0 fairwaves_xtrx_fallback.bit} -file fairwaves_xtrx_fallback.bin
  1760. Creating config memory files...
  1761. Creating bitstream load up from address 0x00000000
  1762. Loading bitfile fairwaves_xtrx_fallback.bit
  1763. Writing file ./fairwaves_xtrx_fallback.bin
  1764. Writing log file ./fairwaves_xtrx_fallback.prm
  1765. ===================================
  1766. Configuration Memory information
  1767. ===================================
  1768. File Format BIN
  1769. Interface SPIX4
  1770. Size 16M
  1771. Start Address 0x00000000
  1772. End Address 0x00FFFFFF
  1773.  
  1774. Addr1 Addr2 Date File(s)
  1775. 0x00000000 0x00097487 Dec 19 18:48:45 2021 fairwaves_xtrx_fallback.bit
  1776. 0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
  1777. write_cfgmem completed successfully
  1778. # quit
  1779. INFO: [Common 17-206] Exiting Vivado at Sun Dec 19 18:48:47 2021...
  1780. (Litex_venv) mikek@mikek-M6700:~/Documents/Cyclone_5/Litex/litex-boards/litex_boards/targets$
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