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NovaYoshi

DCPU-16 address registers

Oct 6th, 2018
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  1. Four 32-bit address registers, P0, P1, P2, P3
  2.  
  3. All extra instructions use the mask: ........fff1100f
  4.  
  5. ------------------- Load/store offset by small constant
  6.  
  7. SETB R, [Px+n] : load 8-bit zero extend
  8. 1100
  9. rrra annn 000 0
  10. Register r = [Address register a + n] zero extended
  11.  
  12. SETS R, [Px+n] : load 8-bit sign extend
  13. 1100
  14. rrra annn 000 1
  15. Register r = [Address register a + n] sign extended
  16.  
  17. SET R, [Px+n] : load 16-bit
  18. 1100
  19. rrra annn 001 0
  20. Register r = [Address register a + n*2]
  21.  
  22. SETB [Px+n], R : store 8-bit
  23. SETS [Px+n], R : store 8-bit
  24. 1100
  25. rrra annn 001 1
  26. [Address register a + n] = Register r
  27.  
  28. SET [Px+n], R : store 16-bit
  29. 1100
  30. rrra annn 010 0
  31. [Address register a + n*2] = Register r
  32.  
  33. ------------------- Load/store offset by register
  34.  
  35. SETB R, [Px+r] : load 8-bit zero extend
  36. 1100
  37. rrra aRRR 010 1
  38. Register r = [Address register a + Register R] zero extended
  39.  
  40. SETS R, [Px+r] : load 8-bit sign extend
  41. 1100
  42. rrra aRRR 011 0
  43. Register r = [Address register a + Register R] sign extended
  44.  
  45. SET R, [Px+r] : load 16-bit
  46. 1100
  47. rrra aRRR 011 1
  48. Register r = [Address register a + Register R]
  49.  
  50. SETB [Px+r], R : store 8-bit
  51. SETS [Px+r], R : store 8-bit
  52. 1100
  53. rrra aRRR 100 0
  54. [Address register a + Register R] = Register r
  55.  
  56. SET [Px+r], R : store 16-bit
  57. 1100
  58. rrra aRRR 100 1
  59. [Address register a + Register R] = Register r
  60.  
  61. -------------------
  62.  
  63. ADD Px, n : Add small constant to address register
  64. SUB Px, n : Subtract small constant from address register
  65. 1100
  66. aann nnnn 101 0
  67. Address register a += sign extended N
  68.  
  69. B
  70.  
  71. C
  72.  
  73. D
  74.  
  75. E
  76.  
  77. -------------------
  78.  
  79. SET PxL, R : Load low half of address register with register
  80. 1100
  81. 000a aRRR 111 1
  82.  
  83. SET PxH, R: Load high half of address register with register
  84. 1100
  85. 001a aRRR 111 1
  86.  
  87. ADD Px, R : Add register to address register
  88. 1100
  89. 010a aRRR 111 1
  90.  
  91. SUB Px, R : Subtract register from address register
  92. 1100
  93. 011a aRRR 111 1
  94.  
  95. 1100
  96. 100a aRRR 111 1
  97.  
  98. 1100
  99. 101a aRRR 111 1
  100.  
  101. 1100
  102. 110a aRRR 111 1
  103.  
  104. ------------------- No-operand address register operations
  105.  
  106. SET PUSH, Px : Push address register
  107. 111 1100
  108. a a000 111 1
  109. Pushes an address register to the stack
  110.  
  111.  
  112. SET Px, POP : Pop address register
  113. 111 1100
  114. a a001 111 1
  115. Pops an address register from the stack
  116.  
  117. SET Px, constant : Load a 32-bit constant
  118. 111 1100
  119. a a010 111 1 nnnnnnnn nnnnnnnn nnnnnnnn nnnnnnnn
  120. Px = a constant
  121.  
  122. SET Px, [word] : Load address register from memory
  123. 111 1100
  124. a a011 111 1 nnnnnnnn nnnnnnnn
  125. Px = [word]
  126.  
  127. SET [word], Px : Store address register to memory
  128. 111 1100
  129. a a100 111 1 nnnnnnnn nnnnnnnn
  130. [word] = Px
  131.  
  132. 111 1100
  133. a a101 111 1
  134.  
  135. 111 1100
  136. a a110 111 1
  137.  
  138. 111 1100
  139. a a111 111 1
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