module counter16bit(clk,reset,q);
    input clk,reset;
    output [15:0]q;
    reg [15:0]q;

    initial q=16'b1111111111111110;

    always @(posedge clk) begin
    if (reset)
        q=16'b0;
    else
        q=q+1;
    end
endmodule