library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity numarator_minute is
	port(clk,reset:in std_logic;
	iesire:out std_logic_vector(5 downto 0));
end numarator_minute;

architecture  arh_minute of numarator_minute is
signal copie: std_logic_vector(5 downto 0):="000000";
begin
	process(clk,reset)
	begin
	if(reset='1') then
		copie<="000000";
	elsif(clk='1' and clk'event) then
		copie<=copie+"000001";
	end if;
	if(copie="111011")then
		copie<="000000" after 0 ms;
	end if;
end process;
iesire<=copie;
end arh_minute;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity numarator_ore is
	port(clk,reset:in std_logic;
	iesire:out std_logic_vector(4 downto 0));
end numarator_ore;

architecture  arh_ore of numarator_ore is
signal copie: std_logic_vector(4 downto 0):="00000";
begin
	process(clk,reset)
	begin
	if(reset='1') then
		copie<="00000";
	elsif(clk='1' and clk'event) then
		copie<=copie+"00001";
	end if;
	if(copie="10111")then
		copie<="00000";
	end if;
end process;
iesire<=copie;
end arh_ore;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity numarator_zile2 is
	port(clk,reset:in std_logic;
	iesire:out std_logic_vector(2 downto 0));
end numarator_zile2;

architecture  arh_zile2 of numarator_zile2 is
signal copie: std_logic_vector(2 downto 0):="001";
begin
	process(clk,reset)
	begin
	if(reset='1') then
		copie<="001";
	elsif(clk='1' and clk'event) then
		copie<=copie+"001";
	end if;
	if(copie="111")then
		copie<="001";
	end if;
	end process;
iesire<=copie;
end arh_zile2;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity numarator_zile1 is
	port(clk,reset:in std_logic;
	iesire:out std_logic_vector(4 downto 0));
end numarator_zile1;

architecture  arh_zile1 of numarator_zile1 is
signal copie: std_logic_vector(4 downto 0):="00001";
begin
	process(clk,reset)
	begin
	if(reset='1') then
		copie<="00001";
	elsif(clk='1' and clk'event) then
		copie<=copie+"00001";
	end if;
	if(copie="11110")then
		copie<="00001";
	end if;
end process;
iesire<=copie;
end arh_zile1;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity numarator_luni is
	port(clk,reset:in std_logic;
	iesire:out std_logic_vector(3 downto 0));
end numarator_luni;

architecture  arh_luni of numarator_luni is
signal copie: std_logic_vector(3 downto 0):="0001";
begin
	process(clk,reset)
	begin
	if(reset='1') then
		copie<="0001";
	elsif(clk='1' and clk'event) then
		copie<=copie+"0001";
	end if;
	if(copie="1100")then
		copie<="0001";
	end if;
	end process;
iesire<=copie;
end arh_luni;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity numarator_ani is
	port(clk,reset:in std_logic;
	iesire:out std_logic_vector(11 downto 0));
end numarator_ani;

architecture  arh_ani of numarator_ani is
signal copie: std_logic_vector(11 downto 0):="011111100011";
begin
	process(clk,reset)
	begin
	if(reset='1') then
		copie<="011111100011";
	elsif(clk='1' and clk'event) then
		copie<=copie+"000000000001";
	end if;
end process;
iesire<=copie;
end arh_ani;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity numarator_minute is
	port(clk,reset:in std_logic;
	iesire:out std_logic_vector(5 downto 0));
end numarator_minute;

architecture  arh_minute2 of numarator_minute is
signal copie: std_logic_vector(5 downto 0):="000000";
begin
	process(clk,reset)
	begin
	if(reset='1') then
		copie<="000000";
	elsif(clk='1' and clk'event) then
		copie<=copie+"000001";
	end if;
	if(copie="111011")then
		copie<="000000" after 0 ms;
	end if;
end process;
iesire<=copie;
end arh_minute2;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity numarator_ore is
	port(clk,reset:in std_logic;
	iesire:out std_logic_vector(4 downto 0));
end numarator_ore;

architecture  arh_ore2 of numarator_ore is
signal copie: std_logic_vector(4 downto 0):="00000";
begin
	process(clk,reset)
	begin
	if(reset='1') then
		copie<="00000";
	elsif(clk='1' and clk'event) then
		copie<=copie+"00001";
	end if;
	if(copie="10111")then
		copie<="00000";
	end if;
end process;
iesire<=copie;
end arh_ore2;
library ieee;
use ieee.std_logic_1164.all;

entity sapte_segmente is
	port(
	x:in std_logic_vector(2 downto 0);
	y:out std_logic_vector(6 downto 0)
	);
end sapte_segmente;

architecture decodificatorprimalitera of sapte_segmente is
begin
	with x select
	y<="0001110" when "001",
	"1110110" when "010",
	"1110110" when "011",
	"0111000" when "100",
	"0111110" when "101",
	"1011011" when "110",
	"1111110" when "111",
	"0000001" when others;
end decodificatorprimalitera;
architecture decodificatoradoualitera of sapte_segmente is
begin
	with x select
	y<="0111110" when "001",
	"1110111" when "010",
	"0110000" when "011",
	"1111110" when "100",
	"0110000" when "101",
	"1110111" when "110",
	"0111110" when "111",
	"0000001" when others;
end decodificatoradoualitera;
library IEEE;
use ieee.std_Logic_1164.all;
entity comparator5 is
	port( intrare1,intrare2:in std_logic_vector(4 downto 0);
	iesire:out std_logic);
end comparator5;

architecture comparator5b of comparator5 is
begin
 iesire<= '1' when (intrare1=intrare2) else '0';
end comparator5b;
library IEEE;
use ieee.std_Logic_1164.all;
entity comparator6 is
	port( intrare1,intrare2:in std_logic_vector(5 downto 0);
	iesire:out std_logic);
end comparator6;

architecture comparator6b of comparator6 is
begin
 iesire<= '1' when (intrare1=intrare2) else '0';
end comparator6b;
library IEEE;
use ieee.std_logic_1164.all;
entity poarta_si is
	port(a,b:in std_logic;
	iesire:out std_logic);
end poarta_si;
architecture si of poarta_si is
begin
	iesire<=a and b;
end si;