10.26
11.3, .6, .7, .14, .15
12.6, .12
13.3, .4
14.3, .5
15.1, .4
16.3, .7
17.5, .9, .16


Addressing Modes

Pipeline Hazards

RISC Designs
	1. More registers
	2. Speed up
	3. Loops and Loads/Stores

Instruction lvl Parallelism
	-how muh

Cache coherence
	-understand
	-protocol for c.c
	-how works: directory, mesi

Multicore computers
	-

Betterz
	-Fixed of variable length instructions:				fixed -- fetch, look at opcode, then operands... If fixed, opcode easy
	-Large cache vs large registers:					registers -- access patterns; registers fast, cache slow; cache -- less memory look-ups
	-Short vs long instruction pipeline:				short -- bad because need to wait for opcode to load; long -- bad because need more registers to compensate for instruction
	-RISC vs CISC										RISC -- fast, CICS --
	-Scoreboard vs Tomasulo								tomasulo -- register renaming, avoid dependencies Write after read, read after write; scoreboard -- depect dependency and stall
	-Hardwired vs microprogammed						hardwire -- faster, difficult to debug; microprogrammed -- functionality
	-Directory vs MESI cache coherence					directory -- NUMA (to directory through bus, then everywhere else); MESI -- common bus braodcast faster



I1: r3b = r3a + r5a
I2: r4a = r3b + 1
I3: r3c = r5a +1
I4: r7a = r3c + r4a
I5: r5b = r4a + r7a

I2: RAW depends on I1, r3
I3: WAR depends on I2, r3
I4: RAW depends on I3, r3
I5: WAR depends on I4, r7
I1: r3b = r3a + r5a
I2: r4a = r3b + 1
I3: r3c = r5a +1
I4: r7a = r3c + r4a
I5: r5b = r4a + r7a


redesign using fetch, indirect

MBR --> PC
PC --> MAR
MAR --> memory
memory --> MBR