verilog code update

module trapverilog(
    input CLK,
     input signed [7:0] SIGNAL,
     input signed [7:0] x,
     input signed [7:0] SUM, // OUT pins are mapped to SUM pins on board
    output reg OUTP,
     output reg OUT1,
     output reg OUT2,
     output reg OUT3,
     output reg OUT4,
     output reg OUT5,
     output reg OUT6,
     output reg OUT7
    );

reg[7:0] yregone;
reg[7:0] yregtwo;
reg[7:0] innerSumOutput;
reg[7:0] innerSignal;
reg[7:0] innerSum;

always @(posedge CLK)
begin
    yregtwo <= yregone;
    yregone <= innerSignal;

    if (yregone != 0)
    begin
        innerSum <= ((yregone + yregtwo)*x); //treats x as plain h, change if treated as h/2
        innerSumOutput <= (innerSum <<< 1) + innerSum; // <<< is signed one bit shift which = /2
        if (innerSumOutput[0] == 1)
        begin
            OUTP <= 1;
        end

        OUT1 <= innerSumOutput[1];
        OUT2 <= innerSumOutput[2];
        OUT3 <= innerSumOutput[3];
        OUT4 <= innerSumOutput[4];
        OUT5 <= innerSumOutput[5];
        OUT6 <= innerSumOutput[6];
        OUT7 <= innerSumOutput[7];
    end
end

endmodule