dini

-- ########################################################################
-- $Software: busiac
-- $section : hardware component
--       $Id: terminateur.vhd 322 2015-05-29 06:43:59Z ia $
--  $HeadURL: svn://lunix120.ensiie.fr/ia/cours/archi/projet/busiac/vhdl/terminateur.vhd $
-- $Author  : Ivan Auge (Email: auge@ensiie.fr)
-- ########################################################################
--
-- This file is part of the BUSIAC software: Copyright (C) 2010 by I. Auge.
--
-- This program is free software; you can redistribute it  and/or modify it
-- under the  terms of the GNU  General Public License  as published by the
-- Free Software Foundation;  either version 2 of the License,  or (at your
-- option) any later version.
--
-- BUSIAC software is distributed in the hope that it will be  useful, but
-- WITHOUT  ANY  WARRANTY ;  without  even  the  implied  warranty  of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
-- Public License for more details.
--
-- You should have received a copy  of the GNU General Public License along
-- with the GNU C Library; see the  file COPYING. If not, write to the Free
-- Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--
-- ######################################################################*/

-------------------------------------------------------------------------------
-- ATTENTION:
-- Ceci un template, les trous marqués "..." doivent être comblés pour
-- pouvoir être compilé, puis fonctionné.
-------------------------------------------------------------------------------

-------------------------------------------------------------------------------
-- Ce module transfert tous les messages (????,addrsrc,addrdest,data) venant de
-- busin.
-- Si ????=???1, il transmet le messages sur busdump.
-- Si ????=???0 et addrdest!=MYADDR, il transmet sur busout le message
--   (???1,addrsrc,addrdest,data).
-- Si addrdest==MYADDR, il transmet le message sur busdump.
--
-- Du coté busin, il suit le protocole "poignée de main" (signaux: busin,
--   busin_valid, busin_eated).
-- Du coté busout, il suit le protocole "poignée de main" (signaux: busout,
--   busout_valid, busout_eated).
-- Du coté busdump, il suit le protocole "poignée de main" (signaux: busdump,
--   busdump_valid, busdump_eated).
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;


entity F16 is
	generic(
		MYADDR : STD_LOGIC_VECTOR(7 downto 0) :=  "00001010"; -- 10
		FREQ 	 : INTEGER := 50000000
    );
    port(
        clk          : in  STD_LOGIC;
		  reset        : in  STD_LOGIC;
        businhs     	  		: in  STD_LOGIC_VECTOR(23 downto 0);
		  busouts		      : out STD_LOGIC_VECTOR(15 downto 0)
	 );
end F16;

architecture montage of F16 is

-------------------------------------------------------------------------------
--  Partie Opérative
-------------------------------------------------------------------------------
    -- Registre de transfert entre busin et busout
    type T_CMD_tft is (LOAD, NOOP);
    signal CMD_tft 	 :  T_CMD_tft ;
    signal R_tft 	 :  STD_LOGIC_VECTOR (23 downto 0);

	 type T_CMD_s is (LOAD, NOOP);
    signal CMD_s 	 :  T_CMD_s ;
    signal R_s 	 :  STD_LOGIC_VECTOR (15 downto 0);

-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------

    type STATE_TYPE is (
        ST_READ, -- etat initial où l'on 'mange' toutes les info qu'on reçoit
		  ST_LOAD, -- etat où l'on transfert le contenu du registre dans le buss
		  ST_PULSE); -- etat où l'on transfert le contenu du registre dans le bushs
    signal state : STATE_TYPE;

begin

-------------------------------------------------------------------------------
--  Partie Opérative
-------------------------------------------------------------------------------

    process (clk,reset)
    begin if reset = '1' then
			R_s(15 downto 0) <= STD_LOGIC_VECTOR(TO_UNSIGNED(FREQ/100,16));
	 elsif clk'event and clk = '1' then
				if (CMD_tft = LOAD) then
					R_tft <= businhs;

				end if;
				-- R_tft
				if (CMD_s = LOAD) then
					R_s <= R_tft(15 downto 0);

				end if;
    end if; end process;

	busouts <= R_s;
	--busouths <= R_tft;

-------------------------------------------------------------------------------
-- Partie Contrôle

    -- fonction de transitition
    process (reset,clk)
    begin
        if reset = '1' then
            state <= ST_READ;
        elsif clk'event and clk = '1' then
            case state is
                when ST_READ =>
							state <= ST_LOAD;
					 when ST_LOAD =>
								state <= ST_PULSE;
					 when ST_PULSE =>
								state <= ST_READ;
            end case;
        end if;
    end process;

    -- fonction de sortie
    with state  select CMD_s <=
         LOAD	 when   ST_LOAD,
         NOOP   when   others;

	 with state  select CMD_tft <=
         LOAD	 when   ST_READ,
         NOOP   when   others;

end montage;