module RDC_config(
input clk_10MHz,
input clk_20MHz,
input clk_100MHz,
output reg FSYNC,
output [1:0] A_x,
output SOE,
output CS,
output reg SDI,
output S_CLK
);

reg [2:0] state = 1; //initialize current state of state machine register
reg [2:0] next_state = 1; //initialize next state of state machine register
reg [5:0] counter_20MHz = 0; //initialize counter register for 20MHz clock edges
reg [5:0] counter_10MHz = 0; //initialize counter register for 10MHz clock edges
reg SDI = 1'b0; //initialize data line to 0
reg FSYNC = 1'b1; //initialize FSYNC to 1

//initialize state machine or go to next state
always@(posedge clk_100MHz)
begin
    state <= next_state;
end

//Counter for tracking number of 10MHz clock edges
always@(posedge clk_10MHz)begin
    counter_10MHz <= counter_10MHz+1;
end

//Counter for tracking number of 20MHz clock edges
always@(posedge clk_20MHz)begin
    counter_20MHz <= counter_20MHz+1;
end


//This state machine changes the excitation frequency parameter of the RDC to be 5KHz.
//It sends out 0x91 as the RDC register address and then 0x14 as the register value.
always@(state or counter_10MHz or counter_20MHz) begin
    case(state)
        0:   //State 0: end state
            begin
               SDI <= 1'b0;
               FSYNC <= 1'b1;
               next_state <= 0;
            end
        1:   //State 1: wait 5 20MHz clock edges, then set FSYNC low
            if(counter_20MHz == 5)begin
               FSYNC <= 1'b0;
               SDI <= 1'b0;
               next_state <= 2;
            end
        2:  //State 2: wait one 20MHz clock edge, then set SDI high
            if(counter_20MHz == 6)begin
               FSYNC <= 1'b0;
               SDI <= 1'b1;
               next_state <= 3;
            end
        3:  //State 3: wait two 20MHz clock edges, then set SDI low
            if(counter_20MHz == 8)begin
               FSYNC <= 1'b0;
               SDI <= 1'b0;
               next_state <= 4;
            end
        4:  //State 4: wait four 20MHz clock edges, then set SDI high
            if(counter_20MHz == 12)begin
               FSYNC <= 1'b0;
               SDI <= 1'b1;
               next_state <= 5;
            end
        5:  //State 5: wait two 20MHz clock edges, then set SDI low
            if(counter_20MHz == 14)begin
               FSYNC <= 1'b0;
               SDI <= 1'b0;
               next_state <= 6;
            end
        6:  //State 6: wait six 20MHz clock edges, then set SDI high
            if(counter_20MHz == 20)begin
               FSYNC <= 1'b0;
               SDI <= 1'b1;
               next_state <= 7;
            end
        7:  //State 7: wait eleven 10MHz clock edges, then set FSYNC high
            if(counter_10MHz == 11)begin
               FSYNC <= 1'b1;
               SDI <= 1'b1;
               next_state <= 8;
            end
        8:  //State 8: wait two 20MHz clock edges from state 6, then set SDI low. 0x91 has been sent.
            if(counter_20MHz == 22)begin
               FSYNC <= 1'b1;
               SDI <= 1'b0;
               next_state <= 9;
            end
        9:  //State 9: wait seven 20MHz clock edges, then set FSYNC low
            if(counter_20MHz == 29)begin
               FSYNC <= 1'b0;
               SDI <= 1'b0;
               next_state <= 10;
            end
        10:  //State 10: wait 18 10MHz clock edges, then set SDI high
            if(counter_10MHz == 18)begin
               FSYNC <= 1'b0;
               SDI <= 1'b1;
               next_state <= 11;
            end
        11:  //State 11: wait 1 10MHz clock edge, then set SDI low
            if(counter_10MHz == 19)begin
               FSYNC <= 1'b0;
               SDI <= 1'b0;
               next_state <= 12;
            end
        12:  //State 12: wait 1 10MHz clock edge, then set SDI high
            if(counter_10MHz == 20)begin
               FSYNC <= 1'b0;
               SDI <= 1'b1;
               next_state <= 13;
            end
        13:  //State 13: wait 1 10MHz clock edge, then set SDI low
            if(counter_10MHz == 21)begin
               FSYNC <= 1'b0;
               SDI <= 1'b0;
               next_state <= 14;
            end
        14:  //State 14: wait 45 20MHz clock edges, then set FSYNC high. 0x14 has been sent
            if(counter_20MHz == 45)begin
               FSYNC <= 1'b1;
               SDI <= 1'b0;
               next_state <= 0;
            end
    endcase
end

assign SOE = 1'b0; //enable serial configuration on RDC
assign A_x = 2'b11; //set to configuration mode
assign CS = 1'b0; //chip select held low
assign SCLK = clk_10MHz; //RDC SCLK set to 10MHz
endmodule