U-Boot SPL board init
spl_early_init
uclass_find_device_by_seq: 0 -1
uclass_find_device_by_seq: 0 0
   - -1 -1 'root_driver'
   - not found
clk_set_defaults()
clk_set_default_parents: could not read assigned-clock-parents for ff8ec020
ofnode_read_bool: u-boot,dm-pre-reloc: true
ofnode_read_bool: u-boot,dm-pre-reloc: true
ofnode_read_bool: u-boot,dm-pre-reloc: true
ofnode_read_bool: u-boot,dm-pre-reloc: true
ofnode_read_bool: u-boot,dm-pre-reloc: true
ofnode_read_bool: u-boot,dm-pre-reloc: true
ofnode_read_bool: u-boot,dm-pre-reloc: true
ofnode_read_bool: u-boot,dm-pre-reloc: true
ofnode_read_bool: u-boot,dm-pre-reloc: true
ofnode_read_bool: u-boot,dm-pre-reloc: true
uclass_find_device_by_seq: 0 -1
uclass_find_device_by_seq: 0 0
   - -1 -1 'power-management@ff310000'
   - -1 -1 'syscon@ff320000'
   - -1 -1 'syscon@ff330000'
   - -1 -1 'syscon@ff620000'
   - -1 -1 'syscon@ff770000'
   - not found
uclass_find_device_by_seq: 0 -1
uclass_find_device_by_seq: 0 0
   - -1 -1 'pinctrl'
   - not found
clk_set_defaults(pinctrl)
clk_set_default_parents: could not read assigned-clock-parents for ff8ee2a0
ofnode_read_u32: rockchip,grf: x (17)
uclass_find_device_by_seq: 0 -1
uclass_find_device_by_seq: 0 0
   - -1 -1 'power-management@ff310000'
   - -1 -1 'syscon@ff320000'
   - -1 0 'syscon@ff330000'
   - found
uclass_find_device_by_seq: 0 1
   - -1 -1 'power-management@ff310000'
   - -1 -1 'syscon@ff320000'
   - -1 0 'syscon@ff330000'
   - -1 -1 'syscon@ff620000'
   - -1 -1 'syscon@ff770000'
   - not found
fdtdec_get_addr_size_fixed: reg: addr=00000000x, size=x
ofnode_read_bool: little-endian: false
ofnode_read_bool: big-endian: false
ofnode_read_bool: native-endian: false
clk_set_defaults(syscon@ff770000)
clk_set_default_parents: could not read assigned-clock-parents for ff8ee1d0
ofnode_read_u32: rockchip,pmu: x (116)
uclass_find_device_by_seq: 0 -1
uclass_find_device_by_seq: 0 0
   - -1 -1 'power-management@ff310000'
   - -1 -1 'syscon@ff320000'
   - -1 0 'syscon@ff330000'
   - found
uclass_find_device_by_seq: 0 1
   - -1 -1 'power-management@ff310000'
   - -1 -1 'syscon@ff320000'
   - -1 0 'syscon@ff330000'
   - -1 -1 'syscon@ff620000'
   - -1 1 'syscon@ff770000'
   - found
uclass_find_device_by_seq: 0 2
   - -1 -1 'power-management@ff310000'
   - -1 -1 'syscon@ff320000'
   - -1 0 'syscon@ff330000'
   - -1 -1 'syscon@ff620000'
   - -1 1 'syscon@ff770000'
   - not found
fdtdec_get_addr_size_fixed: reg: addr=00000000x, size=x
ofnode_read_bool: little-endian: false
ofnode_read_bool: big-endian: false
ofnode_read_bool: native-endian: false
clk_set_defaults(syscon@ff320000)
clk_set_default_parents: could not read assigned-clock-parents for ff8ec4e8
bank 0, iomux 0 has iom_offset 0x0 drv_offset 0x80
bank 0, iomux 1 has iom_offset 0x4 drv_offset 0x88
bank 0, iomux 2 has iom_offset 0x8 drv_offset 0x8c
bank 0, iomux 3 has iom_offset 0xc drv_offset 0x90
bank 1, iomux 0 has iom_offset 0x10 drv_offset 0xa0
bank 1, iomux 1 has iom_offset 0x14 drv_offset 0xa8
bank 1, iomux 2 has iom_offset 0x18 drv_offset 0xb0
bank 1, iomux 3 has iom_offset 0x1c drv_offset 0xb8
bank 2, iomux 0 has iom_offset 0xe000 drv_offset 0xe100
bank 2, iomux 1 has iom_offset 0xe004 drv_offset 0xe104
bank 2, iomux 2 has iom_offset 0xe008 drv_offset 0xe108
bank 2, iomux 3 has iom_offset 0xe00c drv_offset 0xe10c
bank 3, iomux 0 has iom_offset 0xe010 drv_offset 0xe110
bank 3, iomux 1 has iom_offset 0xe014 drv_offset 0xe118
bank 3, iomux 2 has iom_offset 0xe018 drv_offset 0xe120
bank 3, iomux 3 has iom_offset 0xe01c drv_offset 0xe128
bank 4, iomux 0 has iom_offset 0xe020 drv_offset 0xe12c
bank 4, iomux 1 has iom_offset 0xe024 drv_offset 0xe130
bank 4, iomux 2 has iom_offset 0xe028 drv_offset 0xe138
bank 4, iomux 3 has iom_offset 0xe02c drv_offset 0xe13c
fdtdec_get_addr_size_fixed: reg: addr=00000000x, size=x
ofnode_read_bool: little-endian: false
ofnode_read_bool: big-endian: false
ofnode_read_bool: native-endian: false
clk_set_defaults(syscon@ff330000)
clk_set_default_parents: could not read assigned-clock-parents for ff8ec588
uclass_find_device_by_seq: 0 -1
uclass_find_device_by_seq: 0 0
   - -1 -1 'dmc'
   - not found
ofnode_read_u32_array: rockchip,sdram-params: fdtdec_get_int_array: rockchip,sdram-params
get_prop_check_min_len: rockchip,sdram-params
fdtdec_get_addr_size_fixed: reg: addr=00000000x, size=x
fdtdec_get_addr_size_fixed: reg: addr=00000000x, size=x
fdtdec_get_addr_size_fixed: reg: addr=00000000x, size=x
fdtdec_get_addr_size_fixed: reg: addr=00000000x, size=x
fdtdec_get_addr_size_fixed: reg: addr=00000000x, size=x
fdtdec_get_addr_size_fixed: reg: addr=00000000x, size=x
fdtdec_get_addr_size_fixed: reg: addr=00000000x, size=x
fdtdec_get_addr_size_fixed: reg: addr=00000000x, size=x
ofnode_read_bool: little-endian: false
ofnode_read_bool: big-endian: false
ofnode_read_bool: native-endian: false
clk_set_defaults(dmc)
clk_set_default_parents: could not read assigned-clock-parents for ff8ec6f8
uclass_find_device_by_seq: 0 -1
uclass_find_device_by_seq: 0 0
   - -1 -1 'power-management@ff310000'
   - -1 2 'syscon@ff320000'
   - -1 0 'syscon@ff330000'
   - found
uclass_find_device_by_seq: 0 1
   - -1 -1 'power-management@ff310000'
   - -1 2 'syscon@ff320000'
   - -1 0 'syscon@ff330000'
   - -1 -1 'syscon@ff620000'
   - -1 1 'syscon@ff770000'
   - found
uclass_find_device_by_seq: 0 2
   - -1 -1 'power-management@ff310000'
   - -1 2 'syscon@ff320000'
   - found
uclass_find_device_by_seq: 0 3
   - -1 -1 'power-management@ff310000'
   - -1 2 'syscon@ff320000'
   - -1 0 'syscon@ff330000'
   - -1 -1 'syscon@ff620000'
   - -1 1 'syscon@ff770000'
   - not found
fdtdec_get_addr_size_fixed: reg: addr=00000000x, size=x
ofnode_read_bool: little-endian: false
ofnode_read_bool: big-endian: false
ofnode_read_bool: native-endian: false
clk_set_defaults(syscon@ff620000)
clk_set_default_parents: could not read assigned-clock-parents for ff8ec628
uclass_find_device_by_seq: 0 -1
uclass_find_device_by_seq: 0 0
   - -1 -1 'power-management@ff310000'
   - -1 2 'syscon@ff320000'
   - -1 0 'syscon@ff330000'
   - found
uclass_find_device_by_seq: 0 1
   - -1 -1 'power-management@ff310000'
   - -1 2 'syscon@ff320000'
   - -1 0 'syscon@ff330000'
   - -1 3 'syscon@ff620000'
   - -1 1 'syscon@ff770000'
   - found
uclass_find_device_by_seq: 0 2
   - -1 -1 'power-management@ff310000'
   - -1 2 'syscon@ff320000'
   - found
uclass_find_device_by_seq: 0 3
   - -1 -1 'power-management@ff310000'
   - -1 2 'syscon@ff320000'
   - -1 0 'syscon@ff330000'
   - -1 3 'syscon@ff620000'
   - found
uclass_find_device_by_seq: 0 4
   - -1 -1 'power-management@ff310000'
   - -1 2 'syscon@ff320000'
   - -1 0 'syscon@ff330000'
   - -1 3 'syscon@ff620000'
   - -1 1 'syscon@ff770000'
   - not found
fdtdec_get_addr_size_fixed: reg: addr=00000000x, size=x
ofnode_read_bool: little-endian: false
ofnode_read_bool: big-endian: false
ofnode_read_bool: native-endian: false
clk_set_defaults(power-management@ff310000)
clk_set_default_parents: could not read assigned-clock-parents for ff8ec448
uclass_find_device_by_seq: 0 -1
uclass_find_device_by_seq: 0 0
   - -1 -1 'pmu-clock-controller@ff750000'
   - -1 -1 'clock-controller@ff760000'
   - not found
fdtdec_get_addr_size_auto_parent: na=2, ns=2, fdtdec_get_addr_size_fixed: reg: addr=00000000x
clk_set_defaults(pmu-clock-controller@ff750000)
clk_set_default_parents: could not read assigned-clock-parents for ff8edfb8
uclass_find_device_by_seq: 0 -1
uclass_find_device_by_seq: 0 0
   - -1 0 'pmu-clock-controller@ff750000'
   - found
uclass_find_device_by_seq: 0 1
   - -1 0 'pmu-clock-controller@ff750000'
   - -1 -1 'clock-controller@ff760000'
   - not found
fdtdec_get_addr_size_auto_parent: na=2, ns=2, fdtdec_get_addr_size_fixed: reg: addr=00000000x
clk_set_defaults(clock-controller@ff760000)
clk_set_default_parents: could not read assigned-clock-parents for ff8ee058
rk3399_configure_cpu_l: 429   PLL at ff760000: fbdiv=50, refdiv=1, postdiv1=2, postdiv2=1, vco=1200000 khz, output=600000 khz
rk3399_configure_cpu_b: 463   PLL at ff760020: fbdiv=50, refdiv=1, postdiv1=2, postdiv2=1, vco=1200000 khz, output=600000 khz
rkclk_init: 1123   PLL at ff760080: fbdiv=99, refdiv=2, postdiv1=2, postdiv2=1, vco=1188000 khz, output=594000 khz
PLL at ff760060: fbdiv=64, refdiv=1, postdiv1=2, postdiv2=2, vco=1536000 khz, output=384000 khz
con reg ffa80000 ffa80800 ffa82000 ffa84000 ffa88000 ffa88800 ffa8a000 ffa8c000
cru ff760000, cic ff620000, grf ff320000, sgrf ff330000, pmucru ff750000, pmu ff310000
clk_get_by_indexed_prop(dev=ff8ec6f8, index=0, clk=ff8ee3f8)
fdtdec_get_int: #clock-cells: x (1)
clk_of_xlate_default(clk=ff8ee3f8)
clk_request(dev=ff8ee058, clk=ff8ee3f8)
clk_set_rate(clk=ff8ee3f8, rate=50000000)
rk3399_ddr_set_clk: 869   PLL at ff760040: fbdiv=50, refdiv=1, postdiv1=6, postdiv2=4, vco=1200000 khz, output=50000 khz
Starting SDRAM initialization...
Channel 0: LPDDR4, MHz
BW= Col= Bk= CS0 Row= CS1 Row= CS= Die BW= Size=MB
Channel 1: LPDDR4, MHz
BW= Col= Bk= CS0 Row= CS1 Row= CS= Die BW= Size=MB
256B stride
clk_set_rate(clk=ff8ee3f8, rate=400000000)
rk3399_ddr_set_clk: 869   PLL at ff760040: fbdiv=50, refdiv=1, postdiv1=3, postdiv2=1, vco=1200000 khz, output=400000 khz
clk Hang:2824
4096 : 0
clk Hang:2837
channel 0 training pass
channel 1 training pass
change freq to 400 MHz 0, 1
clk_set_rate(clk=ff8ee3f8, rate=800000000)
rk3399_ddr_set_clk: 869   PLL at ff760040: fbdiv=100, refdiv=3, postdiv1=1, postdiv2=1, vco=800000 khz, output=800000 khz
clk Hang:2824
4096 : 16
clk Hang:2837
channel 0 training pass
channel 1 training pass
change freq to 800 MHz 1, 0
Finish SDRAM initialization...
>>SPL: board_init_r()
spl_init
Trying to boot from MMC1
uclass_find_device_by_seq: 0 0
   - -1 -1 'sdhci@fe330000'
   - not found
uclass_find_device_by_seq: 1 0
   - -1 -1 'sdhci@fe330000'
   - not found
uclass_find_device_by_seq: 0 -1
uclass_find_device_by_seq: 0 0
   - -1 -1 'sdhci@fe330000'
   - not found
fdtdec_get_addr_size_auto_parent: na=2, ns=2, fdtdec_get_addr_size_fixed: reg: addr=00000000x
ofnode_read_u32: bus-width: x (8)
clk_set_defaults(sdhci@fe330000)
clk_set_default_parents: could not read assigned-clock-parents for ff8ec0f8
ofnode_read_u32: max-frequency: x (200000000)
clk_get_by_indexed_prop(dev=ff8ec0f8, index=0, clk=7fcd8)
fdtdec_get_int: #clock-cells: x (1)
clk_of_xlate_default(clk=7fcd8)
clk_request(dev=ff8ee058, clk=7fcd8)
clk_set_rate(clk=7fcd8, rate=200000000)
clock is disabled (0Hz)
clock is enabled (400000Hz)
clock is enabled (25000000Hz)
clock is enabled (52000000Hz)
spl: mmc boot mode: raw
blk_find_device: if_type=6, devnum=0: [email protected], 6, 0
hdr read sector 4000, count=1
mkimage signature not found - ih_magic = 1400000a
blk_find_device: if_type=6, devnum=0: [email protected], 6, 0
read 190 sectors to 200000
Jumping to U-Boot
SPL malloc() used 0x2a8 bytes (0 KB)
loaded - jumping to U-Boot...
image entry point: 0x200000