// ------------------------------------------------------------------------- --
// Title         : DCF77-Decoder
// Project       : Praktikum FPGA-Entwurfstechnik
// ------------------------------------------------------------------------- --
// File          : timeAndDateClock.v
// Author        : Tim Stadtmann
// Company       : IDS RWTH Aachen
// Created       : 2018/09/20
// ------------------------------------------------------------------------- --
// Description   : Decodes the dcf77 signal
// ------------------------------------------------------------------------- --
// Revisions     :
// Date        Version  Author  Description
// 2018/09/20  1.0      TS      Created
// ------------------------------------------------------------------------- --

module dcf77_decoder(clk,             // Global 10MHz clock
                     clk_en_1hz,      // Indicates start of second
                     nReset,          // Global reset
                     minute_start_in, // New minute trigger
                     dcf_Signal_in,   // DFC Signal
                     timeAndDate_out,
                     data_valid,      // Control signal, High if data is valid
                     dcf_value,       // Decoded value of dcf input signal
                            LED_DEBUG_MIN,
                            LED_DEBUG_DATA,
                            LED_DEBUG_CLK_1,
                            LED_RECEIVING,
                            recv_buffer
                            );

input clk,
      clk_en_1hz,
      nReset,
      minute_start_in,
      dcf_Signal_in;

output reg[43:0]  timeAndDate_out;
output reg        data_valid;
output            dcf_value;

// ---------- YOUR CODE HERE ----------

output LED_DEBUG_MIN;
output LED_RECEIVING;
output reg LED_DEBUG_DATA;
output reg LED_DEBUG_CLK_1;

reg receiving;
reg [5:0] seconds_counter;
output reg [58:0] recv_buffer;
reg data_ok;

assign LED_DEBUG_MIN = minute_start_in;
assign LED_RECEIVING = receiving;

always @(posedge clk, negedge nReset) begin
    if(nReset == 0) begin
        receiving <= 0;
        seconds_counter <= 'b0;
        data_valid <= 0;
        timeAndDate_out <= 'b0;
        recv_buffer <= 'b0;
    end else begin

        if (minute_start_in == 1) begin
            receiving <= 1;
            seconds_counter <= 'b0;
            recv_buffer <= 'b0;

        end else if(seconds_counter == 6'd59) begin
            receiving <= 0;

            timeAndDate_out[6:0] <= 'b0; //seconds = 0

            timeAndDate_out[10:7 ] <= recv_buffer[24:21]; //minute LSD
            timeAndDate_out[13:11] <= recv_buffer[27:25]; //minute MSD

            timeAndDate_out[17:14] <= recv_buffer[32:29]; //hour LSD
            timeAndDate_out[19:18] <= recv_buffer[34:33]; //hour MSD

            timeAndDate_out[23:20] <= recv_buffer[39:36]; //day LSD
            timeAndDate_out[25:24] <= recv_buffer[41:40]; //day MSD

            timeAndDate_out[29:26] <= recv_buffer[48:45]; //month LSD
            timeAndDate_out[30   ] <= recv_buffer[49]; //month MSD

            timeAndDate_out[34:31] <= recv_buffer[53:50]; //year LSD
            timeAndDate_out[38:35] <= recv_buffer[57:54]; //year MSD

            timeAndDate_out[41:39] <= recv_buffer[44:42]; //weekday
            timeAndDate_out[43:42] <= recv_buffer[18:17]; // timezone & DST

            data_ok <= ( ~^recv_buffer[28:21] ) &&  ( ~^recv_buffer[35:29] ) && ( ~^recv_buffer[58:36] ); //parity bit check
            seconds_counter <= 'b0;

        end else if( (clk_en_1hz == 1) && (receiving == 1) ) begin

            LED_DEBUG_CLK_1 <= ~LED_DEBUG_CLK_1;
            LED_DEBUG_DATA <= ~dcf_Signal_in;
            recv_buffer[seconds_counter] <= ~dcf_Signal_in;
            seconds_counter <= seconds_counter + 1;

        end

        if(clk_en_1hz) begin
            if(data_ok) begin
                if(data_valid) begin
                    data_ok <= 0;
                    data_valid <= 0;
                end else begin
                    data_valid <= 1;
                end
            end
        end


    end

end


endmodule