test sim litex

from litex.tools.litex_sim import *

class TestSim(SimSoC):
    def __init__(self, host_ip="192.168.1.100", host_udp_port=2000):
        SimSoC.__init__(self,
            cpu_type              = None,
            integrated_rom_size   = 0x10000,
            uart_name             = "sim",
            with_sdram            = False,
            with_etherbone        = False,
            etherbone_mac_address = 0x10e2d5000001,
            etherbone_ip_address  = "192.168.1.50",
            sdram_module          = "MT48LC16M16",
            sdram_data_width      = 8,
            with_sdcard           = False,
        )
        from litex.build.sim import SimPlatform

        import numpy

        pileup_datamem = Memory(16, 2**15, name="test_data")

        self.specials += pileup_datamem
        pd_rp = pileup_datamem.get_port()

        counter = Signal(15, reset=0)

        self.sync += counter.eq(counter + 1)
        self.comb += [
            pd_rp.adr.eq(counter),
        ]


def main():
    from litex.soc.integration.soc import LiteXSoCArgumentParser
    parser = LiteXSoCArgumentParser(description="LiteX SoC Simulation utility")
    sim_args(parser)
    args = parser.parse_args()

    soc_kwargs             = soc_core_argdict(args)
    builder_kwargs         = builder_argdict(args)
    verilator_build_kwargs = verilator_build_argdict(args)

    sys_clk_freq = int(1e6)
    sim_config   = SimConfig()
    sim_config.add_clocker("sys_clk", freq_hz=sys_clk_freq)
    sim_config.add_module("serial2console", "serial")
    # sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": "192.168.1.100"})

    # SoC ------------------------------------------------------------------------------------------
    soc = TestSim()

    def pre_run_callback(vns):
        if args.trace:
            generate_gtkw_savefile(builder, vns, args.trace_fst)

    # Build/Run ------------------------------------------------------------------------------------
    builder = Builder(soc, csr_csv="csr.csv")
    builder.build(sim_config=sim_config,
                  interactive      = not args.non_interactive,
                  pre_run_callback = pre_run_callback,
                  **verilator_build_kwargs,
    )


if __name__ == "__main__":
    main()