library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity top is
   port(
      clk_50MHz : in  std_logic;
      res_o     : out std_logic_vector(31 downto 0)
   );
end entity top;
-------------------------------------------------------------------------------
architecture top_arch of top is
   constant LFSR_LENGTH : positive := (res_o'length - 2) / 2;

   ----------------------------------------------------------------------------
   signal clk_170MHz   : std_logic;
   signal new_operands : std_logic;

   -- signals for arithmetic operation
   signal a : std_logic_vector(LFSR_LENGTH - 1 downto 0);
   signal b : std_logic_vector(LFSR_LENGTH - 1 downto 0);
   signal c : std_logic_vector(LFSR_LENGTH - 1 downto 0);
   signal d : std_logic_vector(LFSR_LENGTH - 1 downto 0);

   signal ua : unsigned(LFSR_LENGTH - 1 downto 0);
   signal ub : unsigned(LFSR_LENGTH - 1 downto 0);
   signal uc : unsigned(LFSR_LENGTH - 1 downto 0);
   signal ud : unsigned(LFSR_LENGTH - 1 downto 0);


   -- results
   signal result_d : unsigned(res_o'range) := (others => '0');
   signal result   : unsigned(res_o'range) := (others => '0');

      signal res1 : unsigned(result_d'length - 3 downto 0) := (others => '0');
      signal res2 : unsigned(result_d'length - 3 downto 0) := (others => '0');
      signal res3 : unsigned(result_d'length - 3 downto 0) := (others => '0');
      signal res4 : unsigned(result_d'length - 3 downto 0) := (others => '0');
      signal subres1 : unsigned(result_d'length - 3 downto 0) := (others => '0');
      signal subres2 : unsigned(result_d'length - 3 downto 0) := (others => '0');


   ----------------------------------------------------------------------------

   component clk_gen
      port(
         clk_170 : out std_logic;
         clk_50  : in  std_logic
      );
   end component;

   ----------------------------------------------------------------------------
begin
   ----------------------------------------------------------------------------

   clk_gen_inst : clk_gen
      port map(
         clk_170 => clk_170MHz,
         clk_50  => clk_50MHz
      );

   new_operands_gen : entity work.ce_gen
      generic map(
         DIV_FACT => 8
      )
      port map(
         clk  => clk_170MHz,
         srst => '0',
         ce   => '1',
         ce_o => new_operands
      );

   ----------------------------------------------------------------------------
   -- random generators

   gen_A : entity work.lfsr_gen
      generic map(
         LFSR_LENGTH => LFSR_LENGTH,
         SEED        => 1
      )
      port map(
         clk    => clk_170MHz,
         ena_i  => new_operands,
         dout_o => a
      );

   gen_B : entity work.lfsr_gen
      generic map(
         LFSR_LENGTH => LFSR_LENGTH,
         SEED        => 2
      )
      port map(
         clk    => clk_170MHz,
         ena_i  => new_operands,
         dout_o => b
      );

   gen_C : entity work.lfsr_gen
      generic map(
         LFSR_LENGTH => LFSR_LENGTH,
         SEED        => 3
      )
      port map(
         clk    => clk_170MHz,
         ena_i  => new_operands,
         dout_o => c
      );

   gen_D : entity work.lfsr_gen
      generic map(
         LFSR_LENGTH => LFSR_LENGTH,
         SEED        => 5
      )
      port map(
         clk    => clk_170MHz,
         ena_i  => new_operands,
         dout_o => d
      );

   ----------------------------------------------------------------------------
   -- result output register
   calc_register : process(clk_170MHz) is
   begin
      if rising_edge(clk_170MHz) then
         result <= result_d;
      end if;
   end process calc_register;

   res_o <= std_logic_vector(result);

   --------------------------- MODIFY FOLLOWING -------------------------------

   -- result=(a*b)+(c*d)+(a*c)+(b*d)
    s_res : process(clk_170MHz) is

   begin
   if rising_edge(clk_170MHz) then

   ua<= unsigned(a);
   ub<= unsigned(b);
   uc<= unsigned(c);
   ud<= unsigned(d);

      res1     <= ua*ub;
      res2     <= uc*ud;
      res3     <= ua*uc;
      res4     <= ub*ud;

    subres1 <= res1+res2;
    subres2 <= res3+res4;

   end if;
       result_d <= to_unsigned(0, result_d'length)+ subres1;
    result_d <= to_unsigned(0, result_d'length) + subres2;
   end process s_res;

   ----------------------------------------------------------------------------

end architecture top_arch;
-------------------------------------------------------------------------------