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dtc

Nov 21st, 2021
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  1. [root@quartz64 policy0]# dtc -I fs /sys/firmware/devicetree/base
  2. <stdout>: Warning (unit_address_vs_reg): /memory: node has a reg or ranges property, but no unit name
  3. <stdout>: Warning (clocks_property): /i2c@fe5c0000:clocks: cell 0 is not a phandle reference
  4. <stdout>: Warning (clocks_property): /i2c@fe5c0000:clocks: cell 2 is not a phandle reference
  5. <stdout>: Warning (clocks_property): /gpu@fde60000:clocks: cell 0 is not a phandle reference
  6. <stdout>: Warning (clocks_property): /gpu@fde60000:clocks: cell 2 is not a phandle reference
  7. <stdout>: Warning (clocks_property): /spdif@fe460000:clocks: cell 0 is not a phandle reference
  8. <stdout>: Warning (clocks_property): /spdif@fe460000:clocks: cell 2 is not a phandle reference
  9. <stdout>: Warning (clocks_property): /pinctrl/gpio@fdd60000:clocks: cell 0 is not a phandle reference
  10. <stdout>: Warning (clocks_property): /pinctrl/gpio@fdd60000:clocks: cell 2 is not a phandle reference
  11. <stdout>: Warning (clocks_property): /pinctrl/gpio@fe770000:clocks: cell 0 is not a phandle reference
  12. <stdout>: Warning (clocks_property): /pinctrl/gpio@fe770000:clocks: cell 2 is not a phandle reference
  13. <stdout>: Warning (clocks_property): /pinctrl/gpio@fe740000:clocks: cell 0 is not a phandle reference
  14. <stdout>: Warning (clocks_property): /pinctrl/gpio@fe740000:clocks: cell 2 is not a phandle reference
  15. <stdout>: Warning (clocks_property): /pinctrl/gpio@fe750000:clocks: cell 0 is not a phandle reference
  16. <stdout>: Warning (clocks_property): /pinctrl/gpio@fe750000:clocks: cell 2 is not a phandle reference
  17. <stdout>: Warning (clocks_property): /pinctrl/gpio@fe760000:clocks: cell 0 is not a phandle reference
  18. <stdout>: Warning (clocks_property): /pinctrl/gpio@fe760000:clocks: cell 2 is not a phandle reference
  19. <stdout>: Warning (clocks_property): /mmc@fe2c0000:clocks: cell 0 is not a phandle reference
  20. <stdout>: Warning (clocks_property): /mmc@fe2c0000:clocks: cell 2 is not a phandle reference
  21. <stdout>: Warning (clocks_property): /mmc@fe2c0000:clocks: cell 4 is not a phandle reference
  22. <stdout>: Warning (clocks_property): /mmc@fe2c0000:clocks: cell 6 is not a phandle reference
  23. <stdout>: Warning (clocks_property): /serial@fe6a0000:clocks: cell 0 is not a phandle reference
  24. <stdout>: Warning (clocks_property): /serial@fe6a0000:clocks: cell 2 is not a phandle reference
  25. <stdout>: Warning (clocks_property): /watchdog@fe600000:clocks: cell 0 is not a phandle reference
  26. <stdout>: Warning (clocks_property): /watchdog@fe600000:clocks: cell 2 is not a phandle reference
  27. <stdout>: Warning (clocks_property): /tsadc@fe710000:clocks: cell 0 is not a phandle reference
  28. <stdout>: Warning (clocks_property): /tsadc@fe710000:clocks: cell 2 is not a phandle reference
  29. <stdout>: Warning (clocks_property): /mmc@fe000000:clocks: cell 0 is not a phandle reference
  30. <stdout>: Warning (clocks_property): /mmc@fe000000:clocks: cell 2 is not a phandle reference
  31. <stdout>: Warning (clocks_property): /mmc@fe000000:clocks: cell 4 is not a phandle reference
  32. <stdout>: Warning (clocks_property): /mmc@fe000000:clocks: cell 6 is not a phandle reference
  33. <stdout>: Warning (clocks_property): /serial@fe670000:clocks: cell 0 is not a phandle reference
  34. <stdout>: Warning (clocks_property): /serial@fe670000:clocks: cell 2 is not a phandle reference
  35. <stdout>: Warning (clocks_property): /usb2-phy@fe8a0000:clocks: cell 0 is not a phandle reference
  36. <stdout>: Warning (clocks_property): /ethernet@fe010000:clocks: cell 0 is not a phandle reference
  37. <stdout>: Warning (clocks_property): /ethernet@fe010000:clocks: cell 2 is not a phandle reference
  38. <stdout>: Warning (clocks_property): /ethernet@fe010000:clocks: cell 4 is not a phandle reference
  39. <stdout>: Warning (clocks_property): /ethernet@fe010000:clocks: cell 6 is not a phandle reference
  40. <stdout>: Warning (clocks_property): /ethernet@fe010000:clocks: cell 8 is not a phandle reference
  41. <stdout>: Warning (clocks_property): /ethernet@fe010000:clocks: cell 10 is not a phandle reference
  42. <stdout>: Warning (clocks_property): /ethernet@fe010000:clocks: cell 12 is not a phandle reference
  43. <stdout>: Warning (clocks_property): /ethernet@fe010000:clocks: cell 14 is not a phandle reference
  44. <stdout>: Warning (clocks_property): /i2c@fe5d0000:clocks: cell 0 is not a phandle reference
  45. <stdout>: Warning (clocks_property): /i2c@fe5d0000:clocks: cell 2 is not a phandle reference
  46. <stdout>: Warning (clocks_property): /dmac@fe530000:clocks: cell 0 is not a phandle reference
  47. <stdout>: Warning (clocks_property): /serial@fe6b0000:clocks: cell 0 is not a phandle reference
  48. <stdout>: Warning (clocks_property): /serial@fe6b0000:clocks: cell 2 is not a phandle reference
  49. <stdout>: Warning (clocks_property): /usb@fd800000:clocks: cell 0 is not a phandle reference
  50. <stdout>: Warning (clocks_property): /usb@fd800000:clocks: cell 2 is not a phandle reference
  51. <stdout>: Warning (clocks_property): /usb@fd800000:clocks: cell 4 is not a phandle reference
  52. <stdout>: Warning (clocks_property): /usb@fd840000:clocks: cell 0 is not a phandle reference
  53. <stdout>: Warning (clocks_property): /usb@fd840000:clocks: cell 2 is not a phandle reference
  54. <stdout>: Warning (clocks_property): /usb@fd840000:clocks: cell 4 is not a phandle reference
  55. <stdout>: Warning (clocks_property): /hdmi@fe0a0000:clocks: cell 0 is not a phandle reference
  56. <stdout>: Warning (clocks_property): /hdmi@fe0a0000:clocks: cell 2 is not a phandle reference
  57. <stdout>: Warning (clocks_property): /hdmi@fe0a0000:clocks: cell 4 is not a phandle reference
  58. <stdout>: Warning (clocks_property): /hdmi@fe0a0000:clocks: cell 6 is not a phandle reference
  59. <stdout>: Warning (clocks_property): /power-management@fdd90000/power-controller/power-domain@9:clocks: cell 0 is not a phandle reference
  60. <stdout>: Warning (clocks_property): /power-management@fdd90000/power-controller/power-domain@9:clocks: cell 2 is not a phandle reference
  61. <stdout>: Warning (clocks_property): /power-management@fdd90000/power-controller/power-domain@9:clocks: cell 4 is not a phandle reference
  62. <stdout>: Warning (clocks_property): /power-management@fdd90000/power-controller/power-domain@7:clocks: cell 0 is not a phandle reference
  63. <stdout>: Warning (clocks_property): /power-management@fdd90000/power-controller/power-domain@7:clocks: cell 2 is not a phandle reference
  64. <stdout>: Warning (clocks_property): /power-management@fdd90000/power-controller/power-domain@15:clocks: cell 0 is not a phandle reference
  65. <stdout>: Warning (clocks_property): /power-management@fdd90000/power-controller/power-domain@13:clocks: cell 0 is not a phandle reference
  66. <stdout>: Warning (clocks_property): /power-management@fdd90000/power-controller/power-domain@11:clocks: cell 0 is not a phandle reference
  67. <stdout>: Warning (clocks_property): /power-management@fdd90000/power-controller/power-domain@8:clocks: cell 0 is not a phandle reference
  68. <stdout>: Warning (clocks_property): /power-management@fdd90000/power-controller/power-domain@8:clocks: cell 2 is not a phandle reference
  69. <stdout>: Warning (clocks_property): /power-management@fdd90000/power-controller/power-domain@14:clocks: cell 0 is not a phandle reference
  70. <stdout>: Warning (clocks_property): /power-management@fdd90000/power-controller/power-domain@10:clocks: cell 0 is not a phandle reference
  71. <stdout>: Warning (clocks_property): /power-management@fdd90000/power-controller/power-domain@10:clocks: cell 2 is not a phandle reference
  72. <stdout>: Warning (clocks_property): /serial@fe680000:clocks: cell 0 is not a phandle reference
  73. <stdout>: Warning (clocks_property): /serial@fe680000:clocks: cell 2 is not a phandle reference
  74. <stdout>: Warning (clocks_property): /usb@fd880000:clocks: cell 0 is not a phandle reference
  75. <stdout>: Warning (clocks_property): /usb@fd880000:clocks: cell 2 is not a phandle reference
  76. <stdout>: Warning (clocks_property): /usb@fd880000:clocks: cell 4 is not a phandle reference
  77. <stdout>: Warning (clocks_property): /saradc@fe720000:clocks: cell 0 is not a phandle reference
  78. <stdout>: Warning (clocks_property): /saradc@fe720000:clocks: cell 2 is not a phandle reference
  79. <stdout>: Warning (clocks_property): /usb2-phy@fe8b0000:clocks: cell 0 is not a phandle reference
  80. <stdout>: Warning (clocks_property): /i2c@fe5a0000:clocks: cell 0 is not a phandle reference
  81. <stdout>: Warning (clocks_property): /i2c@fe5a0000:clocks: cell 2 is not a phandle reference
  82. <stdout>: Warning (clocks_property): /i2c@fe5e0000:clocks: cell 0 is not a phandle reference
  83. <stdout>: Warning (clocks_property): /i2c@fe5e0000:clocks: cell 2 is not a phandle reference
  84. <stdout>: Warning (clocks_property): /i2s@fe410000:clocks: cell 0 is not a phandle reference
  85. <stdout>: Warning (clocks_property): /i2s@fe410000:clocks: cell 2 is not a phandle reference
  86. <stdout>: Warning (clocks_property): /i2s@fe410000:clocks: cell 4 is not a phandle reference
  87. <stdout>: Warning (clocks_property): /pwm@fe6e0030:clocks: cell 0 is not a phandle reference
  88. <stdout>: Warning (clocks_property): /pwm@fe6e0030:clocks: cell 2 is not a phandle reference
  89. <stdout>: Warning (clocks_property): /serial@fe6c0000:clocks: cell 0 is not a phandle reference
  90. <stdout>: Warning (clocks_property): /serial@fe6c0000:clocks: cell 2 is not a phandle reference
  91. <stdout>: Warning (clocks_property): /usb@fd8c0000:clocks: cell 0 is not a phandle reference
  92. <stdout>: Warning (clocks_property): /usb@fd8c0000:clocks: cell 2 is not a phandle reference
  93. <stdout>: Warning (clocks_property): /usb@fd8c0000:clocks: cell 4 is not a phandle reference
  94. <stdout>: Warning (clocks_property): /pwm@fe6e0020:clocks: cell 0 is not a phandle reference
  95. <stdout>: Warning (clocks_property): /pwm@fe6e0020:clocks: cell 2 is not a phandle reference
  96. <stdout>: Warning (clocks_property): /pwm@fe6e0010:clocks: cell 0 is not a phandle reference
  97. <stdout>: Warning (clocks_property): /pwm@fe6e0010:clocks: cell 2 is not a phandle reference
  98. <stdout>: Warning (clocks_property): /serial@fe650000:clocks: cell 0 is not a phandle reference
  99. <stdout>: Warning (clocks_property): /serial@fe650000:clocks: cell 2 is not a phandle reference
  100. <stdout>: Warning (clocks_property): /serial@fe650000/bluetooth:clocks: cell 0 is not a phandle reference
  101. <stdout>: Warning (clocks_property): /pwm@fe6e0000:clocks: cell 0 is not a phandle reference
  102. <stdout>: Warning (clocks_property): /pwm@fe6e0000:clocks: cell 2 is not a phandle reference
  103. <stdout>: Warning (clocks_property): /pwm@fe700030:clocks: cell 0 is not a phandle reference
  104. <stdout>: Warning (clocks_property): /pwm@fe700030:clocks: cell 2 is not a phandle reference
  105. <stdout>: Warning (clocks_property): /serial@fe690000:clocks: cell 0 is not a phandle reference
  106. <stdout>: Warning (clocks_property): /serial@fe690000:clocks: cell 2 is not a phandle reference
  107. <stdout>: Warning (clocks_property): /i2c@fdd40000:clocks: cell 0 is not a phandle reference
  108. <stdout>: Warning (clocks_property): /i2c@fdd40000:clocks: cell 2 is not a phandle reference
  109. <stdout>: Warning (clocks_property): /i2c@fdd40000/pmic@20:clocks: cell 0 is not a phandle reference
  110. <stdout>: Warning (clocks_property): /pwm@fdd70030:clocks: cell 0 is not a phandle reference
  111. <stdout>: Warning (clocks_property): /pwm@fdd70030:clocks: cell 2 is not a phandle reference
  112. <stdout>: Warning (clocks_property): /serial@fdd50000:clocks: cell 0 is not a phandle reference
  113. <stdout>: Warning (clocks_property): /serial@fdd50000:clocks: cell 2 is not a phandle reference
  114. <stdout>: Warning (clocks_property): /pwm@fe700020:clocks: cell 0 is not a phandle reference
  115. <stdout>: Warning (clocks_property): /pwm@fe700020:clocks: cell 2 is not a phandle reference
  116. <stdout>: Warning (clocks_property): /pwm@fdd70020:clocks: cell 0 is not a phandle reference
  117. <stdout>: Warning (clocks_property): /pwm@fdd70020:clocks: cell 2 is not a phandle reference
  118. <stdout>: Warning (clocks_property): /pwm@fe700010:clocks: cell 0 is not a phandle reference
  119. <stdout>: Warning (clocks_property): /pwm@fe700010:clocks: cell 2 is not a phandle reference
  120. <stdout>: Warning (clocks_property): /i2c@fe5b0000:clocks: cell 0 is not a phandle reference
  121. <stdout>: Warning (clocks_property): /i2c@fe5b0000:clocks: cell 2 is not a phandle reference
  122. <stdout>: Warning (clocks_property): /pwm@fdd70010:clocks: cell 0 is not a phandle reference
  123. <stdout>: Warning (clocks_property): /pwm@fdd70010:clocks: cell 2 is not a phandle reference
  124. <stdout>: Warning (clocks_property): /pwm@fe700000:clocks: cell 0 is not a phandle reference
  125. <stdout>: Warning (clocks_property): /pwm@fe700000:clocks: cell 2 is not a phandle reference
  126. <stdout>: Warning (clocks_property): /pwm@fdd70000:clocks: cell 0 is not a phandle reference
  127. <stdout>: Warning (clocks_property): /pwm@fdd70000:clocks: cell 2 is not a phandle reference
  128. <stdout>: Warning (clocks_property): /mmc@fe2b0000:clocks: cell 0 is not a phandle reference
  129. <stdout>: Warning (clocks_property): /mmc@fe2b0000:clocks: cell 2 is not a phandle reference
  130. <stdout>: Warning (clocks_property): /mmc@fe2b0000:clocks: cell 4 is not a phandle reference
  131. <stdout>: Warning (clocks_property): /mmc@fe2b0000:clocks: cell 6 is not a phandle reference
  132. <stdout>: Warning (clocks_property): /dmac@fe550000:clocks: cell 0 is not a phandle reference
  133. <stdout>: Warning (clocks_property): /cpus/cpu@0:clocks: cell 0 is not a phandle reference
  134. <stdout>: Warning (clocks_property): /pwm@fe6f0030:clocks: cell 0 is not a phandle reference
  135. <stdout>: Warning (clocks_property): /pwm@fe6f0030:clocks: cell 2 is not a phandle reference
  136. <stdout>: Warning (clocks_property): /serial@fe6d0000:clocks: cell 0 is not a phandle reference
  137. <stdout>: Warning (clocks_property): /serial@fe6d0000:clocks: cell 2 is not a phandle reference
  138. <stdout>: Warning (clocks_property): /iommu@fe043e00:clocks: cell 0 is not a phandle reference
  139. <stdout>: Warning (clocks_property): /iommu@fe043e00:clocks: cell 2 is not a phandle reference
  140. <stdout>: Warning (clocks_property): /pwm@fe6f0020:clocks: cell 0 is not a phandle reference
  141. <stdout>: Warning (clocks_property): /pwm@fe6f0020:clocks: cell 2 is not a phandle reference
  142. <stdout>: Warning (clocks_property): /pwm@fe6f0010:clocks: cell 0 is not a phandle reference
  143. <stdout>: Warning (clocks_property): /pwm@fe6f0010:clocks: cell 2 is not a phandle reference
  144. <stdout>: Warning (clocks_property): /vop@fe040000:clocks: cell 0 is not a phandle reference
  145. <stdout>: Warning (clocks_property): /vop@fe040000:clocks: cell 2 is not a phandle reference
  146. <stdout>: Warning (clocks_property): /vop@fe040000:clocks: cell 4 is not a phandle reference
  147. <stdout>: Warning (clocks_property): /vop@fe040000:clocks: cell 6 is not a phandle reference
  148. <stdout>: Warning (clocks_property): /vop@fe040000:clocks: cell 8 is not a phandle reference
  149. <stdout>: Warning (clocks_property): /serial@fe660000:clocks: cell 0 is not a phandle reference
  150. <stdout>: Warning (clocks_property): /serial@fe660000:clocks: cell 2 is not a phandle reference
  151. <stdout>: Warning (clocks_property): /pwm@fe6f0000:clocks: cell 0 is not a phandle reference
  152. <stdout>: Warning (clocks_property): /pwm@fe6f0000:clocks: cell 2 is not a phandle reference
  153. <stdout>: Warning (clocks_property): /mmc@fe310000:clocks: cell 0 is not a phandle reference
  154. <stdout>: Warning (clocks_property): /mmc@fe310000:clocks: cell 2 is not a phandle reference
  155. <stdout>: Warning (clocks_property): /mmc@fe310000:clocks: cell 4 is not a phandle reference
  156. <stdout>: Warning (clocks_property): /mmc@fe310000:clocks: cell 6 is not a phandle reference
  157. <stdout>: Warning (clocks_property): /mmc@fe310000:clocks: cell 8 is not a phandle reference
  158. <stdout>: Warning (cooling_device_property): /thermal-zones/cpu-thermal/cooling-maps/map0:cooling-device: cell 0 is not a phandle reference
  159. <stdout>: Warning (cooling_device_property): /thermal-zones/cpu-thermal/cooling-maps/map0:cooling-device: cell 3 is not a phandle reference
  160. <stdout>: Warning (cooling_device_property): /thermal-zones/cpu-thermal/cooling-maps/map0:cooling-device: cell 6 is not a phandle reference
  161. <stdout>: Warning (cooling_device_property): /thermal-zones/cpu-thermal/cooling-maps/map0:cooling-device: cell 9 is not a phandle reference
  162. <stdout>: Warning (cooling_device_property): /thermal-zones/cpu-thermal/cooling-maps/map1:cooling-device: cell 0 is not a phandle reference
  163. <stdout>: Warning (dmas_property): /spdif@fe460000:dmas: cell 0 is not a phandle reference
  164. <stdout>: Warning (dmas_property): /serial@fe6a0000:dmas: cell 0 is not a phandle reference
  165. <stdout>: Warning (dmas_property): /serial@fe6a0000:dmas: cell 2 is not a phandle reference
  166. <stdout>: Warning (dmas_property): /serial@fe670000:dmas: cell 0 is not a phandle reference
  167. <stdout>: Warning (dmas_property): /serial@fe670000:dmas: cell 2 is not a phandle reference
  168. <stdout>: Warning (dmas_property): /serial@fe6b0000:dmas: cell 0 is not a phandle reference
  169. <stdout>: Warning (dmas_property): /serial@fe6b0000:dmas: cell 2 is not a phandle reference
  170. <stdout>: Warning (dmas_property): /serial@fe680000:dmas: cell 0 is not a phandle reference
  171. <stdout>: Warning (dmas_property): /serial@fe680000:dmas: cell 2 is not a phandle reference
  172. <stdout>: Warning (dmas_property): /i2s@fe410000:dmas: cell 0 is not a phandle reference
  173. <stdout>: Warning (dmas_property): /i2s@fe410000:dmas: cell 2 is not a phandle reference
  174. <stdout>: Warning (dmas_property): /serial@fe6c0000:dmas: cell 0 is not a phandle reference
  175. <stdout>: Warning (dmas_property): /serial@fe6c0000:dmas: cell 2 is not a phandle reference
  176. <stdout>: Warning (dmas_property): /serial@fe650000:dmas: cell 0 is not a phandle reference
  177. <stdout>: Warning (dmas_property): /serial@fe650000:dmas: cell 2 is not a phandle reference
  178. <stdout>: Warning (dmas_property): /serial@fe690000:dmas: cell 0 is not a phandle reference
  179. <stdout>: Warning (dmas_property): /serial@fe690000:dmas: cell 2 is not a phandle reference
  180. <stdout>: Warning (dmas_property): /serial@fdd50000:dmas: cell 0 is not a phandle reference
  181. <stdout>: Warning (dmas_property): /serial@fdd50000:dmas: cell 2 is not a phandle reference
  182. <stdout>: Warning (dmas_property): /serial@fe6d0000:dmas: cell 0 is not a phandle reference
  183. <stdout>: Warning (dmas_property): /serial@fe6d0000:dmas: cell 2 is not a phandle reference
  184. <stdout>: Warning (dmas_property): /serial@fe660000:dmas: cell 0 is not a phandle reference
  185. <stdout>: Warning (dmas_property): /serial@fe660000:dmas: cell 2 is not a phandle reference
  186. <stdout>: Warning (iommus_property): /vop@fe040000:iommus: cell 0 is not a phandle reference
  187. <stdout>: Warning (phys_property): /usb@fd800000:phys: cell 0 is not a phandle reference
  188. <stdout>: Warning (phys_property): /usb@fd840000:phys: cell 0 is not a phandle reference
  189. <stdout>: Warning (phys_property): /usb@fd880000:phys: cell 0 is not a phandle reference
  190. <stdout>: Warning (phys_property): /usb@fd8c0000:phys: cell 0 is not a phandle reference
  191. <stdout>: Warning (power_domains_property): /gpu@fde60000:power-domains: cell 0 is not a phandle reference
  192. <stdout>: Warning (power_domains_property): /hdmi@fe0a0000:power-domains: cell 0 is not a phandle reference
  193. <stdout>: Warning (power_domains_property): /vop@fe040000:power-domains: cell 0 is not a phandle reference
  194. <stdout>: Warning (resets_property): /mmc@fe2c0000:resets: cell 0 is not a phandle reference
  195. <stdout>: Warning (resets_property): /tsadc@fe710000:resets: cell 0 is not a phandle reference
  196. <stdout>: Warning (resets_property): /tsadc@fe710000:resets: cell 2 is not a phandle reference
  197. <stdout>: Warning (resets_property): /tsadc@fe710000:resets: cell 4 is not a phandle reference
  198. <stdout>: Warning (resets_property): /mmc@fe000000:resets: cell 0 is not a phandle reference
  199. <stdout>: Warning (resets_property): /ethernet@fe010000:resets: cell 0 is not a phandle reference
  200. <stdout>: Warning (resets_property): /saradc@fe720000:resets: cell 0 is not a phandle reference
  201. <stdout>: Warning (resets_property): /i2s@fe410000:resets: cell 0 is not a phandle reference
  202. <stdout>: Warning (resets_property): /i2s@fe410000:resets: cell 2 is not a phandle reference
  203. <stdout>: Warning (resets_property): /mmc@fe2b0000:resets: cell 0 is not a phandle reference
  204. <stdout>: Warning (sound_dai_property): /rk817-sound/simple-audio-card,cpu:sound-dai: cell 0 is not a phandle reference
  205. <stdout>: Warning (sound_dai_property): /rk817-sound/simple-audio-card,codec:sound-dai: cell 0 is not a phandle reference
  206. <stdout>: Warning (sound_dai_property): /spdif-sound/simple-audio-card,cpu:sound-dai: cell 0 is not a phandle reference
  207. <stdout>: Warning (sound_dai_property): /spdif-sound/simple-audio-card,codec:sound-dai: cell 0 is not a phandle reference
  208. <stdout>: Warning (thermal_sensors_property): /thermal-zones/cpu-thermal:thermal-sensors: cell 0 is not a phandle reference
  209. <stdout>: Warning (thermal_sensors_property): /thermal-zones/gpu-thermal:thermal-sensors: cell 0 is not a phandle reference
  210. <stdout>: Warning (gpios_property): /ethernet@fe010000:snps,reset-gpio: cell 0 is not a phandle reference
  211. <stdout>: Warning (gpios_property): /vcc3v3_sd:gpio: cell 0 is not a phandle reference
  212. <stdout>: Warning (gpios_property): /leds/led-diy:gpios: cell 0 is not a phandle reference
  213. <stdout>: Warning (gpios_property): /leds/led-work:gpios: cell 0 is not a phandle reference
  214. <stdout>: Warning (gpios_property): /vcc5v0_usb20_host:gpio: cell 0 is not a phandle reference
  215. <stdout>: Warning (gpios_property): /gpio_fan:gpios: cell 0 is not a phandle reference
  216. <stdout>: Warning (gpios_property): /serial@fe650000/bluetooth:device-wake-gpios: cell 0 is not a phandle reference
  217. <stdout>: Warning (gpios_property): /serial@fe650000/bluetooth:host-wake-gpios: cell 0 is not a phandle reference
  218. <stdout>: Warning (gpios_property): /serial@fe650000/bluetooth:shutdown-gpios: cell 0 is not a phandle reference
  219. <stdout>: Warning (gpios_property): /mmc@fe2b0000:cd-gpios: cell 0 is not a phandle reference
  220. <stdout>: Warning (interrupt_provider): /pinctrl/gpio@fdd60000: Missing #address-cells in interrupt provider
  221. <stdout>: Warning (interrupt_provider): /pinctrl/gpio@fe770000: Missing #address-cells in interrupt provider
  222. <stdout>: Warning (interrupt_provider): /pinctrl/gpio@fe740000: Missing #address-cells in interrupt provider
  223. <stdout>: Warning (interrupt_provider): /pinctrl/gpio@fe750000: Missing #address-cells in interrupt provider
  224. <stdout>: Warning (interrupt_provider): /pinctrl/gpio@fe760000: Missing #address-cells in interrupt provider
  225. <stdout>: Warning (interrupt_provider): /interrupt-controller@fd400000: Missing #address-cells in interrupt provider
  226. <stdout>: Warning (graph_child_address): /hdmi@fe0a0000/ports: graph node has single child node 'port@0', #address-cells/#size-cells are not necessary
  227. <stdout>: Warning (graph_child_address): /vop@fe040000/ports/port@0: graph node has single child node 'endpoint@0', #address-cells/#size-cells are not necessary
  228. <stdout>: Warning (graph_child_address): /vop@fe040000/ports/port@1: graph node has single child node 'endpoint@0', #address-cells/#size-cells are not necessary
  229. <stdout>: Warning (graph_child_address): /vop@fe040000/ports/port@2: graph node has single child node 'endpoint@0', #address-cells/#size-cells are not necessary
  230. /dts-v1/;
  231.  
  232. / {
  233. #address-cells = <0x02>;
  234. model = "Pine64 RK3566 Quartz64-A Board";
  235. #size-cells = <0x02>;
  236. interrupt-parent = <0x01>;
  237. compatible = "pine64,quartz64-a\0rockchip,rk3566";
  238.  
  239. qos@fe158300 {
  240. compatible = "rockchip,rk3568-qos\0syscon";
  241. reg = <0x00 0xfe158300 0x00 0x20>;
  242. phandle = <0x28>;
  243. };
  244.  
  245. syscon@fdc20000 {
  246. compatible = "rockchip,rk3568-pmugrf\0syscon\0simple-mfd";
  247. reg = <0x00 0xfdc20000 0x00 0x10000>;
  248. phandle = <0x85>;
  249.  
  250. io-domains {
  251. compatible = "rockchip,rk3568-pmu-io-voltage-domain";
  252. status = "disabled";
  253. phandle = <0xa1>;
  254. };
  255. };
  256.  
  257. i2c@fe5c0000 {
  258. pinctrl-names = "default";
  259. #address-cells = <0x01>;
  260. pinctrl-0 = <0x5d>;
  261. clock-names = "i2c\0pclk";
  262. interrupts = <0x00 0x31 0x04>;
  263. clocks = <0x0b 0x14c 0x0b 0x14b>;
  264. #size-cells = <0x00>;
  265. compatible = "rockchip,rk3568-i2c\0rockchip,rk3399-i2c";
  266. status = "disabled";
  267. reg = <0x00 0xfe5c0000 0x00 0x1000>;
  268. phandle = <0xc2>;
  269. };
  270.  
  271. gpu@fde60000 {
  272. power-domains = <0x34 0x07>;
  273. mali-supply = <0x35>;
  274. clock-names = "core\0bus";
  275. interrupts = <0x00 0x28 0x04 0x00 0x29 0x04 0x00 0x27 0x04>;
  276. clocks = <0x02 0x01 0x0b 0x1b>;
  277. compatible = "rockchip,rk3568-mali\0arm,mali-bifrost";
  278. status = "okay";
  279. interrupt-names = "job\0mmu\0gpu";
  280. reg = <0x00 0xfde60000 0x00 0x4000>;
  281. phandle = <0xb1>;
  282. operating-points-v2 = <0x33>;
  283. #cooling-cells = <0x02>;
  284. };
  285.  
  286. spdif@fe460000 {
  287. pinctrl-names = "default";
  288. pinctrl-0 = <0x56>;
  289. clock-names = "mclk\0hclk";
  290. interrupts = <0x00 0x66 0x04>;
  291. clocks = <0x0b 0x5f 0x0b 0x5c>;
  292. dma-names = "tx";
  293. #sound-dai-cells = <0x00>;
  294. compatible = "rockchip,rk3568-spdif";
  295. status = "okay";
  296. reg = <0x00 0xfe460000 0x00 0x1000>;
  297. phandle = <0x92>;
  298. dmas = <0x55 0x01>;
  299. };
  300.  
  301. qos@fe1a8100 {
  302. compatible = "rockchip,rk3568-qos\0syscon";
  303. reg = <0x00 0xfe1a8100 0x00 0x20>;
  304. phandle = <0x22>;
  305. };
  306.  
  307. syscon@fdc60000 {
  308. compatible = "rockchip,rk3568-grf\0syscon\0simple-mfd";
  309. reg = <0x00 0xfdc60000 0x00 0x10000>;
  310. phandle = <0x0f>;
  311. };
  312.  
  313. pinctrl {
  314. #address-cells = <0x02>;
  315. #size-cells = <0x02>;
  316. compatible = "rockchip,rk3568-pinctrl";
  317. rockchip,pmu = <0x85>;
  318. ranges;
  319. rockchip,grf = <0x0f>;
  320. phandle = <0xe5>;
  321.  
  322. eth0 {
  323.  
  324. eth0-pins {
  325. rockchip,pins = <0x02 0x11 0x02 0x86>;
  326. phandle = <0x13a>;
  327. };
  328. };
  329.  
  330. i2c3 {
  331.  
  332. i2c3m1-xfer {
  333. rockchip,pins = <0x03 0x0d 0x04 0x8b 0x03 0x0e 0x04 0x8b>;
  334. phandle = <0x152>;
  335. };
  336.  
  337. i2c3m0-xfer {
  338. rockchip,pins = <0x01 0x01 0x01 0x8b 0x01 0x00 0x01 0x8b>;
  339. phandle = <0x5d>;
  340. };
  341. };
  342.  
  343. pwm9 {
  344.  
  345. pwm9m1-pins {
  346. rockchip,pins = <0x01 0x1e 0x04 0x86>;
  347. phandle = <0x1b7>;
  348. };
  349.  
  350. pwm9m0-pins {
  351. rockchip,pins = <0x03 0x0a 0x05 0x86>;
  352. phandle = <0x7b>;
  353. };
  354. };
  355.  
  356. pcfg-pull-none-drv-level-7 {
  357. drive-strength = <0x07>;
  358. bias-disable;
  359. phandle = <0xec>;
  360. };
  361.  
  362. pwm14 {
  363.  
  364. pwm14m1-pins {
  365. rockchip,pins = <0x04 0x12 0x01 0x86>;
  366. phandle = <0x1bc>;
  367. };
  368.  
  369. pwm14m0-pins {
  370. rockchip,pins = <0x03 0x14 0x01 0x86>;
  371. phandle = <0x80>;
  372. };
  373. };
  374.  
  375. npu {
  376.  
  377. npu-pins {
  378. rockchip,pins = <0x00 0x11 0x02 0x86>;
  379. phandle = <0x193>;
  380. };
  381. };
  382.  
  383. pcie30x1 {
  384.  
  385. pcie30x1m1-pins {
  386. rockchip,pins = <0x02 0x1a 0x04 0x86 0x03 0x01 0x04 0x86 0x02 0x1b 0x04 0x86>;
  387. phandle = <0x199>;
  388. };
  389.  
  390. pcie30x1m0-pins {
  391. rockchip,pins = <0x00 0x04 0x03 0x86 0x00 0x13 0x03 0x86 0x00 0x12 0x03 0x86>;
  392. phandle = <0x198>;
  393. };
  394.  
  395. pcie30x1-buttonrstn {
  396. rockchip,pins = <0x00 0x0b 0x03 0x86>;
  397. phandle = <0x19b>;
  398. };
  399.  
  400. pcie30x1m2-pins {
  401. rockchip,pins = <0x01 0x05 0x04 0x86 0x01 0x02 0x04 0x86 0x01 0x03 0x04 0x86>;
  402. phandle = <0x19a>;
  403. };
  404. };
  405.  
  406. gpio@fdd60000 {
  407. gpio-controller;
  408. interrupts = <0x00 0x21 0x04>;
  409. clocks = <0x0e 0x2e 0x0e 0x0c>;
  410. compatible = "rockchip,gpio-bank";
  411. #interrupt-cells = <0x02>;
  412. reg = <0x00 0xfdd60000 0x00 0x100>;
  413. phandle = <0x12>;
  414. #gpio-cells = <0x02>;
  415. interrupt-controller;
  416. };
  417.  
  418. uart8 {
  419.  
  420. uart8m0-rtsn {
  421. rockchip,pins = <0x02 0x09 0x03 0x86>;
  422. phandle = <0x206>;
  423. };
  424.  
  425. uart8m0-ctsn {
  426. rockchip,pins = <0x02 0x0a 0x03 0x86>;
  427. phandle = <0x205>;
  428. };
  429.  
  430. uart8m1-xfer {
  431. rockchip,pins = <0x03 0x00 0x04 0x88 0x02 0x1f 0x04 0x88>;
  432. phandle = <0x207>;
  433. };
  434.  
  435. uart8m0-xfer {
  436. rockchip,pins = <0x02 0x16 0x02 0x88 0x02 0x15 0x03 0x88>;
  437. phandle = <0x6e>;
  438. };
  439. };
  440.  
  441. gmac-txc-level2 {
  442.  
  443. gmac0-rgmii-clk-level2 {
  444. rockchip,pins = <0x02 0x05 0x02 0x86 0x02 0x08 0x02 0x89>;
  445. phandle = <0x22a>;
  446. };
  447.  
  448. gmac1m1-rgmii-clk-level2 {
  449. rockchip,pins = <0x04 0x03 0x03 0x86 0x04 0x00 0x03 0x89>;
  450. phandle = <0x22c>;
  451. };
  452.  
  453. gmac1m0-rgmii-clk-level2 {
  454. rockchip,pins = <0x03 0x07 0x03 0x86 0x03 0x06 0x03 0x89>;
  455. phandle = <0x22b>;
  456. };
  457. };
  458.  
  459. spi2 {
  460.  
  461. spi2m0-cs1 {
  462. rockchip,pins = <0x02 0x15 0x04 0x86>;
  463. phandle = <0x1e2>;
  464. };
  465.  
  466. spi2m1-cs1 {
  467. rockchip,pins = <0x02 0x1c 0x03 0x86>;
  468. phandle = <0x1e5>;
  469. };
  470.  
  471. spi2m1-pins {
  472. rockchip,pins = <0x03 0x00 0x03 0x86 0x02 0x1f 0x03 0x86 0x02 0x1e 0x03 0x86>;
  473. phandle = <0x1e3>;
  474. };
  475.  
  476. spi2m0-cs0 {
  477. rockchip,pins = <0x02 0x14 0x04 0x86>;
  478. phandle = <0x1e1>;
  479. };
  480.  
  481. spi2m0-pins {
  482. rockchip,pins = <0x02 0x11 0x04 0x86 0x02 0x12 0x04 0x86 0x02 0x13 0x04 0x86>;
  483. phandle = <0x1e0>;
  484. };
  485.  
  486. spi2m1-cs0 {
  487. rockchip,pins = <0x02 0x1d 0x03 0x86>;
  488. phandle = <0x1e4>;
  489. };
  490. };
  491.  
  492. pcfg-pull-up-drv-level-15 {
  493. drive-strength = <0x0f>;
  494. phandle = <0x102>;
  495. bias-pull-up;
  496. };
  497.  
  498. pcfg-pull-down-drv-level-13 {
  499. drive-strength = <0x0d>;
  500. bias-pull-down;
  501. phandle = <0x110>;
  502. };
  503.  
  504. pcfg-pull-up-drv-level-2 {
  505. drive-strength = <0x02>;
  506. phandle = <0x87>;
  507. bias-pull-up;
  508. };
  509.  
  510. i2s1 {
  511.  
  512. i2s1m0-sdo1 {
  513. rockchip,pins = <0x01 0x08 0x01 0x86>;
  514. phandle = <0x15a>;
  515. };
  516.  
  517. i2s1m0-lrcktx {
  518. rockchip,pins = <0x01 0x05 0x01 0x86>;
  519. phandle = <0x58>;
  520. };
  521.  
  522. i2s1m1-sdi1 {
  523. rockchip,pins = <0x03 0x1b 0x04 0x86>;
  524. phandle = <0x163>;
  525. };
  526.  
  527. i2s1m1-lrcktx {
  528. rockchip,pins = <0x03 0x18 0x04 0x86>;
  529. phandle = <0x15e>;
  530. };
  531.  
  532. i2s1m0-lrckrx {
  533. rockchip,pins = <0x01 0x06 0x01 0x86>;
  534. phandle = <0x155>;
  535. };
  536.  
  537. i2s1m0-sdi3 {
  538. rockchip,pins = <0x01 0x08 0x02 0x86>;
  539. phandle = <0x159>;
  540. };
  541.  
  542. i2s1m2-lrcktx {
  543. rockchip,pins = <0x02 0x1a 0x05 0x86>;
  544. phandle = <0x16b>;
  545. };
  546.  
  547. i2s1m1-lrckrx {
  548. rockchip,pins = <0x04 0x07 0x05 0x86>;
  549. phandle = <0x15d>;
  550. };
  551.  
  552. i2s1m0-mclk {
  553. rockchip,pins = <0x01 0x02 0x01 0x86>;
  554. phandle = <0x14>;
  555. };
  556.  
  557. i2s1m0-sclktx {
  558. rockchip,pins = <0x01 0x03 0x01 0x86>;
  559. phandle = <0x57>;
  560. };
  561.  
  562. i2s1m2-sdo2 {
  563. rockchip,pins = <0x03 0x11 0x05 0x86>;
  564. phandle = <0x175>;
  565. };
  566.  
  567. i2s1m2-lrckrx {
  568. rockchip,pins = <0x03 0x15 0x05 0x86>;
  569. phandle = <0x16a>;
  570. };
  571.  
  572. i2s1m0-sdi1 {
  573. rockchip,pins = <0x01 0x0a 0x02 0x86>;
  574. phandle = <0x157>;
  575. };
  576.  
  577. i2s1m1-sclktx {
  578. rockchip,pins = <0x03 0x17 0x04 0x86>;
  579. phandle = <0x161>;
  580. };
  581.  
  582. i2s1m0-sclkrx {
  583. rockchip,pins = <0x01 0x04 0x01 0x86>;
  584. phandle = <0x156>;
  585. };
  586.  
  587. i2s1m2-sclktx {
  588. rockchip,pins = <0x02 0x19 0x05 0x86>;
  589. phandle = <0x16e>;
  590. };
  591.  
  592. i2s1m2-sdo0 {
  593. rockchip,pins = <0x02 0x1f 0x05 0x86>;
  594. phandle = <0x173>;
  595. };
  596.  
  597. i2s1m1-sclkrx {
  598. rockchip,pins = <0x04 0x06 0x05 0x86>;
  599. phandle = <0x160>;
  600. };
  601.  
  602. i2s1m2-sclkrx {
  603. rockchip,pins = <0x03 0x13 0x05 0x86>;
  604. phandle = <0x16d>;
  605. };
  606.  
  607. i2s1m1-sdo2 {
  608. rockchip,pins = <0x04 0x09 0x04 0x86>;
  609. phandle = <0x168>;
  610. };
  611.  
  612. i2s1m2-sdi2 {
  613. rockchip,pins = <0x02 0x1d 0x05 0x86>;
  614. phandle = <0x171>;
  615. };
  616.  
  617. i2s1m1-sdo0 {
  618. rockchip,pins = <0x03 0x19 0x04 0x86>;
  619. phandle = <0x166>;
  620. };
  621.  
  622. i2s1m2-sdi0 {
  623. rockchip,pins = <0x02 0x1b 0x05 0x86>;
  624. phandle = <0x16f>;
  625. };
  626.  
  627. i2s1m0-sdo2 {
  628. rockchip,pins = <0x01 0x09 0x01 0x86>;
  629. phandle = <0x15b>;
  630. };
  631.  
  632. i2s1m1-sdi2 {
  633. rockchip,pins = <0x03 0x1c 0x04 0x86>;
  634. phandle = <0x164>;
  635. };
  636.  
  637. i2s1m0-sdo0 {
  638. rockchip,pins = <0x01 0x07 0x01 0x86>;
  639. phandle = <0x5a>;
  640. };
  641.  
  642. i2s1m1-sdi0 {
  643. rockchip,pins = <0x03 0x1a 0x04 0x86>;
  644. phandle = <0x162>;
  645. };
  646.  
  647. i2s1m2-sdo3 {
  648. rockchip,pins = <0x03 0x12 0x05 0x86>;
  649. phandle = <0x176>;
  650. };
  651.  
  652. i2s1m0-sdi2 {
  653. rockchip,pins = <0x01 0x09 0x02 0x86>;
  654. phandle = <0x158>;
  655. };
  656.  
  657. i2s1m2-sdo1 {
  658. rockchip,pins = <0x03 0x00 0x05 0x86>;
  659. phandle = <0x174>;
  660. };
  661.  
  662. i2s1m0-sdi0 {
  663. rockchip,pins = <0x01 0x0b 0x01 0x86>;
  664. phandle = <0x59>;
  665. };
  666.  
  667. i2s1m1-sdo3 {
  668. rockchip,pins = <0x04 0x0d 0x04 0x86>;
  669. phandle = <0x169>;
  670. };
  671.  
  672. i2s1m2-sdi3 {
  673. rockchip,pins = <0x02 0x1e 0x05 0x86>;
  674. phandle = <0x172>;
  675. };
  676.  
  677. i2s1m2-mclk {
  678. rockchip,pins = <0x02 0x18 0x05 0x86>;
  679. phandle = <0x16c>;
  680. };
  681.  
  682. i2s1m1-sdo1 {
  683. rockchip,pins = <0x04 0x08 0x05 0x86>;
  684. phandle = <0x167>;
  685. };
  686.  
  687. i2s1m2-sdi1 {
  688. rockchip,pins = <0x02 0x1c 0x05 0x86>;
  689. phandle = <0x170>;
  690. };
  691.  
  692. i2s1m0-sdo3 {
  693. rockchip,pins = <0x01 0x0a 0x01 0x86>;
  694. phandle = <0x15c>;
  695. };
  696.  
  697. i2s1m1-sdi3 {
  698. rockchip,pins = <0x03 0x1d 0x04 0x86>;
  699. phandle = <0x165>;
  700. };
  701.  
  702. i2s1m1-mclk {
  703. rockchip,pins = <0x03 0x16 0x04 0x86>;
  704. phandle = <0x15f>;
  705. };
  706. };
  707.  
  708. pdm {
  709.  
  710. pdmm0-sdi3 {
  711. rockchip,pins = <0x01 0x08 0x03 0x86>;
  712. phandle = <0x1a5>;
  713. };
  714.  
  715. pdmm2-clk1 {
  716. rockchip,pins = <0x03 0x14 0x05 0x86>;
  717. phandle = <0x1ac>;
  718. };
  719.  
  720. pdmm0-sdi1 {
  721. rockchip,pins = <0x01 0x0a 0x03 0x86>;
  722. phandle = <0x1a3>;
  723. };
  724.  
  725. pdmm1-clk {
  726. rockchip,pins = <0x03 0x1e 0x05 0x86>;
  727. phandle = <0x1a6>;
  728. };
  729.  
  730. pdmm1-clk1 {
  731. rockchip,pins = <0x04 0x00 0x04 0x86>;
  732. phandle = <0x1a7>;
  733. };
  734.  
  735. pdmm2-sdi2 {
  736. rockchip,pins = <0x03 0x0f 0x05 0x86>;
  737. phandle = <0x1af>;
  738. };
  739.  
  740. pdmm0-clk1 {
  741. rockchip,pins = <0x01 0x04 0x03 0x86>;
  742. phandle = <0x1a1>;
  743. };
  744.  
  745. pdmm2-sdi0 {
  746. rockchip,pins = <0x03 0x0b 0x05 0x86>;
  747. phandle = <0x1ad>;
  748. };
  749.  
  750. pdmm1-sdi2 {
  751. rockchip,pins = <0x04 0x02 0x05 0x86>;
  752. phandle = <0x1aa>;
  753. };
  754.  
  755. pdmm1-sdi0 {
  756. rockchip,pins = <0x03 0x1f 0x05 0x86>;
  757. phandle = <0x1a8>;
  758. };
  759.  
  760. pdmm0-sdi2 {
  761. rockchip,pins = <0x01 0x09 0x03 0x86>;
  762. phandle = <0x1a4>;
  763. };
  764.  
  765. pdmm0-sdi0 {
  766. rockchip,pins = <0x01 0x0b 0x02 0x86>;
  767. phandle = <0x1a2>;
  768. };
  769.  
  770. pdmm2-sdi3 {
  771. rockchip,pins = <0x03 0x10 0x05 0x86>;
  772. phandle = <0x1b0>;
  773. };
  774.  
  775. pdmm2-sdi1 {
  776. rockchip,pins = <0x03 0x0c 0x05 0x86>;
  777. phandle = <0x1ae>;
  778. };
  779.  
  780. pdmm1-sdi3 {
  781. rockchip,pins = <0x04 0x03 0x05 0x86>;
  782. phandle = <0x1ab>;
  783. };
  784.  
  785. pdmm0-clk {
  786. rockchip,pins = <0x01 0x06 0x03 0x86>;
  787. phandle = <0x1a0>;
  788. };
  789.  
  790. pdmm1-sdi1 {
  791. rockchip,pins = <0x04 0x01 0x04 0x86>;
  792. phandle = <0x1a9>;
  793. };
  794. };
  795.  
  796. pcfg-pull-none-drv-level-12 {
  797. drive-strength = <0x0c>;
  798. bias-disable;
  799. phandle = <0xf1>;
  800. };
  801.  
  802. gpio@fe770000 {
  803. gpio-controller;
  804. interrupts = <0x00 0x25 0x04>;
  805. clocks = <0x0b 0x169 0x0b 0x16a>;
  806. compatible = "rockchip,gpio-bank";
  807. #interrupt-cells = <0x02>;
  808. reg = <0x00 0xfe770000 0x00 0x100>;
  809. phandle = <0x95>;
  810. #gpio-cells = <0x02>;
  811. interrupt-controller;
  812. };
  813.  
  814. i2c1 {
  815.  
  816. i2c1-xfer {
  817. rockchip,pins = <0x00 0x0b 0x01 0x8b 0x00 0x0c 0x01 0x8b>;
  818. phandle = <0x5b>;
  819. };
  820. };
  821.  
  822. pwm7 {
  823.  
  824. pwm7-pins {
  825. rockchip,pins = <0x00 0x16 0x01 0x86>;
  826. phandle = <0x79>;
  827. };
  828. };
  829.  
  830. pcfg-pull-none-drv-level-5 {
  831. drive-strength = <0x05>;
  832. bias-disable;
  833. phandle = <0xea>;
  834. };
  835.  
  836. gmac0 {
  837.  
  838. gmac0-clkinout {
  839. rockchip,pins = <0x02 0x12 0x02 0x86>;
  840. phandle = <0x141>;
  841. };
  842.  
  843. gmac0-miim {
  844. rockchip,pins = <0x02 0x13 0x02 0x86 0x02 0x14 0x02 0x86>;
  845. phandle = <0x140>;
  846. };
  847.  
  848. gmac0-tx-bus2 {
  849. rockchip,pins = <0x02 0x0b 0x01 0x89 0x02 0x0c 0x01 0x89 0x02 0x0d 0x01 0x86>;
  850. phandle = <0x144>;
  851. };
  852.  
  853. gmac0-rgmii-bus {
  854. rockchip,pins = <0x02 0x03 0x02 0x86 0x02 0x04 0x02 0x86 0x02 0x06 0x02 0x89 0x02 0x07 0x02 0x89>;
  855. phandle = <0x146>;
  856. };
  857.  
  858. gmac0-rx-er {
  859. rockchip,pins = <0x02 0x15 0x02 0x86>;
  860. phandle = <0x142>;
  861. };
  862.  
  863. gmac0-rx-bus2 {
  864. rockchip,pins = <0x02 0x0e 0x01 0x86 0x02 0x0f 0x02 0x86 0x02 0x10 0x02 0x86>;
  865. phandle = <0x143>;
  866. };
  867.  
  868. gmac0-rgmii-clk {
  869. rockchip,pins = <0x02 0x05 0x02 0x86 0x02 0x08 0x02 0x8a>;
  870. phandle = <0x145>;
  871. };
  872. };
  873.  
  874. pwm12 {
  875.  
  876. pwm12m1-pins {
  877. rockchip,pins = <0x04 0x15 0x01 0x86>;
  878. phandle = <0x1ba>;
  879. };
  880.  
  881. pwm12m0-pins {
  882. rockchip,pins = <0x03 0x0f 0x02 0x86>;
  883. phandle = <0x7e>;
  884. };
  885. };
  886.  
  887. uart6 {
  888.  
  889. uart6m0-ctsn {
  890. rockchip,pins = <0x02 0x10 0x03 0x86>;
  891. phandle = <0x1fe>;
  892. };
  893.  
  894. uart6m1-xfer {
  895. rockchip,pins = <0x01 0x1e 0x03 0x88 0x01 0x1d 0x03 0x88>;
  896. phandle = <0x200>;
  897. };
  898.  
  899. uart6m0-xfer {
  900. rockchip,pins = <0x02 0x03 0x03 0x88 0x02 0x04 0x03 0x88>;
  901. phandle = <0x6c>;
  902. };
  903.  
  904. uart6m0-rtsn {
  905. rockchip,pins = <0x02 0x0f 0x03 0x86>;
  906. phandle = <0x1ff>;
  907. };
  908. };
  909.  
  910. pcfg-pull-down-drv-level-8 {
  911. drive-strength = <0x08>;
  912. bias-pull-down;
  913. phandle = <0x10b>;
  914. };
  915.  
  916. gpu {
  917.  
  918. gpu-pins {
  919. rockchip,pins = <0x00 0x10 0x02 0x86 0x00 0x06 0x04 0x86>;
  920. phandle = <0x14f>;
  921. };
  922. };
  923.  
  924. spi0 {
  925.  
  926. spi0m0-cs0 {
  927. rockchip,pins = <0x00 0x16 0x02 0x86>;
  928. phandle = <0x1d7>;
  929. };
  930.  
  931. spi0m1-cs0 {
  932. rockchip,pins = <0x02 0x1a 0x03 0x86>;
  933. phandle = <0x1da>;
  934. };
  935.  
  936. spi0m1-pins {
  937. rockchip,pins = <0x02 0x1b 0x03 0x86 0x02 0x18 0x03 0x86 0x02 0x19 0x03 0x86>;
  938. phandle = <0x1d9>;
  939. };
  940.  
  941. spi0m0-cs1 {
  942. rockchip,pins = <0x00 0x14 0x02 0x86>;
  943. phandle = <0x1d8>;
  944. };
  945.  
  946. spi0m0-pins {
  947. rockchip,pins = <0x00 0x0d 0x02 0x86 0x00 0x15 0x02 0x86 0x00 0x0e 0x02 0x86>;
  948. phandle = <0x1d6>;
  949. };
  950. };
  951.  
  952. fspi {
  953.  
  954. fspi-pins {
  955. rockchip,pins = <0x01 0x18 0x01 0x86 0x01 0x1b 0x01 0x86 0x01 0x19 0x01 0x86 0x01 0x1a 0x01 0x86 0x01 0x17 0x02 0x86 0x01 0x1c 0x01 0x86>;
  956. phandle = <0x13e>;
  957. };
  958.  
  959. fspi-cs1 {
  960. rockchip,pins = <0x01 0x16 0x02 0x88>;
  961. phandle = <0x13f>;
  962. };
  963. };
  964.  
  965. pcfg-pull-up-drv-level-13 {
  966. drive-strength = <0x0d>;
  967. phandle = <0x100>;
  968. bias-pull-up;
  969. };
  970.  
  971. clk32k {
  972.  
  973. clk32k-out0 {
  974. rockchip,pins = <0x00 0x08 0x02 0x86>;
  975. phandle = <0x0a>;
  976. };
  977.  
  978. clk32k-in {
  979. rockchip,pins = <0x00 0x08 0x01 0x86>;
  980. phandle = <0x12e>;
  981. };
  982.  
  983. clk32k-out1 {
  984. rockchip,pins = <0x02 0x16 0x01 0x86>;
  985. phandle = <0x12f>;
  986. };
  987. };
  988.  
  989. pcfg-pull-down-drv-level-11 {
  990. drive-strength = <0x0b>;
  991. bias-pull-down;
  992. phandle = <0x10e>;
  993. };
  994.  
  995. bt {
  996.  
  997. bt-wake-l {
  998. rockchip,pins = <0x02 0x11 0x00 0x86>;
  999. phandle = <0x65>;
  1000. };
  1001.  
  1002. bt-host-wake-l {
  1003. rockchip,pins = <0x02 0x10 0x00 0x8e>;
  1004. phandle = <0x64>;
  1005. };
  1006.  
  1007. bt-enable-h {
  1008. rockchip,pins = <0x02 0x0f 0x00 0x86>;
  1009. phandle = <0x66>;
  1010. };
  1011. };
  1012.  
  1013. ebc {
  1014.  
  1015. ebc-pins {
  1016. rockchip,pins = <0x04 0x10 0x02 0x86 0x04 0x0b 0x02 0x86 0x04 0x0c 0x02 0x86 0x04 0x06 0x02 0x86 0x04 0x11 0x02 0x86 0x03 0x16 0x02 0x86 0x03 0x17 0x02 0x86 0x03 0x18 0x02 0x86 0x03 0x19 0x02 0x86 0x03 0x1a 0x02 0x86 0x03 0x1b 0x02 0x86 0x03 0x1c 0x02 0x86 0x03 0x1d 0x02 0x86 0x03 0x1e 0x02 0x86 0x03 0x1f 0x02 0x86 0x04 0x00 0x02 0x86 0x04 0x01 0x02 0x86 0x04 0x02 0x02 0x86 0x04 0x03 0x02 0x86 0x04 0x04 0x02 0x86 0x04 0x05 0x02 0x86 0x04 0x0e 0x02 0x86 0x04 0x0f 0x02 0x86>;
  1017. phandle = <0x132>;
  1018. };
  1019.  
  1020. ebc-extern {
  1021. rockchip,pins = <0x04 0x07 0x02 0x86 0x04 0x08 0x02 0x86 0x04 0x09 0x02 0x86 0x04 0x0d 0x02 0x86 0x04 0x0a 0x02 0x86>;
  1022. phandle = <0x131>;
  1023. };
  1024. };
  1025.  
  1026. pcfg-pull-up-drv-level-0 {
  1027. drive-strength = <0x00>;
  1028. phandle = <0xf5>;
  1029. bias-pull-up;
  1030. };
  1031.  
  1032. spi2-hs {
  1033.  
  1034. spi2m0-cs1 {
  1035. rockchip,pins = <0x02 0x15 0x04 0x8c>;
  1036. phandle = <0x21a>;
  1037. };
  1038.  
  1039. spi2m1-cs1 {
  1040. rockchip,pins = <0x02 0x1c 0x03 0x8c>;
  1041. phandle = <0x21d>;
  1042. };
  1043.  
  1044. spi2m1-pins {
  1045. rockchip,pins = <0x03 0x00 0x03 0x8c 0x02 0x1f 0x03 0x8c 0x02 0x1e 0x03 0x8c>;
  1046. phandle = <0x21b>;
  1047. };
  1048.  
  1049. spi2m0-cs0 {
  1050. rockchip,pins = <0x02 0x14 0x04 0x8c>;
  1051. phandle = <0x219>;
  1052. };
  1053.  
  1054. spi2m0-pins {
  1055. rockchip,pins = <0x02 0x11 0x04 0x8c 0x02 0x12 0x04 0x8c 0x02 0x13 0x04 0x8c>;
  1056. phandle = <0x218>;
  1057. };
  1058.  
  1059. spi2m1-cs0 {
  1060. rockchip,pins = <0x02 0x1d 0x03 0x8c>;
  1061. phandle = <0x21c>;
  1062. };
  1063. };
  1064.  
  1065. pcfg-pull-none-drv-level-10 {
  1066. drive-strength = <0x0a>;
  1067. bias-disable;
  1068. phandle = <0xef>;
  1069. };
  1070.  
  1071. pwm5 {
  1072.  
  1073. pwm5-pins {
  1074. rockchip,pins = <0x00 0x14 0x01 0x86>;
  1075. phandle = <0x77>;
  1076. };
  1077. };
  1078.  
  1079. pcfg-pull-none-drv-level-3 {
  1080. drive-strength = <0x03>;
  1081. bias-disable;
  1082. phandle = <0x8d>;
  1083. };
  1084.  
  1085. isp {
  1086.  
  1087. isp-pins {
  1088. rockchip,pins = <0x04 0x0c 0x04 0x86 0x04 0x06 0x01 0x86 0x04 0x09 0x01 0x86>;
  1089. phandle = <0x18f>;
  1090. };
  1091. };
  1092.  
  1093. pwm10 {
  1094.  
  1095. pwm10m1-pins {
  1096. rockchip,pins = <0x02 0x01 0x02 0x86>;
  1097. phandle = <0x1b8>;
  1098. };
  1099.  
  1100. pwm10m0-pins {
  1101. rockchip,pins = <0x03 0x0d 0x05 0x86>;
  1102. phandle = <0x7c>;
  1103. };
  1104. };
  1105.  
  1106. pcfg-pull-down-smt {
  1107. input-schmitt-enable;
  1108. bias-pull-down;
  1109. phandle = <0x114>;
  1110. };
  1111.  
  1112. pcfg-pull-down {
  1113. bias-pull-down;
  1114. phandle = <0x8e>;
  1115. };
  1116.  
  1117. uart4 {
  1118.  
  1119. uart4m0-ctsn {
  1120. rockchip,pins = <0x01 0x07 0x02 0x86>;
  1121. phandle = <0x1f8>;
  1122. };
  1123.  
  1124. uart4m1-xfer {
  1125. rockchip,pins = <0x03 0x09 0x04 0x88 0x03 0x0a 0x04 0x88>;
  1126. phandle = <0x1fa>;
  1127. };
  1128.  
  1129. uart4m0-xfer {
  1130. rockchip,pins = <0x01 0x04 0x02 0x88 0x01 0x06 0x02 0x88>;
  1131. phandle = <0x6a>;
  1132. };
  1133.  
  1134. uart4m0-rtsn {
  1135. rockchip,pins = <0x01 0x05 0x02 0x86>;
  1136. phandle = <0x1f9>;
  1137. };
  1138. };
  1139.  
  1140. pcfg-pull-down-drv-level-6 {
  1141. drive-strength = <0x06>;
  1142. bias-pull-down;
  1143. phandle = <0x109>;
  1144. };
  1145.  
  1146. pcfg-pull-up-drv-level-9 {
  1147. drive-strength = <0x09>;
  1148. phandle = <0xfc>;
  1149. bias-pull-up;
  1150. };
  1151.  
  1152. pcfg-pull-up-drv-level-11 {
  1153. drive-strength = <0x0b>;
  1154. phandle = <0xfe>;
  1155. bias-pull-up;
  1156. };
  1157.  
  1158. mcu {
  1159.  
  1160. mcu-pins {
  1161. rockchip,pins = <0x00 0x0c 0x04 0x86 0x00 0x11 0x04 0x86 0x00 0x0b 0x04 0x86 0x00 0x12 0x04 0x86 0x00 0x13 0x04 0x86>;
  1162. phandle = <0x192>;
  1163. };
  1164. };
  1165.  
  1166. pwm3 {
  1167.  
  1168. pwm3-pins {
  1169. rockchip,pins = <0x00 0x12 0x01 0x86>;
  1170. phandle = <0x1b>;
  1171. };
  1172. };
  1173.  
  1174. pcfg-pull-none-drv-level-1 {
  1175. drive-strength = <0x01>;
  1176. bias-disable;
  1177. phandle = <0x8a>;
  1178. };
  1179.  
  1180. sata2 {
  1181.  
  1182. sata2-pins {
  1183. rockchip,pins = <0x04 0x14 0x03 0x86>;
  1184. phandle = <0x1c2>;
  1185. };
  1186. };
  1187.  
  1188. gpio@fe740000 {
  1189. gpio-controller;
  1190. interrupts = <0x00 0x22 0x04>;
  1191. clocks = <0x0b 0x163 0x0b 0x164>;
  1192. compatible = "rockchip,gpio-bank";
  1193. #interrupt-cells = <0x02>;
  1194. reg = <0x00 0xfe740000 0x00 0x100>;
  1195. phandle = <0xe6>;
  1196. #gpio-cells = <0x02>;
  1197. interrupt-controller;
  1198. };
  1199.  
  1200. cam {
  1201.  
  1202. cam-clkout0 {
  1203. rockchip,pins = <0x04 0x07 0x01 0x86>;
  1204. phandle = <0x122>;
  1205. };
  1206.  
  1207. cam-clkout1 {
  1208. rockchip,pins = <0x04 0x08 0x01 0x86>;
  1209. phandle = <0x123>;
  1210. };
  1211. };
  1212.  
  1213. uart2 {
  1214.  
  1215. uart2m1-xfer {
  1216. rockchip,pins = <0x01 0x1e 0x02 0x88 0x01 0x1d 0x02 0x88>;
  1217. phandle = <0x1f4>;
  1218. };
  1219.  
  1220. uart2m0-xfer {
  1221. rockchip,pins = <0x00 0x18 0x01 0x88 0x00 0x19 0x01 0x88>;
  1222. phandle = <0x68>;
  1223. };
  1224. };
  1225.  
  1226. pcfg-pull-down-drv-level-4 {
  1227. drive-strength = <0x04>;
  1228. bias-pull-down;
  1229. phandle = <0x107>;
  1230. };
  1231.  
  1232. pcfg-pull-up-drv-level-7 {
  1233. drive-strength = <0x07>;
  1234. phandle = <0xfa>;
  1235. bias-pull-up;
  1236. };
  1237.  
  1238. lcdc {
  1239.  
  1240. lcdc-ctl {
  1241. rockchip,pins = <0x03 0x00 0x01 0x86 0x02 0x18 0x01 0x86 0x02 0x19 0x01 0x86 0x02 0x1a 0x01 0x86 0x02 0x1b 0x01 0x86 0x02 0x1c 0x01 0x86 0x02 0x1d 0x01 0x86 0x02 0x1e 0x01 0x86 0x02 0x1f 0x01 0x86 0x03 0x01 0x01 0x86 0x03 0x02 0x01 0x86 0x03 0x03 0x01 0x86 0x03 0x04 0x01 0x86 0x03 0x05 0x01 0x86 0x03 0x06 0x01 0x86 0x03 0x07 0x01 0x86 0x03 0x08 0x01 0x86 0x03 0x09 0x01 0x86 0x03 0x0a 0x01 0x86 0x03 0x0b 0x01 0x86 0x03 0x0c 0x01 0x86 0x03 0x0d 0x01 0x86 0x03 0x0e 0x01 0x86 0x03 0x0f 0x01 0x86 0x03 0x10 0x01 0x86 0x03 0x13 0x01 0x86 0x03 0x11 0x01 0x86 0x03 0x12 0x01 0x86>;
  1242. phandle = <0x191>;
  1243. };
  1244. };
  1245.  
  1246. cpu {
  1247.  
  1248. cpu-pins {
  1249. rockchip,pins = <0x00 0x0f 0x02 0x86>;
  1250. phandle = <0x130>;
  1251. };
  1252. };
  1253.  
  1254. sdmmc1 {
  1255.  
  1256. sdmmc1-cmd {
  1257. rockchip,pins = <0x02 0x07 0x01 0x87>;
  1258. phandle = <0x1c7>;
  1259. };
  1260.  
  1261. sdmmc1-clk {
  1262. rockchip,pins = <0x02 0x08 0x01 0x87>;
  1263. phandle = <0x1c6>;
  1264. };
  1265.  
  1266. sdmmc1-bus4 {
  1267. rockchip,pins = <0x02 0x03 0x01 0x87 0x02 0x04 0x01 0x87 0x02 0x05 0x01 0x87 0x02 0x06 0x01 0x87>;
  1268. phandle = <0x1c5>;
  1269. };
  1270.  
  1271. sdmmc1-det {
  1272. rockchip,pins = <0x02 0x0a 0x01 0x88>;
  1273. phandle = <0x1c8>;
  1274. };
  1275.  
  1276. sdmmc1-pwren {
  1277. rockchip,pins = <0x02 0x09 0x01 0x86>;
  1278. phandle = <0x1c9>;
  1279. };
  1280. };
  1281.  
  1282. leds {
  1283.  
  1284. diy-led-enable-h {
  1285. rockchip,pins = <0x00 0x1c 0x00 0x86>;
  1286. phandle = <0x90>;
  1287. };
  1288.  
  1289. work-led-enable-h {
  1290. rockchip,pins = <0x00 0x1b 0x00 0x86>;
  1291. phandle = <0x8f>;
  1292. };
  1293. };
  1294.  
  1295. pwm1 {
  1296.  
  1297. pwm1m1-pins {
  1298. rockchip,pins = <0x00 0x0d 0x04 0x86>;
  1299. phandle = <0x1b4>;
  1300. };
  1301.  
  1302. pwm1m0-pins {
  1303. rockchip,pins = <0x00 0x10 0x01 0x86>;
  1304. phandle = <0x19>;
  1305. };
  1306. };
  1307.  
  1308. sata0 {
  1309.  
  1310. sata0-pins {
  1311. rockchip,pins = <0x04 0x16 0x03 0x86>;
  1312. phandle = <0x1c0>;
  1313. };
  1314. };
  1315.  
  1316. refclk {
  1317.  
  1318. refclk-pins {
  1319. rockchip,pins = <0x00 0x00 0x01 0x86>;
  1320. phandle = <0x1be>;
  1321. };
  1322. };
  1323.  
  1324. can2 {
  1325.  
  1326. can2m1-pins {
  1327. rockchip,pins = <0x02 0x09 0x04 0x86 0x02 0x0a 0x04 0x86>;
  1328. phandle = <0x129>;
  1329. };
  1330.  
  1331. can2m0-pins {
  1332. rockchip,pins = <0x04 0x0c 0x03 0x86 0x04 0x0d 0x03 0x86>;
  1333. phandle = <0x128>;
  1334. };
  1335. };
  1336.  
  1337. sata {
  1338.  
  1339. sata-pins {
  1340. rockchip,pins = <0x00 0x04 0x02 0x86 0x00 0x06 0x01 0x86 0x00 0x05 0x02 0x86>;
  1341. phandle = <0x1bf>;
  1342. };
  1343. };
  1344.  
  1345. audiopwm {
  1346.  
  1347. audiopwm-routn {
  1348. rockchip,pins = <0x01 0x07 0x04 0x86>;
  1349. phandle = <0x11d>;
  1350. };
  1351.  
  1352. audiopwm-lout {
  1353. rockchip,pins = <0x01 0x00 0x04 0x86>;
  1354. phandle = <0x119>;
  1355. };
  1356.  
  1357. audiopwm-routp {
  1358. rockchip,pins = <0x01 0x06 0x04 0x86>;
  1359. phandle = <0x11e>;
  1360. };
  1361.  
  1362. audiopwm-loutn {
  1363. rockchip,pins = <0x01 0x01 0x06 0x86>;
  1364. phandle = <0x11a>;
  1365. };
  1366.  
  1367. audiopwm-loutp {
  1368. rockchip,pins = <0x01 0x00 0x06 0x86>;
  1369. phandle = <0x11b>;
  1370. };
  1371.  
  1372. audiopwm-rout {
  1373. rockchip,pins = <0x01 0x01 0x04 0x86>;
  1374. phandle = <0x11c>;
  1375. };
  1376. };
  1377.  
  1378. edpdp {
  1379.  
  1380. edpdpm1-pins {
  1381. rockchip,pins = <0x00 0x12 0x02 0x86>;
  1382. phandle = <0x134>;
  1383. };
  1384.  
  1385. edpdpm0-pins {
  1386. rockchip,pins = <0x04 0x14 0x01 0x86>;
  1387. phandle = <0x133>;
  1388. };
  1389. };
  1390.  
  1391. tsadc {
  1392.  
  1393. tsadc-pin {
  1394. rockchip,pins = <0x00 0x01 0x00 0x86>;
  1395. phandle = <0x74>;
  1396. };
  1397.  
  1398. tsadc-shutorg {
  1399. rockchip,pins = <0x00 0x01 0x02 0x86>;
  1400. phandle = <0x75>;
  1401. };
  1402.  
  1403. tsadcm1-shut {
  1404. rockchip,pins = <0x00 0x02 0x02 0x86>;
  1405. phandle = <0x1ed>;
  1406. };
  1407.  
  1408. tsadcm0-shut {
  1409. rockchip,pins = <0x00 0x01 0x01 0x86>;
  1410. phandle = <0x1ec>;
  1411. };
  1412. };
  1413.  
  1414. uart0 {
  1415.  
  1416. uart0-rtsn {
  1417. rockchip,pins = <0x00 0x14 0x03 0x86>;
  1418. phandle = <0x1ef>;
  1419. };
  1420.  
  1421. uart0-ctsn {
  1422. rockchip,pins = <0x00 0x17 0x03 0x86>;
  1423. phandle = <0x1ee>;
  1424. };
  1425.  
  1426. uart0-xfer {
  1427. rockchip,pins = <0x00 0x10 0x03 0x88 0x00 0x11 0x03 0x88>;
  1428. phandle = <0x17>;
  1429. };
  1430. };
  1431.  
  1432. pcfg-pull-down-drv-level-2 {
  1433. drive-strength = <0x02>;
  1434. bias-pull-down;
  1435. phandle = <0x105>;
  1436. };
  1437.  
  1438. pcfg-pull-up-drv-level-5 {
  1439. drive-strength = <0x05>;
  1440. phandle = <0xf8>;
  1441. bias-pull-up;
  1442. };
  1443.  
  1444. pcfg-pull-none-drv-level-15 {
  1445. drive-strength = <0x0f>;
  1446. bias-disable;
  1447. phandle = <0xf4>;
  1448. };
  1449.  
  1450. eth1 {
  1451.  
  1452. eth1m1-pins {
  1453. rockchip,pins = <0x04 0x0b 0x03 0x86>;
  1454. phandle = <0x13c>;
  1455. };
  1456.  
  1457. eth1m0-pins {
  1458. rockchip,pins = <0x03 0x08 0x03 0x86>;
  1459. phandle = <0x13b>;
  1460. };
  1461. };
  1462.  
  1463. i2c4 {
  1464.  
  1465. i2c4m1-xfer {
  1466. rockchip,pins = <0x02 0x0a 0x02 0x8b 0x02 0x09 0x02 0x8b>;
  1467. phandle = <0x153>;
  1468. };
  1469.  
  1470. i2c4m0-xfer {
  1471. rockchip,pins = <0x04 0x0b 0x01 0x8b 0x04 0x0a 0x01 0x8b>;
  1472. phandle = <0x5e>;
  1473. };
  1474. };
  1475.  
  1476. emmc {
  1477.  
  1478. emmc-clk {
  1479. rockchip,pins = <0x01 0x15 0x01 0x87>;
  1480. phandle = <0x137>;
  1481. };
  1482.  
  1483. emmc-datastrobe {
  1484. rockchip,pins = <0x01 0x16 0x01 0x86>;
  1485. phandle = <0x139>;
  1486. };
  1487.  
  1488. emmc-bus8 {
  1489. rockchip,pins = <0x01 0x0c 0x01 0x87 0x01 0x0d 0x01 0x87 0x01 0x0e 0x01 0x87 0x01 0x0f 0x01 0x87 0x01 0x10 0x01 0x87 0x01 0x11 0x01 0x87 0x01 0x12 0x01 0x87 0x01 0x13 0x01 0x87>;
  1490. phandle = <0x136>;
  1491. };
  1492.  
  1493. emmc-cmd {
  1494. rockchip,pins = <0x01 0x14 0x01 0x87>;
  1495. phandle = <0x138>;
  1496. };
  1497.  
  1498. emmc-rstnout {
  1499. rockchip,pins = <0x01 0x17 0x01 0x86>;
  1500. phandle = <0x135>;
  1501. };
  1502. };
  1503.  
  1504. pcfg-pull-none-drv-level-8 {
  1505. drive-strength = <0x08>;
  1506. bias-disable;
  1507. phandle = <0xed>;
  1508. };
  1509.  
  1510. pwm15 {
  1511.  
  1512. pwm15m0-pins {
  1513. rockchip,pins = <0x03 0x15 0x01 0x86>;
  1514. phandle = <0x81>;
  1515. };
  1516.  
  1517. pwm15m1-pins {
  1518. rockchip,pins = <0x04 0x13 0x01 0x86>;
  1519. phandle = <0x1bd>;
  1520. };
  1521. };
  1522.  
  1523. spdif {
  1524.  
  1525. spdifm1-tx {
  1526. rockchip,pins = <0x03 0x15 0x02 0x86>;
  1527. phandle = <0x1d4>;
  1528. };
  1529.  
  1530. spdifm0-tx {
  1531. rockchip,pins = <0x01 0x04 0x04 0x86>;
  1532. phandle = <0x56>;
  1533. };
  1534.  
  1535. spdifm2-tx {
  1536. rockchip,pins = <0x04 0x14 0x02 0x86>;
  1537. phandle = <0x1d5>;
  1538. };
  1539. };
  1540.  
  1541. pcie30x2 {
  1542.  
  1543. pcie30x2m2-pins {
  1544. rockchip,pins = <0x04 0x12 0x04 0x86 0x04 0x14 0x04 0x86 0x04 0x13 0x04 0x86>;
  1545. phandle = <0x19e>;
  1546. };
  1547.  
  1548. pcie30x2m1-pins {
  1549. rockchip,pins = <0x02 0x1c 0x04 0x86 0x02 0x1e 0x04 0x86 0x02 0x1d 0x04 0x86>;
  1550. phandle = <0x19d>;
  1551. };
  1552.  
  1553. pcie30x2-buttonrstn {
  1554. rockchip,pins = <0x00 0x08 0x03 0x86>;
  1555. phandle = <0x19f>;
  1556. };
  1557.  
  1558. pcie30x2m0-pins {
  1559. rockchip,pins = <0x00 0x06 0x02 0x86 0x00 0x16 0x03 0x86 0x00 0x15 0x03 0x86>;
  1560. phandle = <0x19c>;
  1561. };
  1562. };
  1563.  
  1564. can0 {
  1565.  
  1566. can0m0-pins {
  1567. rockchip,pins = <0x00 0x0c 0x02 0x86 0x00 0x0b 0x02 0x86>;
  1568. phandle = <0x124>;
  1569. };
  1570.  
  1571. can0m1-pins {
  1572. rockchip,pins = <0x02 0x02 0x04 0x86 0x02 0x01 0x04 0x86>;
  1573. phandle = <0x125>;
  1574. };
  1575. };
  1576.  
  1577. pcfg-output-high {
  1578. output-high;
  1579. phandle = <0x116>;
  1580. };
  1581.  
  1582. uart9 {
  1583.  
  1584. uart9m0-rtsn {
  1585. rockchip,pins = <0x02 0x13 0x03 0x86>;
  1586. phandle = <0x209>;
  1587. };
  1588.  
  1589. uart9m2-xfer {
  1590. rockchip,pins = <0x04 0x05 0x04 0x88 0x04 0x04 0x04 0x88>;
  1591. phandle = <0x20b>;
  1592. };
  1593.  
  1594. uart9m0-ctsn {
  1595. rockchip,pins = <0x02 0x14 0x03 0x86>;
  1596. phandle = <0x208>;
  1597. };
  1598.  
  1599. uart9m1-xfer {
  1600. rockchip,pins = <0x04 0x16 0x04 0x88 0x04 0x15 0x04 0x88>;
  1601. phandle = <0x20a>;
  1602. };
  1603.  
  1604. uart9m0-xfer {
  1605. rockchip,pins = <0x02 0x07 0x03 0x88 0x02 0x08 0x03 0x88>;
  1606. phandle = <0x6f>;
  1607. };
  1608. };
  1609.  
  1610. pcfg-pull-up {
  1611. phandle = <0x88>;
  1612. bias-pull-up;
  1613. };
  1614.  
  1615. spi3 {
  1616.  
  1617. spi3m1-cs0 {
  1618. rockchip,pins = <0x04 0x16 0x02 0x86>;
  1619. phandle = <0x1ea>;
  1620. };
  1621.  
  1622. spi3m0-cs1 {
  1623. rockchip,pins = <0x04 0x07 0x04 0x86>;
  1624. phandle = <0x1e8>;
  1625. };
  1626.  
  1627. spi3m1-cs1 {
  1628. rockchip,pins = <0x04 0x19 0x02 0x86>;
  1629. phandle = <0x1eb>;
  1630. };
  1631.  
  1632. spi3m1-pins {
  1633. rockchip,pins = <0x04 0x12 0x02 0x86 0x04 0x15 0x02 0x86 0x04 0x13 0x02 0x86>;
  1634. phandle = <0x1e9>;
  1635. };
  1636.  
  1637. spi3m0-pins {
  1638. rockchip,pins = <0x04 0x0b 0x04 0x86 0x04 0x08 0x04 0x86 0x04 0x0a 0x04 0x86>;
  1639. phandle = <0x1e6>;
  1640. };
  1641.  
  1642. spi3m0-cs0 {
  1643. rockchip,pins = <0x04 0x06 0x04 0x86>;
  1644. phandle = <0x1e7>;
  1645. };
  1646. };
  1647.  
  1648. spi1-hs {
  1649.  
  1650. spi1m0-cs0 {
  1651. rockchip,pins = <0x02 0x10 0x04 0x8c>;
  1652. phandle = <0x214>;
  1653. };
  1654.  
  1655. spi1m1-pins {
  1656. rockchip,pins = <0x03 0x13 0x03 0x8c 0x03 0x12 0x03 0x8c 0x03 0x11 0x03 0x8c>;
  1657. phandle = <0x216>;
  1658. };
  1659.  
  1660. spi1m1-cs0 {
  1661. rockchip,pins = <0x03 0x01 0x03 0x8c>;
  1662. phandle = <0x217>;
  1663. };
  1664.  
  1665. spi1m0-pins {
  1666. rockchip,pins = <0x02 0x0d 0x03 0x8c 0x02 0x0e 0x03 0x8c 0x02 0x0f 0x04 0x8c>;
  1667. phandle = <0x213>;
  1668. };
  1669.  
  1670. spi1m0-cs1 {
  1671. rockchip,pins = <0x02 0x16 0x03 0x8c>;
  1672. phandle = <0x215>;
  1673. };
  1674. };
  1675.  
  1676. pcfg-pull-down-drv-level-14 {
  1677. drive-strength = <0x0e>;
  1678. bias-pull-down;
  1679. phandle = <0x111>;
  1680. };
  1681.  
  1682. bt656 {
  1683.  
  1684. bt656m1-pins {
  1685. rockchip,pins = <0x04 0x0c 0x05 0x86 0x03 0x16 0x05 0x86 0x03 0x17 0x05 0x86 0x03 0x18 0x05 0x86 0x03 0x19 0x05 0x86 0x03 0x1a 0x05 0x86 0x03 0x1b 0x05 0x86 0x03 0x1c 0x05 0x86 0x03 0x1d 0x05 0x86>;
  1686. phandle = <0x120>;
  1687. };
  1688.  
  1689. bt656m0-pins {
  1690. rockchip,pins = <0x03 0x00 0x02 0x86 0x02 0x18 0x02 0x86 0x02 0x19 0x02 0x86 0x02 0x1a 0x02 0x86 0x02 0x1b 0x02 0x86 0x02 0x1c 0x02 0x86 0x02 0x1d 0x02 0x86 0x02 0x1e 0x02 0x86 0x02 0x1f 0x02 0x86>;
  1691. phandle = <0x11f>;
  1692. };
  1693. };
  1694.  
  1695. pcfg-pull-down-drv-level-0 {
  1696. drive-strength = <0x00>;
  1697. bias-pull-down;
  1698. phandle = <0x103>;
  1699. };
  1700.  
  1701. pcfg-pull-up-drv-level-3 {
  1702. drive-strength = <0x03>;
  1703. phandle = <0xf6>;
  1704. bias-pull-up;
  1705. };
  1706.  
  1707. i2s2 {
  1708.  
  1709. i2s2m1-mclk {
  1710. rockchip,pins = <0x04 0x0e 0x05 0x86>;
  1711. phandle = <0x180>;
  1712. };
  1713.  
  1714. i2s2m0-mclk {
  1715. rockchip,pins = <0x02 0x11 0x01 0x86>;
  1716. phandle = <0x179>;
  1717. };
  1718.  
  1719. i2s2m1-sdo {
  1720. rockchip,pins = <0x04 0x0b 0x05 0x86>;
  1721. phandle = <0x184>;
  1722. };
  1723.  
  1724. i2s2m0-lrcktx {
  1725. rockchip,pins = <0x02 0x13 0x01 0x86>;
  1726. phandle = <0x178>;
  1727. };
  1728.  
  1729. i2s2m0-sdi {
  1730. rockchip,pins = <0x02 0x15 0x01 0x86>;
  1731. phandle = <0x17c>;
  1732. };
  1733.  
  1734. i2s2m1-lrcktx {
  1735. rockchip,pins = <0x04 0x04 0x05 0x86>;
  1736. phandle = <0x17f>;
  1737. };
  1738.  
  1739. i2s2m0-lrckrx {
  1740. rockchip,pins = <0x02 0x10 0x01 0x86>;
  1741. phandle = <0x177>;
  1742. };
  1743.  
  1744. i2s2m1-lrckrx {
  1745. rockchip,pins = <0x04 0x05 0x05 0x86>;
  1746. phandle = <0x17e>;
  1747. };
  1748.  
  1749. i2s2m0-sclktx {
  1750. rockchip,pins = <0x02 0x12 0x01 0x86>;
  1751. phandle = <0x17b>;
  1752. };
  1753.  
  1754. i2s2m1-sclktx {
  1755. rockchip,pins = <0x04 0x0f 0x04 0x86>;
  1756. phandle = <0x182>;
  1757. };
  1758.  
  1759. i2s2m0-sclkrx {
  1760. rockchip,pins = <0x02 0x0f 0x01 0x86>;
  1761. phandle = <0x17a>;
  1762. };
  1763.  
  1764. i2s2m1-sclkrx {
  1765. rockchip,pins = <0x04 0x11 0x05 0x86>;
  1766. phandle = <0x181>;
  1767. };
  1768.  
  1769. i2s2m1-sdi {
  1770. rockchip,pins = <0x04 0x0a 0x05 0x86>;
  1771. phandle = <0x183>;
  1772. };
  1773.  
  1774. i2s2m0-sdo {
  1775. rockchip,pins = <0x02 0x14 0x01 0x86>;
  1776. phandle = <0x17d>;
  1777. };
  1778. };
  1779.  
  1780. pcfg-pull-none-drv-level-13 {
  1781. drive-strength = <0x0d>;
  1782. bias-disable;
  1783. phandle = <0xf2>;
  1784. };
  1785.  
  1786. i2c2 {
  1787.  
  1788. i2c2m1-xfer {
  1789. rockchip,pins = <0x04 0x0d 0x01 0x8b 0x04 0x0c 0x01 0x8b>;
  1790. phandle = <0x151>;
  1791. };
  1792.  
  1793. i2c2m0-xfer {
  1794. rockchip,pins = <0x00 0x0d 0x01 0x8b 0x00 0x0e 0x01 0x8b>;
  1795. phandle = <0x5c>;
  1796. };
  1797. };
  1798.  
  1799. gmac-txd-level3 {
  1800.  
  1801. gmac1m1-rgmii-bus-level3 {
  1802. rockchip,pins = <0x04 0x01 0x03 0x86 0x04 0x02 0x03 0x86 0x03 0x1e 0x03 0x8d 0x03 0x1f 0x03 0x8d>;
  1803. phandle = <0x229>;
  1804. };
  1805.  
  1806. gmac1m1-tx-bus2-level3 {
  1807. rockchip,pins = <0x04 0x04 0x03 0x8d 0x04 0x05 0x03 0x8d 0x04 0x06 0x03 0x86>;
  1808. phandle = <0x228>;
  1809. };
  1810.  
  1811. gmac1m0-rgmii-bus-level3 {
  1812. rockchip,pins = <0x03 0x04 0x03 0x86 0x03 0x05 0x03 0x86 0x03 0x02 0x03 0x8d 0x03 0x03 0x03 0x8d>;
  1813. phandle = <0x227>;
  1814. };
  1815.  
  1816. gmac1m0-tx-bus2-level3 {
  1817. rockchip,pins = <0x03 0x0d 0x03 0x8d 0x03 0x0e 0x03 0x8d 0x03 0x0f 0x03 0x86>;
  1818. phandle = <0x226>;
  1819. };
  1820.  
  1821. gmac0-tx-bus2-level3 {
  1822. rockchip,pins = <0x02 0x0b 0x01 0x8d 0x02 0x0c 0x01 0x8d 0x02 0x0d 0x01 0x86>;
  1823. phandle = <0x224>;
  1824. };
  1825.  
  1826. gmac0-rgmii-bus-level3 {
  1827. rockchip,pins = <0x02 0x03 0x02 0x86 0x02 0x04 0x02 0x86 0x02 0x06 0x02 0x8d 0x02 0x07 0x02 0x8d>;
  1828. phandle = <0x225>;
  1829. };
  1830. };
  1831.  
  1832. pwm8 {
  1833.  
  1834. pwm8m1-pins {
  1835. rockchip,pins = <0x01 0x1d 0x04 0x86>;
  1836. phandle = <0x1b6>;
  1837. };
  1838.  
  1839. pwm8m0-pins {
  1840. rockchip,pins = <0x03 0x09 0x05 0x86>;
  1841. phandle = <0x7a>;
  1842. };
  1843. };
  1844.  
  1845. pmic {
  1846.  
  1847. pmic-pins {
  1848. rockchip,pins = <0x00 0x02 0x01 0x86>;
  1849. phandle = <0x1b1>;
  1850. };
  1851.  
  1852. pmic-int-l {
  1853. rockchip,pins = <0x00 0x03 0x00 0x88>;
  1854. phandle = <0x13>;
  1855. };
  1856. };
  1857.  
  1858. pcfg-pull-none-drv-level-6 {
  1859. drive-strength = <0x06>;
  1860. bias-disable;
  1861. phandle = <0xeb>;
  1862. };
  1863.  
  1864. jtag {
  1865.  
  1866. jtag-pins {
  1867. rockchip,pins = <0x01 0x1f 0x02 0x86 0x02 0x00 0x02 0x86>;
  1868. phandle = <0x190>;
  1869. };
  1870. };
  1871.  
  1872. gmac1 {
  1873.  
  1874. gmac1m1-clkinout {
  1875. rockchip,pins = <0x04 0x11 0x03 0x86>;
  1876. phandle = <0x149>;
  1877. };
  1878.  
  1879. gmac1m1-rx-er {
  1880. rockchip,pins = <0x04 0x0a 0x03 0x86>;
  1881. phandle = <0x14a>;
  1882. };
  1883.  
  1884. gmac1m1-rgmii-clk {
  1885. rockchip,pins = <0x04 0x03 0x03 0x86 0x04 0x00 0x03 0x8a>;
  1886. phandle = <0x14d>;
  1887. };
  1888.  
  1889. gmac1m1-miim {
  1890. rockchip,pins = <0x04 0x0e 0x03 0x86 0x04 0x0f 0x03 0x86>;
  1891. phandle = <0x148>;
  1892. };
  1893.  
  1894. gmac1m0-rx-bus2 {
  1895. rockchip,pins = <0x03 0x09 0x03 0x86 0x03 0x0a 0x03 0x86 0x03 0x0b 0x03 0x86>;
  1896. phandle = <0x3d>;
  1897. };
  1898.  
  1899. gmac1m0-rgmii-bus {
  1900. rockchip,pins = <0x03 0x04 0x03 0x86 0x03 0x05 0x03 0x86 0x03 0x02 0x03 0x89 0x03 0x03 0x03 0x89>;
  1901. phandle = <0x40>;
  1902. };
  1903.  
  1904. gmac1m0-miim {
  1905. rockchip,pins = <0x03 0x14 0x03 0x86 0x03 0x15 0x03 0x86>;
  1906. phandle = <0x3b>;
  1907. };
  1908.  
  1909. gmac1m1-tx-bus2 {
  1910. rockchip,pins = <0x04 0x04 0x03 0x89 0x04 0x05 0x03 0x89 0x04 0x06 0x03 0x86>;
  1911. phandle = <0x14c>;
  1912. };
  1913.  
  1914. gmac1m1-rgmii-bus {
  1915. rockchip,pins = <0x04 0x01 0x03 0x86 0x04 0x02 0x03 0x86 0x03 0x1e 0x03 0x89 0x03 0x1f 0x03 0x89>;
  1916. phandle = <0x14e>;
  1917. };
  1918.  
  1919. gmac1m0-rgmii-clk {
  1920. rockchip,pins = <0x03 0x07 0x03 0x86 0x03 0x06 0x03 0x8a>;
  1921. phandle = <0x3e>;
  1922. };
  1923.  
  1924. gmac1m0-clkinout {
  1925. rockchip,pins = <0x03 0x10 0x03 0x86>;
  1926. phandle = <0x3f>;
  1927. };
  1928.  
  1929. gmac1m0-rx-er {
  1930. rockchip,pins = <0x03 0x0c 0x03 0x86>;
  1931. phandle = <0x147>;
  1932. };
  1933.  
  1934. gmac1m0-tx-bus2 {
  1935. rockchip,pins = <0x03 0x0d 0x03 0x89 0x03 0x0e 0x03 0x89 0x03 0x0f 0x03 0x86>;
  1936. phandle = <0x3c>;
  1937. };
  1938.  
  1939. gmac1m1-rx-bus2 {
  1940. rockchip,pins = <0x04 0x07 0x03 0x86 0x04 0x08 0x03 0x86 0x04 0x09 0x03 0x86>;
  1941. phandle = <0x14b>;
  1942. };
  1943. };
  1944.  
  1945. pcfg-pull-none {
  1946. bias-disable;
  1947. phandle = <0x86>;
  1948. };
  1949.  
  1950. pwm13 {
  1951.  
  1952. pwm13m1-pins {
  1953. rockchip,pins = <0x04 0x16 0x01 0x86>;
  1954. phandle = <0x1bb>;
  1955. };
  1956.  
  1957. pwm13m0-pins {
  1958. rockchip,pins = <0x03 0x10 0x02 0x86>;
  1959. phandle = <0x7f>;
  1960. };
  1961. };
  1962.  
  1963. acodec {
  1964.  
  1965. acodec-pins {
  1966. rockchip,pins = <0x01 0x09 0x05 0x86 0x01 0x01 0x05 0x86 0x01 0x00 0x05 0x86 0x01 0x07 0x05 0x86 0x01 0x08 0x05 0x86 0x01 0x03 0x05 0x86 0x01 0x05 0x05 0x86>;
  1967. phandle = <0x118>;
  1968. };
  1969. };
  1970.  
  1971. gpio@fe750000 {
  1972. gpio-controller;
  1973. interrupts = <0x00 0x23 0x04>;
  1974. clocks = <0x0b 0x165 0x0b 0x166>;
  1975. compatible = "rockchip,gpio-bank";
  1976. #interrupt-cells = <0x02>;
  1977. reg = <0x00 0xfe750000 0x00 0x100>;
  1978. phandle = <0x63>;
  1979. #gpio-cells = <0x02>;
  1980. interrupt-controller;
  1981. };
  1982.  
  1983. uart7 {
  1984.  
  1985. uart7m2-xfer {
  1986. rockchip,pins = <0x04 0x03 0x04 0x88 0x04 0x02 0x04 0x88>;
  1987. phandle = <0x204>;
  1988. };
  1989.  
  1990. uart7m0-ctsn {
  1991. rockchip,pins = <0x02 0x12 0x03 0x86>;
  1992. phandle = <0x201>;
  1993. };
  1994.  
  1995. uart7m1-xfer {
  1996. rockchip,pins = <0x03 0x15 0x04 0x88 0x03 0x14 0x04 0x88>;
  1997. phandle = <0x203>;
  1998. };
  1999.  
  2000. uart7m0-xfer {
  2001. rockchip,pins = <0x02 0x05 0x03 0x88 0x02 0x06 0x03 0x88>;
  2002. phandle = <0x6d>;
  2003. };
  2004.  
  2005. uart7m0-rtsn {
  2006. rockchip,pins = <0x02 0x11 0x03 0x86>;
  2007. phandle = <0x202>;
  2008. };
  2009. };
  2010.  
  2011. pcfg-pull-down-drv-level-9 {
  2012. drive-strength = <0x09>;
  2013. bias-pull-down;
  2014. phandle = <0x10c>;
  2015. };
  2016.  
  2017. spi1 {
  2018.  
  2019. spi1m0-cs0 {
  2020. rockchip,pins = <0x02 0x10 0x04 0x86>;
  2021. phandle = <0x1dc>;
  2022. };
  2023.  
  2024. spi1m1-pins {
  2025. rockchip,pins = <0x03 0x13 0x03 0x86 0x03 0x12 0x03 0x86 0x03 0x11 0x03 0x86>;
  2026. phandle = <0x1de>;
  2027. };
  2028.  
  2029. spi1m1-cs0 {
  2030. rockchip,pins = <0x03 0x01 0x03 0x86>;
  2031. phandle = <0x1df>;
  2032. };
  2033.  
  2034. spi1m0-pins {
  2035. rockchip,pins = <0x02 0x0d 0x03 0x86 0x02 0x0e 0x03 0x86 0x02 0x0f 0x04 0x86>;
  2036. phandle = <0x1db>;
  2037. };
  2038.  
  2039. spi1m0-cs1 {
  2040. rockchip,pins = <0x02 0x16 0x03 0x86>;
  2041. phandle = <0x1dd>;
  2042. };
  2043. };
  2044.  
  2045. pcfg-pull-up-drv-level-14 {
  2046. drive-strength = <0x0e>;
  2047. phandle = <0x101>;
  2048. bias-pull-up;
  2049. };
  2050.  
  2051. pcfg-pull-down-drv-level-12 {
  2052. drive-strength = <0x0c>;
  2053. bias-pull-down;
  2054. phandle = <0x10f>;
  2055. };
  2056.  
  2057. pcfg-pull-up-drv-level-1 {
  2058. drive-strength = <0x01>;
  2059. phandle = <0x8c>;
  2060. bias-pull-up;
  2061. };
  2062.  
  2063. pcfg-pull-none-smt {
  2064. bias-disable;
  2065. input-schmitt-enable;
  2066. phandle = <0x8b>;
  2067. };
  2068.  
  2069. pcfg-pull-none-drv-level-11 {
  2070. drive-strength = <0x0b>;
  2071. bias-disable;
  2072. phandle = <0xf0>;
  2073. };
  2074.  
  2075. i2c0 {
  2076.  
  2077. i2c0-xfer {
  2078. rockchip,pins = <0x00 0x09 0x01 0x8b 0x00 0x0a 0x01 0x8b>;
  2079. phandle = <0x10>;
  2080. };
  2081. };
  2082.  
  2083. pwm6 {
  2084.  
  2085. pwm6-pins {
  2086. rockchip,pins = <0x00 0x15 0x01 0x86>;
  2087. phandle = <0x78>;
  2088. };
  2089. };
  2090.  
  2091. pcfg-pull-none-drv-level-4 {
  2092. drive-strength = <0x04>;
  2093. bias-disable;
  2094. phandle = <0xe9>;
  2095. };
  2096.  
  2097. usb2 {
  2098.  
  2099. vcc5v0-usb20-host-en {
  2100. rockchip,pins = <0x04 0x0d 0x00 0x86>;
  2101. phandle = <0x96>;
  2102. };
  2103. };
  2104.  
  2105. pwm11 {
  2106.  
  2107. pwm11m1-pins {
  2108. rockchip,pins = <0x04 0x10 0x03 0x86>;
  2109. phandle = <0x1b9>;
  2110. };
  2111.  
  2112. pwm11m0-pins {
  2113. rockchip,pins = <0x03 0x0e 0x05 0x86>;
  2114. phandle = <0x7d>;
  2115. };
  2116. };
  2117.  
  2118. bt1120 {
  2119.  
  2120. bt1120-pins {
  2121. rockchip,pins = <0x03 0x06 0x02 0x86 0x03 0x01 0x02 0x86 0x03 0x02 0x02 0x86 0x03 0x03 0x02 0x86 0x03 0x04 0x02 0x86 0x03 0x05 0x02 0x86 0x03 0x07 0x02 0x86 0x03 0x08 0x02 0x86 0x03 0x09 0x02 0x86 0x03 0x0a 0x02 0x86 0x03 0x0b 0x02 0x86 0x03 0x0c 0x02 0x86 0x03 0x0d 0x02 0x86 0x03 0x0e 0x02 0x86 0x03 0x11 0x02 0x86 0x03 0x12 0x02 0x86 0x03 0x13 0x02 0x86>;
  2122. phandle = <0x121>;
  2123. };
  2124. };
  2125.  
  2126. uart5 {
  2127.  
  2128. uart5m0-ctsn {
  2129. rockchip,pins = <0x01 0x1f 0x03 0x86>;
  2130. phandle = <0x1fb>;
  2131. };
  2132.  
  2133. uart5m1-xfer {
  2134. rockchip,pins = <0x03 0x13 0x04 0x88 0x03 0x12 0x04 0x88>;
  2135. phandle = <0x1fd>;
  2136. };
  2137.  
  2138. uart5m0-xfer {
  2139. rockchip,pins = <0x02 0x01 0x03 0x88 0x02 0x02 0x03 0x88>;
  2140. phandle = <0x6b>;
  2141. };
  2142.  
  2143. uart5m0-rtsn {
  2144. rockchip,pins = <0x02 0x00 0x03 0x86>;
  2145. phandle = <0x1fc>;
  2146. };
  2147. };
  2148.  
  2149. pcfg-pull-down-drv-level-7 {
  2150. drive-strength = <0x07>;
  2151. bias-pull-down;
  2152. phandle = <0x10a>;
  2153. };
  2154.  
  2155. pcfg-pull-up-drv-level-12 {
  2156. drive-strength = <0x0c>;
  2157. phandle = <0xff>;
  2158. bias-pull-up;
  2159. };
  2160.  
  2161. pcfg-pull-down-drv-level-10 {
  2162. drive-strength = <0x0a>;
  2163. bias-pull-down;
  2164. phandle = <0x10d>;
  2165. };
  2166.  
  2167. flash {
  2168.  
  2169. flash-pins {
  2170. rockchip,pins = <0x01 0x18 0x02 0x86 0x01 0x16 0x03 0x86 0x01 0x1b 0x02 0x86 0x01 0x1c 0x02 0x86 0x01 0x0c 0x02 0x86 0x01 0x0d 0x02 0x86 0x01 0x0e 0x02 0x86 0x01 0x0f 0x02 0x86 0x01 0x10 0x02 0x86 0x01 0x11 0x02 0x86 0x01 0x12 0x02 0x86 0x01 0x13 0x02 0x86 0x01 0x15 0x02 0x86 0x01 0x1a 0x02 0x86 0x01 0x19 0x02 0x86 0x00 0x07 0x01 0x86 0x01 0x17 0x03 0x86 0x01 0x14 0x02 0x86>;
  2171. phandle = <0x13d>;
  2172. };
  2173. };
  2174.  
  2175. vop {
  2176.  
  2177. vopm0-pins {
  2178. rockchip,pins = <0x00 0x13 0x02 0x86>;
  2179. phandle = <0x20c>;
  2180. };
  2181.  
  2182. vopm1-pins {
  2183. rockchip,pins = <0x03 0x14 0x02 0x86>;
  2184. phandle = <0x20d>;
  2185. };
  2186. };
  2187.  
  2188. pwm4 {
  2189.  
  2190. pwm4-pins {
  2191. rockchip,pins = <0x00 0x13 0x01 0x86>;
  2192. phandle = <0x76>;
  2193. };
  2194. };
  2195.  
  2196. pcfg-pull-none-drv-level-2 {
  2197. drive-strength = <0x02>;
  2198. bias-disable;
  2199. phandle = <0x89>;
  2200. };
  2201.  
  2202. vcc_sd {
  2203.  
  2204. vcc-sd-h {
  2205. rockchip,pins = <0x00 0x05 0x00 0x86>;
  2206. phandle = <0x98>;
  2207. };
  2208. };
  2209.  
  2210. uart3 {
  2211.  
  2212. uart3m0-ctsn {
  2213. rockchip,pins = <0x01 0x03 0x02 0x86>;
  2214. phandle = <0x1f5>;
  2215. };
  2216.  
  2217. uart3m1-xfer {
  2218. rockchip,pins = <0x03 0x10 0x04 0x88 0x03 0x0f 0x04 0x88>;
  2219. phandle = <0x1f7>;
  2220. };
  2221.  
  2222. uart3m0-xfer {
  2223. rockchip,pins = <0x01 0x00 0x02 0x88 0x01 0x01 0x02 0x88>;
  2224. phandle = <0x69>;
  2225. };
  2226.  
  2227. uart3m0-rtsn {
  2228. rockchip,pins = <0x01 0x02 0x02 0x86>;
  2229. phandle = <0x1f6>;
  2230. };
  2231. };
  2232.  
  2233. pcfg-pull-down-drv-level-5 {
  2234. drive-strength = <0x05>;
  2235. bias-pull-down;
  2236. phandle = <0x108>;
  2237. };
  2238.  
  2239. pcfg-pull-up-drv-level-8 {
  2240. drive-strength = <0x08>;
  2241. phandle = <0xfb>;
  2242. bias-pull-up;
  2243. };
  2244.  
  2245. pcfg-pull-up-drv-level-10 {
  2246. drive-strength = <0x0a>;
  2247. phandle = <0xfd>;
  2248. bias-pull-up;
  2249. };
  2250.  
  2251. pcfg-output-low {
  2252. phandle = <0x117>;
  2253. output-low;
  2254. };
  2255.  
  2256. hdmitx {
  2257.  
  2258. hdmitx-scl {
  2259. rockchip,pins = <0x04 0x17 0x01 0x86>;
  2260. phandle = <0x47>;
  2261. };
  2262.  
  2263. hdmitx-sda {
  2264. rockchip,pins = <0x04 0x18 0x01 0x86>;
  2265. phandle = <0x48>;
  2266. };
  2267.  
  2268. hdmitxm0-cec {
  2269. rockchip,pins = <0x04 0x19 0x01 0x86>;
  2270. phandle = <0x49>;
  2271. };
  2272.  
  2273. hdmitxm1-cec {
  2274. rockchip,pins = <0x00 0x17 0x01 0x86>;
  2275. phandle = <0x150>;
  2276. };
  2277. };
  2278.  
  2279. sdmmc2 {
  2280.  
  2281. sdmmc2m1-clk {
  2282. rockchip,pins = <0x03 0x06 0x05 0x87>;
  2283. phandle = <0x1d0>;
  2284. };
  2285.  
  2286. sdmmc2m0-det {
  2287. rockchip,pins = <0x03 0x1c 0x03 0x88>;
  2288. phandle = <0x1cd>;
  2289. };
  2290.  
  2291. sdmmc2m0-pwren {
  2292. rockchip,pins = <0x03 0x1d 0x03 0x86>;
  2293. phandle = <0x1ce>;
  2294. };
  2295.  
  2296. sdmmc2m1-det {
  2297. rockchip,pins = <0x03 0x07 0x04 0x88>;
  2298. phandle = <0x1d2>;
  2299. };
  2300.  
  2301. sdmmc2m0-cmd {
  2302. rockchip,pins = <0x03 0x1a 0x03 0x87>;
  2303. phandle = <0x1cc>;
  2304. };
  2305.  
  2306. sdmmc2m1-pwren {
  2307. rockchip,pins = <0x03 0x08 0x04 0x86>;
  2308. phandle = <0x1d3>;
  2309. };
  2310.  
  2311. sdmmc2m1-bus4 {
  2312. rockchip,pins = <0x03 0x01 0x05 0x87 0x03 0x02 0x05 0x87 0x03 0x03 0x05 0x87 0x03 0x04 0x05 0x87>;
  2313. phandle = <0x1cf>;
  2314. };
  2315.  
  2316. sdmmc2m0-clk {
  2317. rockchip,pins = <0x03 0x1b 0x03 0x87>;
  2318. phandle = <0x1cb>;
  2319. };
  2320.  
  2321. sdmmc2m1-cmd {
  2322. rockchip,pins = <0x03 0x05 0x05 0x87>;
  2323. phandle = <0x1d1>;
  2324. };
  2325.  
  2326. sdmmc2m0-bus4 {
  2327. rockchip,pins = <0x03 0x16 0x03 0x87 0x03 0x17 0x03 0x87 0x03 0x18 0x03 0x87 0x03 0x19 0x03 0x87>;
  2328. phandle = <0x1ca>;
  2329. };
  2330. };
  2331.  
  2332. gpio@fe760000 {
  2333. gpio-controller;
  2334. interrupts = <0x00 0x24 0x04>;
  2335. clocks = <0x0b 0x167 0x0b 0x168>;
  2336. compatible = "rockchip,gpio-bank";
  2337. #interrupt-cells = <0x02>;
  2338. reg = <0x00 0xfe760000 0x00 0x100>;
  2339. phandle = <0xe7>;
  2340. #gpio-cells = <0x02>;
  2341. interrupt-controller;
  2342. };
  2343.  
  2344. spi3-hs {
  2345.  
  2346. spi3m1-cs0 {
  2347. rockchip,pins = <0x04 0x16 0x02 0x8c>;
  2348. phandle = <0x222>;
  2349. };
  2350.  
  2351. spi3m0-cs1 {
  2352. rockchip,pins = <0x04 0x07 0x04 0x8c>;
  2353. phandle = <0x220>;
  2354. };
  2355.  
  2356. spi3m1-cs1 {
  2357. rockchip,pins = <0x04 0x19 0x02 0x8c>;
  2358. phandle = <0x223>;
  2359. };
  2360.  
  2361. spi3m1-pins {
  2362. rockchip,pins = <0x04 0x12 0x02 0x8c 0x04 0x15 0x02 0x8c 0x04 0x13 0x02 0x8c>;
  2363. phandle = <0x221>;
  2364. };
  2365.  
  2366. spi3m0-pins {
  2367. rockchip,pins = <0x04 0x0b 0x04 0x8c 0x04 0x08 0x04 0x8c 0x04 0x0a 0x04 0x8c>;
  2368. phandle = <0x21e>;
  2369. };
  2370.  
  2371. spi3m0-cs0 {
  2372. rockchip,pins = <0x04 0x06 0x04 0x8c>;
  2373. phandle = <0x21f>;
  2374. };
  2375. };
  2376.  
  2377. pwm2 {
  2378.  
  2379. pwm2m1-pins {
  2380. rockchip,pins = <0x00 0x0e 0x04 0x86>;
  2381. phandle = <0x1b5>;
  2382. };
  2383.  
  2384. pwm2m0-pins {
  2385. rockchip,pins = <0x00 0x11 0x01 0x86>;
  2386. phandle = <0x1a>;
  2387. };
  2388. };
  2389.  
  2390. pcfg-pull-none-drv-level-0 {
  2391. drive-strength = <0x00>;
  2392. bias-disable;
  2393. phandle = <0xe8>;
  2394. };
  2395.  
  2396. sata1 {
  2397.  
  2398. sata1-pins {
  2399. rockchip,pins = <0x04 0x15 0x03 0x86>;
  2400. phandle = <0x1c1>;
  2401. };
  2402. };
  2403.  
  2404. spi0-hs {
  2405.  
  2406. spi0m0-cs0 {
  2407. rockchip,pins = <0x00 0x16 0x02 0x8c>;
  2408. phandle = <0x20f>;
  2409. };
  2410.  
  2411. spi0m1-cs0 {
  2412. rockchip,pins = <0x02 0x1a 0x03 0x8c>;
  2413. phandle = <0x212>;
  2414. };
  2415.  
  2416. spi0m1-pins {
  2417. rockchip,pins = <0x02 0x1b 0x03 0x8c 0x02 0x18 0x03 0x8c 0x02 0x19 0x03 0x8c>;
  2418. phandle = <0x211>;
  2419. };
  2420.  
  2421. spi0m0-cs1 {
  2422. rockchip,pins = <0x00 0x14 0x02 0x8c>;
  2423. phandle = <0x210>;
  2424. };
  2425.  
  2426. spi0m0-pins {
  2427. rockchip,pins = <0x00 0x0d 0x02 0x8c 0x00 0x15 0x02 0x8c 0x00 0x0e 0x02 0x8c>;
  2428. phandle = <0x20e>;
  2429. };
  2430. };
  2431.  
  2432. pmu {
  2433.  
  2434. pmu-pins {
  2435. rockchip,pins = <0x00 0x05 0x04 0x86 0x00 0x06 0x03 0x86 0x00 0x14 0x04 0x86 0x00 0x15 0x04 0x86 0x00 0x16 0x04 0x86 0x00 0x17 0x04 0x86>;
  2436. phandle = <0x1b2>;
  2437. };
  2438. };
  2439.  
  2440. scr {
  2441.  
  2442. scr-pins {
  2443. rockchip,pins = <0x01 0x02 0x03 0x86 0x01 0x07 0x03 0x88 0x01 0x03 0x03 0x88 0x01 0x05 0x03 0x86>;
  2444. phandle = <0x1c3>;
  2445. };
  2446. };
  2447.  
  2448. uart1 {
  2449.  
  2450. uart1m0-ctsn {
  2451. rockchip,pins = <0x02 0x0e 0x02 0x86>;
  2452. phandle = <0x61>;
  2453. };
  2454.  
  2455. uart1m1-xfer {
  2456. rockchip,pins = <0x03 0x1f 0x04 0x88 0x03 0x1e 0x04 0x88>;
  2457. phandle = <0x1f1>;
  2458. };
  2459.  
  2460. uart1m0-xfer {
  2461. rockchip,pins = <0x02 0x0b 0x02 0x88 0x02 0x0c 0x02 0x88>;
  2462. phandle = <0x60>;
  2463. };
  2464.  
  2465. uart1m1-rtsn {
  2466. rockchip,pins = <0x04 0x0e 0x04 0x86>;
  2467. phandle = <0x1f3>;
  2468. };
  2469.  
  2470. uart1m0-rtsn {
  2471. rockchip,pins = <0x02 0x0d 0x02 0x86>;
  2472. phandle = <0x1f0>;
  2473. };
  2474.  
  2475. uart1m1-ctsn {
  2476. rockchip,pins = <0x04 0x11 0x04 0x86>;
  2477. phandle = <0x1f2>;
  2478. };
  2479. };
  2480.  
  2481. pcfg-pull-down-drv-level-3 {
  2482. drive-strength = <0x03>;
  2483. bias-pull-down;
  2484. phandle = <0x106>;
  2485. };
  2486.  
  2487. pcfg-pull-up-drv-level-6 {
  2488. drive-strength = <0x06>;
  2489. phandle = <0xf9>;
  2490. bias-pull-up;
  2491. };
  2492.  
  2493. i2c5 {
  2494.  
  2495. i2c5m1-xfer {
  2496. rockchip,pins = <0x04 0x17 0x02 0x8b 0x04 0x18 0x02 0x8b>;
  2497. phandle = <0x154>;
  2498. };
  2499.  
  2500. i2c5m0-xfer {
  2501. rockchip,pins = <0x03 0x0b 0x04 0x8b 0x03 0x0c 0x04 0x8b>;
  2502. phandle = <0x5f>;
  2503. };
  2504. };
  2505.  
  2506. pcfg-pull-none-drv-level-9 {
  2507. drive-strength = <0x09>;
  2508. bias-disable;
  2509. phandle = <0xee>;
  2510. };
  2511.  
  2512. sdmmc0 {
  2513.  
  2514. sdmmc0-det {
  2515. rockchip,pins = <0x00 0x04 0x01 0x88>;
  2516. phandle = <0x52>;
  2517. };
  2518.  
  2519. sdmmc0-pwren {
  2520. rockchip,pins = <0x00 0x05 0x01 0x86>;
  2521. phandle = <0x1c4>;
  2522. };
  2523.  
  2524. sdmmc0-bus4 {
  2525. rockchip,pins = <0x01 0x1d 0x01 0x87 0x01 0x1e 0x01 0x87 0x01 0x1f 0x01 0x87 0x02 0x00 0x01 0x87>;
  2526. phandle = <0x4f>;
  2527. };
  2528.  
  2529. sdmmc0-cmd {
  2530. rockchip,pins = <0x02 0x01 0x01 0x87>;
  2531. phandle = <0x51>;
  2532. };
  2533.  
  2534. sdmmc0-clk {
  2535. rockchip,pins = <0x02 0x02 0x01 0x87>;
  2536. phandle = <0x50>;
  2537. };
  2538. };
  2539.  
  2540. pwm0 {
  2541.  
  2542. pwm0m1-pins {
  2543. rockchip,pins = <0x00 0x17 0x02 0x86>;
  2544. phandle = <0x1b3>;
  2545. };
  2546.  
  2547. pwm0m0-pins {
  2548. rockchip,pins = <0x00 0x0f 0x01 0x86>;
  2549. phandle = <0x18>;
  2550. };
  2551. };
  2552.  
  2553. cif {
  2554.  
  2555. cif-dvp-clk {
  2556. rockchip,pins = <0x04 0x11 0x01 0x86 0x04 0x0e 0x01 0x86 0x04 0x0f 0x01 0x86>;
  2557. phandle = <0x12b>;
  2558. };
  2559.  
  2560. cif-clk {
  2561. rockchip,pins = <0x04 0x10 0x01 0x86>;
  2562. phandle = <0x12a>;
  2563. };
  2564.  
  2565. cif-dvp-bus8 {
  2566. rockchip,pins = <0x03 0x16 0x01 0x86 0x03 0x17 0x01 0x86 0x03 0x18 0x01 0x86 0x03 0x19 0x01 0x86 0x03 0x1a 0x01 0x86 0x03 0x1b 0x01 0x86 0x03 0x1c 0x01 0x86 0x03 0x1d 0x01 0x86>;
  2567. phandle = <0x12d>;
  2568. };
  2569.  
  2570. cif-dvp-bus16 {
  2571. rockchip,pins = <0x03 0x1e 0x01 0x86 0x03 0x1f 0x01 0x86 0x04 0x00 0x01 0x86 0x04 0x01 0x01 0x86 0x04 0x02 0x01 0x86 0x04 0x03 0x01 0x86 0x04 0x04 0x01 0x86 0x04 0x05 0x01 0x86>;
  2572. phandle = <0x12c>;
  2573. };
  2574. };
  2575.  
  2576. can1 {
  2577.  
  2578. can1m1-pins {
  2579. rockchip,pins = <0x04 0x12 0x03 0x86 0x04 0x13 0x03 0x86>;
  2580. phandle = <0x127>;
  2581. };
  2582.  
  2583. can1m0-pins {
  2584. rockchip,pins = <0x01 0x00 0x03 0x86 0x01 0x01 0x03 0x86>;
  2585. phandle = <0x126>;
  2586. };
  2587. };
  2588.  
  2589. pcfg-pull-down-drv-level-15 {
  2590. drive-strength = <0x0f>;
  2591. bias-pull-down;
  2592. phandle = <0x112>;
  2593. };
  2594.  
  2595. pcfg-pull-up-smt {
  2596. input-schmitt-enable;
  2597. phandle = <0x113>;
  2598. bias-pull-up;
  2599. };
  2600.  
  2601. pcie20 {
  2602.  
  2603. pcie20-buttonrstn {
  2604. rockchip,pins = <0x00 0x0c 0x03 0x86>;
  2605. phandle = <0x197>;
  2606. };
  2607.  
  2608. pcie20m2-pins {
  2609. rockchip,pins = <0x01 0x08 0x04 0x86 0x01 0x0a 0x04 0x86 0x01 0x09 0x04 0x86>;
  2610. phandle = <0x196>;
  2611. };
  2612.  
  2613. pcie20m1-pins {
  2614. rockchip,pins = <0x02 0x18 0x04 0x86 0x03 0x11 0x04 0x86 0x02 0x19 0x04 0x86>;
  2615. phandle = <0x195>;
  2616. };
  2617.  
  2618. pcie20m0-pins {
  2619. rockchip,pins = <0x00 0x05 0x03 0x86 0x00 0x0e 0x03 0x86 0x00 0x0d 0x03 0x86>;
  2620. phandle = <0x194>;
  2621. };
  2622. };
  2623.  
  2624. pcfg-pull-down-drv-level-1 {
  2625. drive-strength = <0x01>;
  2626. bias-pull-down;
  2627. phandle = <0x104>;
  2628. };
  2629.  
  2630. pcfg-pull-up-drv-level-4 {
  2631. drive-strength = <0x04>;
  2632. phandle = <0xf7>;
  2633. bias-pull-up;
  2634. };
  2635.  
  2636. pcfg-pull-none-drv-level-0-smt {
  2637. drive-strength = <0x00>;
  2638. bias-disable;
  2639. input-schmitt-enable;
  2640. phandle = <0x115>;
  2641. };
  2642.  
  2643. i2s3 {
  2644.  
  2645. i2s3m0-lrck {
  2646. rockchip,pins = <0x03 0x04 0x04 0x86>;
  2647. phandle = <0x185>;
  2648. };
  2649.  
  2650. i2s3m1-mclk {
  2651. rockchip,pins = <0x04 0x12 0x05 0x86>;
  2652. phandle = <0x18b>;
  2653. };
  2654.  
  2655. i2s3m0-sdo {
  2656. rockchip,pins = <0x03 0x05 0x04 0x86>;
  2657. phandle = <0x189>;
  2658. };
  2659.  
  2660. i2s3m0-mclk {
  2661. rockchip,pins = <0x03 0x02 0x04 0x86>;
  2662. phandle = <0x186>;
  2663. };
  2664.  
  2665. i2s3m1-sdo {
  2666. rockchip,pins = <0x04 0x15 0x05 0x86>;
  2667. phandle = <0x18e>;
  2668. };
  2669.  
  2670. i2s3m0-sdi {
  2671. rockchip,pins = <0x03 0x06 0x04 0x86>;
  2672. phandle = <0x188>;
  2673. };
  2674.  
  2675. i2s3m1-sclk {
  2676. rockchip,pins = <0x04 0x13 0x05 0x86>;
  2677. phandle = <0x18c>;
  2678. };
  2679.  
  2680. i2s3m1-sdi {
  2681. rockchip,pins = <0x04 0x16 0x05 0x86>;
  2682. phandle = <0x18d>;
  2683. };
  2684.  
  2685. i2s3m1-lrck {
  2686. rockchip,pins = <0x04 0x14 0x05 0x86>;
  2687. phandle = <0x18a>;
  2688. };
  2689.  
  2690. i2s3m0-sclk {
  2691. rockchip,pins = <0x03 0x03 0x04 0x86>;
  2692. phandle = <0x187>;
  2693. };
  2694. };
  2695.  
  2696. pcfg-pull-none-drv-level-14 {
  2697. drive-strength = <0x0e>;
  2698. bias-disable;
  2699. phandle = <0xf3>;
  2700. };
  2701. };
  2702.  
  2703. mmc@fe2c0000 {
  2704. fifo-depth = <0x100>;
  2705. clock-names = "biu\0ciu\0ciu-drive\0ciu-sample";
  2706. resets = <0x0b 0xd6>;
  2707. interrupts = <0x00 0x63 0x04>;
  2708. clocks = <0x0b 0xb2 0x0b 0xb3 0x0b 0x18c 0x0b 0x18d>;
  2709. compatible = "rockchip,rk3568-dw-mshc\0rockchip,rk3288-dw-mshc";
  2710. status = "disabled";
  2711. reg = <0x00 0xfe2c0000 0x00 0x4000>;
  2712. phandle = <0xbe>;
  2713. max-frequency = <0x8f0d180>;
  2714. reset-names = "reset";
  2715. };
  2716.  
  2717. spdif-dit {
  2718. #sound-dai-cells = <0x00>;
  2719. compatible = "linux,spdif-dit";
  2720. phandle = <0x93>;
  2721. };
  2722.  
  2723. qos@fe158280 {
  2724. compatible = "rockchip,rk3568-qos\0syscon";
  2725. reg = <0x00 0xfe158280 0x00 0x20>;
  2726. phandle = <0x27>;
  2727. };
  2728.  
  2729. serial@fe6a0000 {
  2730. reg-io-width = <0x04>;
  2731. pinctrl-names = "default";
  2732. pinctrl-0 = <0x6c>;
  2733. clock-names = "baudclk\0apb_pclk";
  2734. interrupts = <0x00 0x7a 0x04>;
  2735. clocks = <0x0b 0x133 0x0b 0x130>;
  2736. compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart";
  2737. status = "disabled";
  2738. reg = <0x00 0xfe6a0000 0x00 0x100>;
  2739. phandle = <0xcb>;
  2740. dmas = <0x16 0x0c 0x16 0x0d>;
  2741. reg-shift = <0x02>;
  2742. };
  2743.  
  2744. qos@fe138100 {
  2745. compatible = "rockchip,rk3568-qos\0syscon";
  2746. reg = <0x00 0xfe138100 0x00 0x20>;
  2747. phandle = <0x2c>;
  2748. };
  2749.  
  2750. interrupt-controller@fd400000 {
  2751. mbi-ranges = <0x128 0x18>;
  2752. interrupts = <0x01 0x09 0x04>;
  2753. msi-controller;
  2754. mbi-alias = <0x00 0xfd410000>;
  2755. compatible = "arm,gic-v3";
  2756. #interrupt-cells = <0x03>;
  2757. reg = <0x00 0xfd400000 0x00 0x10000 0x00 0xfd460000 0x00 0x80000>;
  2758. phandle = <0x01>;
  2759. interrupt-controller;
  2760. };
  2761.  
  2762. gpu-opp-table {
  2763. compatible = "operating-points-v2";
  2764. phandle = <0x33>;
  2765.  
  2766. opp-300000000 {
  2767. opp-microvolt = <0xc96a8>;
  2768. opp-hz = <0x00 0x11e1a300>;
  2769. };
  2770.  
  2771. opp-700000000 {
  2772. opp-microvolt = <0xdbba0>;
  2773. opp-hz = <0x00 0x29b92700>;
  2774. };
  2775.  
  2776. opp-200000000 {
  2777. opp-microvolt = <0xc96a8>;
  2778. opp-hz = <0x00 0xbebc200>;
  2779. };
  2780.  
  2781. opp-400000000 {
  2782. opp-microvolt = <0xc96a8>;
  2783. opp-hz = <0x00 0x17d78400>;
  2784. };
  2785.  
  2786. opp-600000000 {
  2787. opp-microvolt = <0xc96a8>;
  2788. opp-hz = <0x00 0x23c34600>;
  2789. };
  2790.  
  2791. opp-800000000 {
  2792. opp-microvolt = <0xf4240>;
  2793. opp-hz = <0x00 0x2faf0800>;
  2794. };
  2795. };
  2796.  
  2797. qos@fe1a8080 {
  2798. compatible = "rockchip,rk3568-qos\0syscon";
  2799. reg = <0x00 0xfe1a8080 0x00 0x20>;
  2800. phandle = <0x21>;
  2801. };
  2802.  
  2803. vcc_sys {
  2804. regulator-max-microvolt = <0x432380>;
  2805. regulator-boot-on;
  2806. regulator-always-on;
  2807. regulator-min-microvolt = <0x432380>;
  2808. regulator-name = "vcc_sys";
  2809. compatible = "regulator-fixed";
  2810. phandle = <0x11>;
  2811. vin-supply = <0x99>;
  2812. };
  2813.  
  2814. watchdog@fe600000 {
  2815. clock-names = "tclk\0pclk";
  2816. interrupts = <0x00 0x95 0x04>;
  2817. clocks = <0x0b 0x116 0x0b 0x115>;
  2818. compatible = "rockchip,rk3568-wdt\0snps,dw-wdt";
  2819. reg = <0x00 0xfe600000 0x00 0x100>;
  2820. phandle = <0xc5>;
  2821. };
  2822.  
  2823. qos@fe128000 {
  2824. compatible = "rockchip,rk3568-qos\0syscon";
  2825. reg = <0x00 0xfe128000 0x00 0x20>;
  2826. phandle = <0x1c>;
  2827. };
  2828.  
  2829. tsadc@fe710000 {
  2830. pinctrl-names = "init\0default\0sleep";
  2831. pinctrl-2 = <0x74>;
  2832. pinctrl-0 = <0x74>;
  2833. clock-names = "tsadc\0apb_pclk";
  2834. rockchip,hw-tshut-polarity = <0x00>;
  2835. assigned-clocks = <0x0b 0x110 0x0b 0x111>;
  2836. assigned-clock-rates = <0x1036640 0xaae60>;
  2837. resets = <0x0b 0x181 0x0b 0x182 0x0b 0x1d7>;
  2838. interrupts = <0x00 0x73 0x04>;
  2839. rockchip,hw-tshut-mode = <0x01>;
  2840. clocks = <0x0b 0x111 0x0b 0x10f>;
  2841. #thermal-sensor-cells = <0x01>;
  2842. compatible = "rockchip,rk3568-tsadc";
  2843. pinctrl-1 = <0x75>;
  2844. status = "okay";
  2845. rockchip,grf = <0x0f>;
  2846. reg = <0x00 0xfe710000 0x00 0x100>;
  2847. phandle = <0x70>;
  2848. rockchip,hw-tshut-temp = <0x17318>;
  2849. };
  2850.  
  2851. external-gmac1-clock {
  2852. clock-output-names = "gmac1_clkin";
  2853. #clock-cells = <0x00>;
  2854. clock-frequency = <0x7735940>;
  2855. compatible = "fixed-clock";
  2856. phandle = <0x39>;
  2857. };
  2858.  
  2859. mmc@fe000000 {
  2860. fifo-depth = <0x100>;
  2861. clock-names = "biu\0ciu\0ciu-drive\0ciu-sample";
  2862. resets = <0x0b 0xeb>;
  2863. interrupts = <0x00 0x64 0x04>;
  2864. clocks = <0x0b 0xc1 0x0b 0xc2 0x0b 0x18e 0x0b 0x18f>;
  2865. compatible = "rockchip,rk3568-dw-mshc\0rockchip,rk3288-dw-mshc";
  2866. status = "disabled";
  2867. reg = <0x00 0xfe000000 0x00 0x4000>;
  2868. phandle = <0xb2>;
  2869. max-frequency = <0x8f0d180>;
  2870. reset-names = "reset";
  2871. };
  2872.  
  2873. rk817-sound {
  2874. simple-audio-card,name = "Analog RK817";
  2875. simple-audio-card,format = "i2s";
  2876. compatible = "simple-audio-card";
  2877. simple-audio-card,mclk-fs = <0x100>;
  2878.  
  2879. simple-audio-card,cpu {
  2880. sound-dai = <0x91>;
  2881. };
  2882.  
  2883. simple-audio-card,codec {
  2884. sound-dai = <0x62>;
  2885. };
  2886. };
  2887.  
  2888. qos@fe138080 {
  2889. compatible = "rockchip,rk3568-qos\0syscon";
  2890. reg = <0x00 0xfe138080 0x00 0x20>;
  2891. phandle = <0x2b>;
  2892. };
  2893.  
  2894. serial@fe670000 {
  2895. reg-io-width = <0x04>;
  2896. pinctrl-names = "default";
  2897. pinctrl-0 = <0x69>;
  2898. clock-names = "baudclk\0apb_pclk";
  2899. interrupts = <0x00 0x77 0x04>;
  2900. clocks = <0x0b 0x127 0x0b 0x124>;
  2901. compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart";
  2902. status = "disabled";
  2903. reg = <0x00 0xfe670000 0x00 0x100>;
  2904. phandle = <0xc8>;
  2905. dmas = <0x16 0x06 0x16 0x07>;
  2906. reg-shift = <0x02>;
  2907. };
  2908.  
  2909. syscon@fdca0000 {
  2910. compatible = "rockchip,rk3568-usb2phy-grf\0syscon";
  2911. reg = <0x00 0xfdca0000 0x00 0x8000>;
  2912. phandle = <0x82>;
  2913. };
  2914.  
  2915. usb2-phy@fe8a0000 {
  2916. rockchip,usbgrf = <0x82>;
  2917. clock-output-names = "clk_usbphy0_480m";
  2918. clock-names = "phyclk";
  2919. interrupts = <0x00 0x87 0x04>;
  2920. clocks = <0x0e 0x13>;
  2921. #clock-cells = <0x00>;
  2922. compatible = "rockchip,rk3568-usb2phy";
  2923. status = "disabled";
  2924. reg = <0x00 0xfe8a0000 0x00 0x10000>;
  2925. phandle = <0xe1>;
  2926.  
  2927. host-port {
  2928. #phy-cells = <0x00>;
  2929. status = "disabled";
  2930. phandle = <0xe2>;
  2931. };
  2932.  
  2933. otg-port {
  2934. #phy-cells = <0x00>;
  2935. status = "disabled";
  2936. phandle = <0xe3>;
  2937. };
  2938. };
  2939.  
  2940. xin32k {
  2941. pinctrl-names = "default";
  2942. clock-output-names = "xin32k";
  2943. pinctrl-0 = <0x0a>;
  2944. #clock-cells = <0x00>;
  2945. clock-frequency = <0x8000>;
  2946. compatible = "fixed-clock";
  2947. phandle = <0x9c>;
  2948. };
  2949.  
  2950. ethernet@fe010000 {
  2951. pinctrl-names = "default";
  2952. phy-supply = <0x3a>;
  2953. phy-mode = "rgmii";
  2954. snps,mixed-burst;
  2955. snps,mtl-rx-config = <0x37>;
  2956. snps,reset-active-low;
  2957. pinctrl-0 = <0x3b 0x3c 0x3d 0x3e 0x3f 0x40>;
  2958. clock-names = "stmmaceth\0mac_clk_rx\0mac_clk_tx\0clk_mac_refout\0aclk_mac\0pclk_mac\0clk_mac_speed\0ptp_ref";
  2959. assigned-clocks = <0x0b 0x189 0x0b 0x187 0x0b 0x186>;
  2960. assigned-clock-parents = <0x0b 0x187 0x0b 0x186 0x39>;
  2961. snps,mtl-tx-config = <0x38>;
  2962. local-mac-address = [b2 00 c4 e0 88 5c];
  2963. resets = <0x0b 0xec>;
  2964. interrupts = <0x00 0x20 0x04 0x00 0x1d 0x04>;
  2965. clocks = <0x0b 0x186 0x0b 0x189 0x0b 0x189 0x0b 0xc7 0x0b 0xc3 0x0b 0xc4 0x0b 0x189 0x0b 0xc8>;
  2966. clock_in_out = "input";
  2967. snps,tso;
  2968. compatible = "rockchip,rk3568-gmac\0snps,dwmac-4.20a";
  2969. status = "okay";
  2970. rockchip,grf = <0x0f>;
  2971. interrupt-names = "macirq\0eth_wake_irq";
  2972. snps,reset-gpio = <0x12 0x13 0x01>;
  2973. reg = <0x00 0xfe010000 0x00 0x10000>;
  2974. rx_delay = <0x10>;
  2975. phandle = <0xb3>;
  2976. phy-handle = <0x41>;
  2977. reset-names = "stmmaceth";
  2978. tx_delay = <0x30>;
  2979. snps,axi-config = <0x36>;
  2980. snps,reset-delays-us = <0x00 0x4e20 0x186a0>;
  2981.  
  2982. mdio {
  2983. #address-cells = <0x01>;
  2984. #size-cells = <0x00>;
  2985. compatible = "snps,dwmac-mdio";
  2986. phandle = <0xb4>;
  2987.  
  2988. ethernet-phy@0 {
  2989. compatible = "ethernet-phy-ieee802.3-c22";
  2990. reg = <0x00>;
  2991. phandle = <0x41>;
  2992. };
  2993. };
  2994.  
  2995. tx-queues-config {
  2996. phandle = <0x38>;
  2997. snps,tx-queues-to-use = <0x01>;
  2998.  
  2999. queue0 {
  3000. };
  3001. };
  3002.  
  3003. stmmac-axi-config {
  3004. snps,wr_osr_lmt = <0x04>;
  3005. phandle = <0x36>;
  3006. snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>;
  3007. snps,rd_osr_lmt = <0x08>;
  3008. };
  3009.  
  3010. rx-queues-config {
  3011. snps,rx-queues-to-use = <0x01>;
  3012. phandle = <0x37>;
  3013.  
  3014. queue0 {
  3015. };
  3016. };
  3017. };
  3018.  
  3019. display-subsystem {
  3020. ports = <0x42>;
  3021. compatible = "rockchip,display-subsystem";
  3022. phandle = <0xb5>;
  3023. };
  3024.  
  3025. i2c@fe5d0000 {
  3026. pinctrl-names = "default";
  3027. #address-cells = <0x01>;
  3028. pinctrl-0 = <0x5e>;
  3029. clock-names = "i2c\0pclk";
  3030. interrupts = <0x00 0x32 0x04>;
  3031. clocks = <0x0b 0x14e 0x0b 0x14d>;
  3032. #size-cells = <0x00>;
  3033. compatible = "rockchip,rk3568-i2c\0rockchip,rk3399-i2c";
  3034. status = "disabled";
  3035. reg = <0x00 0xfe5d0000 0x00 0x1000>;
  3036. phandle = <0xc3>;
  3037. };
  3038.  
  3039. clock-controller@fdd00000 {
  3040. #reset-cells = <0x01>;
  3041. #clock-cells = <0x01>;
  3042. compatible = "rockchip,rk3568-pmucru";
  3043. reg = <0x00 0xfdd00000 0x00 0x1000>;
  3044. phandle = <0x0e>;
  3045. };
  3046.  
  3047. thermal-zones {
  3048. phandle = <0xcf>;
  3049.  
  3050. cpu-thermal {
  3051. polling-delay = <0x3e8>;
  3052. polling-delay-passive = <0x64>;
  3053. thermal-sensors = <0x70 0x00>;
  3054. phandle = <0xd0>;
  3055.  
  3056. trips {
  3057.  
  3058. cpu_crit {
  3059. temperature = <0x17318>;
  3060. hysteresis = <0x7d0>;
  3061. type = "critical";
  3062. phandle = <0xd2>;
  3063. };
  3064.  
  3065. cpu_alert0 {
  3066. temperature = <0x11170>;
  3067. hysteresis = <0x7d0>;
  3068. type = "passive";
  3069. phandle = <0x71>;
  3070. };
  3071.  
  3072. cpu_hot {
  3073. temperature = <0xd6d8>;
  3074. hysteresis = <0x7d0>;
  3075. type = "active";
  3076. phandle = <0x72>;
  3077. };
  3078.  
  3079. cpu_alert1 {
  3080. temperature = <0x124f8>;
  3081. hysteresis = <0x7d0>;
  3082. type = "passive";
  3083. phandle = <0xd1>;
  3084. };
  3085. };
  3086.  
  3087. cooling-maps {
  3088.  
  3089. map0 {
  3090. trip = <0x71>;
  3091. cooling-device = <0x06 0xffffffff 0xffffffff 0x07 0xffffffff 0xffffffff 0x08 0xffffffff 0xffffffff 0x09 0xffffffff 0xffffffff>;
  3092. };
  3093.  
  3094. map1 {
  3095. trip = <0x72>;
  3096. cooling-device = <0x73 0xffffffff 0xffffffff>;
  3097. };
  3098. };
  3099. };
  3100.  
  3101. gpu-thermal {
  3102. polling-delay = <0x3e8>;
  3103. polling-delay-passive = <0x14>;
  3104. thermal-sensors = <0x70 0x01>;
  3105. phandle = <0xd3>;
  3106. };
  3107. };
  3108.  
  3109. qos@fe158200 {
  3110. compatible = "rockchip,rk3568-qos\0syscon";
  3111. reg = <0x00 0xfe158200 0x00 0x20>;
  3112. phandle = <0x26>;
  3113. };
  3114.  
  3115. spdif-sound {
  3116. simple-audio-card,name = "SPDIF";
  3117. compatible = "simple-audio-card";
  3118. phandle = <0x22e>;
  3119.  
  3120. simple-audio-card,cpu {
  3121. sound-dai = <0x92>;
  3122. };
  3123.  
  3124. simple-audio-card,codec {
  3125. sound-dai = <0x93>;
  3126. };
  3127. };
  3128.  
  3129. dmac@fe530000 {
  3130. clock-names = "apb_pclk";
  3131. interrupts = <0x00 0x0e 0x04 0x00 0x0d 0x04>;
  3132. clocks = <0x0b 0x10d>;
  3133. arm,pl330-periph-burst;
  3134. compatible = "arm,pl330\0arm,primecell";
  3135. reg = <0x00 0xfe530000 0x00 0x4000>;
  3136. phandle = <0x16>;
  3137. #dma-cells = <0x01>;
  3138. };
  3139.  
  3140. qos@fe1a8000 {
  3141. compatible = "rockchip,rk3568-qos\0syscon";
  3142. reg = <0x00 0xfe1a8000 0x00 0x20>;
  3143. phandle = <0x20>;
  3144. };
  3145.  
  3146. vcc3v3_sd {
  3147. regulator-max-microvolt = <0x325aa0>;
  3148. pinctrl-names = "default";
  3149. regulator-boot-on;
  3150. gpio = <0x12 0x05 0x01>;
  3151. pinctrl-0 = <0x98>;
  3152. enable-active-low;
  3153. regulator-min-microvolt = <0x325aa0>;
  3154. regulator-name = "vcc3v3_sd";
  3155. compatible = "regulator-fixed";
  3156. phandle = <0x53>;
  3157. vin-supply = <0x3a>;
  3158. };
  3159.  
  3160. serial@fe6b0000 {
  3161. reg-io-width = <0x04>;
  3162. pinctrl-names = "default";
  3163. pinctrl-0 = <0x6d>;
  3164. clock-names = "baudclk\0apb_pclk";
  3165. interrupts = <0x00 0x7b 0x04>;
  3166. clocks = <0x0b 0x137 0x0b 0x134>;
  3167. compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart";
  3168. status = "disabled";
  3169. reg = <0x00 0xfe6b0000 0x00 0x100>;
  3170. phandle = <0xcc>;
  3171. dmas = <0x16 0x0e 0x16 0x0f>;
  3172. reg-shift = <0x02>;
  3173. };
  3174.  
  3175. qos@fe148100 {
  3176. compatible = "rockchip,rk3568-qos\0syscon";
  3177. reg = <0x00 0xfe148100 0x00 0x20>;
  3178. phandle = <0x1f>;
  3179. };
  3180.  
  3181. leds {
  3182. compatible = "gpio-leds";
  3183.  
  3184. led-diy {
  3185. linux,default-trigger = "heartbeat";
  3186. pinctrl-names = "default";
  3187. pinctrl-0 = <0x90>;
  3188. label = "diy-led";
  3189. default-state = "on";
  3190. retain-state-suspended;
  3191. gpios = <0x12 0x1c 0x00>;
  3192. };
  3193.  
  3194. led-work {
  3195. pinctrl-names = "default";
  3196. pinctrl-0 = <0x8f>;
  3197. label = "work-led";
  3198. default-state = "off";
  3199. retain-state-suspended;
  3200. gpios = <0x12 0x1b 0x00>;
  3201. };
  3202. };
  3203.  
  3204. psci {
  3205. method = "smc";
  3206. compatible = "arm,psci-1.0";
  3207. };
  3208.  
  3209. usb@fd800000 {
  3210. phy-names = "usb";
  3211. interrupts = <0x00 0x82 0x04>;
  3212. clocks = <0x0b 0xbd 0x0b 0xbe 0x0b 0xbc>;
  3213. compatible = "generic-ehci";
  3214. status = "okay";
  3215. phys = <0x0c>;
  3216. reg = <0x00 0xfd800000 0x00 0x40000>;
  3217. phandle = <0x9d>;
  3218. };
  3219.  
  3220. xin24m {
  3221. clock-output-names = "xin24m";
  3222. #clock-cells = <0x00>;
  3223. clock-frequency = <0x16e3600>;
  3224. compatible = "fixed-clock";
  3225. phandle = <0x9b>;
  3226. };
  3227.  
  3228. qos@fe158180 {
  3229. compatible = "rockchip,rk3568-qos\0syscon";
  3230. reg = <0x00 0xfe158180 0x00 0x20>;
  3231. phandle = <0x25>;
  3232. };
  3233.  
  3234. qos@fe180000 {
  3235. compatible = "rockchip,rk3568-qos\0syscon";
  3236. reg = <0x00 0xfe180000 0x00 0x20>;
  3237. phandle = <0xbc>;
  3238. };
  3239.  
  3240. usb@fd840000 {
  3241. phy-names = "usb";
  3242. interrupts = <0x00 0x83 0x04>;
  3243. clocks = <0x0b 0xbd 0x0b 0xbe 0x0b 0xbc>;
  3244. compatible = "generic-ohci";
  3245. status = "okay";
  3246. phys = <0x0c>;
  3247. reg = <0x00 0xfd840000 0x00 0x40000>;
  3248. phandle = <0x9e>;
  3249. };
  3250.  
  3251. hdmi@fe0a0000 {
  3252. power-domains = <0x34 0x09>;
  3253. reg-io-width = <0x04>;
  3254. pinctrl-names = "default";
  3255. avdd-1v8-supply = <0x4b>;
  3256. pinctrl-0 = <0x47 0x48 0x49>;
  3257. clock-names = "iahb\0isfr\0cec\0hclk";
  3258. interrupts = <0x00 0x2d 0x04>;
  3259. clocks = <0x0b 0xe6 0x0b 0xe7 0x0b 0x193 0x0b 0xde>;
  3260. #sound-dai-cells = <0x00>;
  3261. compatible = "rockchip,rk3568-dw-hdmi";
  3262. status = "okay";
  3263. rockchip,grf = <0x0f>;
  3264. reg = <0x00 0xfe0a0000 0x00 0x20000>;
  3265. phandle = <0xba>;
  3266. avdd-0v9-supply = <0x4a>;
  3267.  
  3268. ports {
  3269. #address-cells = <0x01>;
  3270. #size-cells = <0x00>;
  3271.  
  3272. port@0 {
  3273. #address-cells = <0x01>;
  3274. #size-cells = <0x00>;
  3275. reg = <0x00>;
  3276. phandle = <0xbb>;
  3277.  
  3278. endpoint@1 {
  3279. remote-endpoint = <0x4d>;
  3280. status = "disabled";
  3281. reg = <0x01>;
  3282. phandle = <0x45>;
  3283. };
  3284.  
  3285. endpoint@2 {
  3286. remote-endpoint = <0x4e>;
  3287. status = "disabled";
  3288. reg = <0x02>;
  3289. phandle = <0x46>;
  3290. };
  3291.  
  3292. endpoint@0 {
  3293. remote-endpoint = <0x4c>;
  3294. status = "okay";
  3295. reg = <0x00>;
  3296. phandle = <0x44>;
  3297. };
  3298. };
  3299. };
  3300. };
  3301.  
  3302. power-management@fdd90000 {
  3303. compatible = "rockchip,rk3568-pmu\0syscon\0simple-mfd";
  3304. reg = <0x00 0xfdd90000 0x00 0x1000>;
  3305. phandle = <0xb0>;
  3306.  
  3307. power-controller {
  3308. #address-cells = <0x01>;
  3309. #size-cells = <0x00>;
  3310. #power-domain-cells = <0x01>;
  3311. compatible = "rockchip,rk3568-power-controller";
  3312. phandle = <0x34>;
  3313.  
  3314. power-domain@9 {
  3315. clocks = <0x0b 0xda 0x0b 0xdb 0x0b 0xdc>;
  3316. #power-domain-cells = <0x00>;
  3317. reg = <0x09>;
  3318. pm_qos = <0x20 0x21 0x22>;
  3319. };
  3320.  
  3321. power-domain@7 {
  3322. clocks = <0x0b 0x19 0x0b 0x1a>;
  3323. #power-domain-cells = <0x00>;
  3324. reg = <0x07>;
  3325. pm_qos = <0x1c>;
  3326. };
  3327.  
  3328. power-domain@15 {
  3329. clocks = <0x0b 0x7f>;
  3330. #power-domain-cells = <0x00>;
  3331. reg = <0x0f>;
  3332. pm_qos = <0x2e 0x2f 0x30 0x31 0x32>;
  3333. };
  3334.  
  3335. power-domain@13 {
  3336. clocks = <0x0b 0x107>;
  3337. #power-domain-cells = <0x00>;
  3338. reg = <0x0d>;
  3339. pm_qos = <0x2a>;
  3340. };
  3341.  
  3342. power-domain@11 {
  3343. clocks = <0x0b 0xed>;
  3344. #power-domain-cells = <0x00>;
  3345. reg = <0x0b>;
  3346. pm_qos = <0x29>;
  3347. };
  3348.  
  3349. power-domain@8 {
  3350. clocks = <0x0b 0xcc 0x0b 0xcd>;
  3351. #power-domain-cells = <0x00>;
  3352. reg = <0x08>;
  3353. pm_qos = <0x1d 0x1e 0x1f>;
  3354. };
  3355.  
  3356. power-domain@14 {
  3357. clocks = <0x0b 0x102>;
  3358. #power-domain-cells = <0x00>;
  3359. reg = <0x0e>;
  3360. pm_qos = <0x2b 0x2c 0x2d>;
  3361. };
  3362.  
  3363. power-domain@10 {
  3364. clocks = <0x0b 0xf1 0x0b 0xf2>;
  3365. #power-domain-cells = <0x00>;
  3366. reg = <0x0a>;
  3367. pm_qos = <0x23 0x24 0x25 0x26 0x27 0x28>;
  3368. };
  3369. };
  3370. };
  3371.  
  3372. vcc5v0_usb20_host {
  3373. regulator-max-microvolt = <0x4c4b40>;
  3374. pinctrl-names = "default";
  3375. gpio = <0x95 0x0d 0x00>;
  3376. pinctrl-0 = <0x96>;
  3377. enable-active-high;
  3378. regulator-min-microvolt = <0x4c4b40>;
  3379. regulator-name = "vcc5v0_usb20_host";
  3380. compatible = "regulator-fixed";
  3381. phandle = <0x84>;
  3382. vin-supply = <0x97>;
  3383. };
  3384.  
  3385. qos@fe148080 {
  3386. compatible = "rockchip,rk3568-qos\0syscon";
  3387. reg = <0x00 0xfe148080 0x00 0x20>;
  3388. phandle = <0x1e>;
  3389. };
  3390.  
  3391. serial@fe680000 {
  3392. reg-io-width = <0x04>;
  3393. pinctrl-names = "default";
  3394. pinctrl-0 = <0x6a>;
  3395. clock-names = "baudclk\0apb_pclk";
  3396. interrupts = <0x00 0x78 0x04>;
  3397. clocks = <0x0b 0x12b 0x0b 0x128>;
  3398. compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart";
  3399. status = "disabled";
  3400. reg = <0x00 0xfe680000 0x00 0x100>;
  3401. phandle = <0xc9>;
  3402. dmas = <0x16 0x08 0x16 0x09>;
  3403. reg-shift = <0x02>;
  3404. };
  3405.  
  3406. usb@fd880000 {
  3407. phy-names = "usb";
  3408. interrupts = <0x00 0x85 0x04>;
  3409. clocks = <0x0b 0xbf 0x0b 0xc0 0x0b 0xbc>;
  3410. compatible = "generic-ehci";
  3411. status = "okay";
  3412. phys = <0x0d>;
  3413. reg = <0x00 0xfd880000 0x00 0x40000>;
  3414. phandle = <0x9f>;
  3415. };
  3416.  
  3417. qos@fe190400 {
  3418. compatible = "rockchip,rk3568-qos\0syscon";
  3419. reg = <0x00 0xfe190400 0x00 0x20>;
  3420. phandle = <0x32>;
  3421. };
  3422.  
  3423. saradc@fe720000 {
  3424. clock-names = "saradc\0apb_pclk";
  3425. resets = <0x0b 0x180>;
  3426. interrupts = <0x00 0x5d 0x04>;
  3427. clocks = <0x0b 0x113 0x0b 0x112>;
  3428. #io-channel-cells = <0x01>;
  3429. compatible = "rockchip,rk3568-saradc\0rockchip,rk3399-saradc";
  3430. status = "disabled";
  3431. reg = <0x00 0xfe720000 0x00 0x100>;
  3432. phandle = <0xd4>;
  3433. reset-names = "saradc-apb";
  3434. };
  3435.  
  3436. usb2-phy@fe8b0000 {
  3437. rockchip,usbgrf = <0x83>;
  3438. clock-output-names = "clk_usbphy1_480m";
  3439. clock-names = "phyclk";
  3440. interrupts = <0x00 0x88 0x04>;
  3441. clocks = <0x0e 0x15>;
  3442. #clock-cells = <0x00>;
  3443. compatible = "rockchip,rk3568-usb2phy";
  3444. status = "okay";
  3445. reg = <0x00 0xfe8b0000 0x00 0x10000>;
  3446. phandle = <0xe4>;
  3447.  
  3448. host-port {
  3449. phy-supply = <0x84>;
  3450. #phy-cells = <0x00>;
  3451. status = "okay";
  3452. phandle = <0x0d>;
  3453. };
  3454.  
  3455. otg-port {
  3456. phy-supply = <0x84>;
  3457. #phy-cells = <0x00>;
  3458. status = "okay";
  3459. phandle = <0x0c>;
  3460. };
  3461. };
  3462.  
  3463. syscon@fdca8000 {
  3464. compatible = "rockchip,rk3568-usb2phy-grf\0syscon";
  3465. reg = <0x00 0xfdca8000 0x00 0x8000>;
  3466. phandle = <0x83>;
  3467. };
  3468.  
  3469. i2c@fe5a0000 {
  3470. pinctrl-names = "default";
  3471. #address-cells = <0x01>;
  3472. pinctrl-0 = <0x5b>;
  3473. clock-names = "i2c\0pclk";
  3474. interrupts = <0x00 0x2f 0x04>;
  3475. clocks = <0x0b 0x148 0x0b 0x147>;
  3476. #size-cells = <0x00>;
  3477. compatible = "rockchip,rk3568-i2c\0rockchip,rk3399-i2c";
  3478. status = "disabled";
  3479. reg = <0x00 0xfe5a0000 0x00 0x1000>;
  3480. phandle = <0xc0>;
  3481. };
  3482.  
  3483. sram@10f000 {
  3484. #address-cells = <0x01>;
  3485. #size-cells = <0x01>;
  3486. compatible = "mmio-sram";
  3487. ranges = <0x00 0x00 0x10f000 0x100>;
  3488. reg = <0x00 0x10f000 0x00 0x100>;
  3489.  
  3490. sram@0 {
  3491. compatible = "arm,scmi-shmem";
  3492. reg = <0x00 0x100>;
  3493. phandle = <0x05>;
  3494. };
  3495. };
  3496.  
  3497. i2c@fe5e0000 {
  3498. pinctrl-names = "default";
  3499. #address-cells = <0x01>;
  3500. pinctrl-0 = <0x5f>;
  3501. clock-names = "i2c\0pclk";
  3502. interrupts = <0x00 0x33 0x04>;
  3503. clocks = <0x0b 0x150 0x0b 0x14f>;
  3504. #size-cells = <0x00>;
  3505. compatible = "rockchip,rk3568-i2c\0rockchip,rk3399-i2c";
  3506. status = "disabled";
  3507. reg = <0x00 0xfe5e0000 0x00 0x1000>;
  3508. phandle = <0xc4>;
  3509. };
  3510.  
  3511. qos@fe190380 {
  3512. compatible = "rockchip,rk3568-qos\0syscon";
  3513. reg = <0x00 0xfe190380 0x00 0x20>;
  3514. phandle = <0x31>;
  3515. };
  3516.  
  3517. vbus {
  3518. regulator-max-microvolt = <0x4c4b40>;
  3519. regulator-boot-on;
  3520. regulator-always-on;
  3521. regulator-min-microvolt = <0x4c4b40>;
  3522. regulator-name = "vbus";
  3523. compatible = "regulator-fixed";
  3524. phandle = <0x99>;
  3525. vin-supply = <0x94>;
  3526. };
  3527.  
  3528. timer {
  3529. arm,no-tick-in-suspend;
  3530. interrupts = <0x01 0x0d 0x04 0x01 0x0e 0x04 0x01 0x0b 0x04 0x01 0x0a 0x04>;
  3531. compatible = "arm,armv8-timer";
  3532. };
  3533.  
  3534. opp-table-0 {
  3535. opp-shared;
  3536. compatible = "operating-points-v2";
  3537. phandle = <0x03>;
  3538.  
  3539. opp-1800000000 {
  3540. opp-microvolt = <0x100590 0x100590 0x118c30>;
  3541. opp-hz = <0x00 0x6b49d200>;
  3542. };
  3543.  
  3544. opp-1608000000 {
  3545. opp-microvolt = <0xee098 0xee098 0x118c30>;
  3546. opp-hz = <0x00 0x5fd82200>;
  3547. };
  3548.  
  3549. opp-1104000000 {
  3550. opp-microvolt = <0xdbba0 0xdbba0 0x118c30>;
  3551. opp-hz = <0x00 0x41cdb400>;
  3552. };
  3553.  
  3554. opp-816000000 {
  3555. opp-microvolt = <0xdbba0 0xdbba0 0x118c30>;
  3556. opp-hz = <0x00 0x30a32c00>;
  3557. opp-suspend;
  3558. };
  3559.  
  3560. opp-600000000 {
  3561. opp-microvolt = <0xdbba0 0xdbba0 0x118c30>;
  3562. opp-hz = <0x00 0x23c34600>;
  3563. };
  3564.  
  3565. opp-1416000000 {
  3566. opp-microvolt = <0xdbba0 0xdbba0 0x118c30>;
  3567. opp-hz = <0x00 0x54667200>;
  3568. };
  3569.  
  3570. opp-408000000 {
  3571. opp-microvolt = <0xdbba0 0xdbba0 0x118c30>;
  3572. opp-hz = <0x00 0x18519600>;
  3573. clock-latency-ns = <0x9c40>;
  3574. };
  3575. };
  3576.  
  3577. i2s@fe410000 {
  3578. pinctrl-names = "default";
  3579. pinctrl-0 = <0x57 0x58 0x59 0x5a>;
  3580. clock-names = "mclk_tx\0mclk_rx\0hclk";
  3581. assigned-clocks = <0x0b 0x45 0x0b 0x49>;
  3582. assigned-clock-rates = <0x46cf7100 0x46cf7100>;
  3583. resets = <0x0b 0x52 0x0b 0x53>;
  3584. interrupts = <0x00 0x35 0x04>;
  3585. clocks = <0x0b 0x47 0x0b 0x4b 0x0b 0x3a>;
  3586. dma-names = "rx\0tx";
  3587. #sound-dai-cells = <0x00>;
  3588. compatible = "rockchip,rk3568-i2s-tdm";
  3589. status = "okay";
  3590. rockchip,grf = <0x0f>;
  3591. reg = <0x00 0xfe410000 0x00 0x1000>;
  3592. rockchip,trcm-sync-tx-only;
  3593. phandle = <0x91>;
  3594. dmas = <0x55 0x03 0x55 0x02>;
  3595. reset-names = "tx-m\0rx-m";
  3596. };
  3597.  
  3598. pwm@fe6e0030 {
  3599. pinctrl-names = "active";
  3600. pinctrl-0 = <0x79>;
  3601. clock-names = "pwm\0pclk";
  3602. clocks = <0x0b 0x15a 0x0b 0x159>;
  3603. #pwm-cells = <0x03>;
  3604. compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
  3605. status = "disabled";
  3606. reg = <0x00 0xfe6e0030 0x00 0x10>;
  3607. phandle = <0xd8>;
  3608. };
  3609.  
  3610. serial@fe6c0000 {
  3611. reg-io-width = <0x04>;
  3612. pinctrl-names = "default";
  3613. pinctrl-0 = <0x6e>;
  3614. clock-names = "baudclk\0apb_pclk";
  3615. interrupts = <0x00 0x7c 0x04>;
  3616. clocks = <0x0b 0x13b 0x0b 0x138>;
  3617. compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart";
  3618. status = "disabled";
  3619. reg = <0x00 0xfe6c0000 0x00 0x100>;
  3620. phandle = <0xcd>;
  3621. dmas = <0x16 0x10 0x16 0x11>;
  3622. reg-shift = <0x02>;
  3623. };
  3624.  
  3625. usb@fd8c0000 {
  3626. phy-names = "usb";
  3627. interrupts = <0x00 0x86 0x04>;
  3628. clocks = <0x0b 0xbf 0x0b 0xc0 0x0b 0xbc>;
  3629. compatible = "generic-ohci";
  3630. status = "okay";
  3631. phys = <0x0d>;
  3632. reg = <0x00 0xfd8c0000 0x00 0x40000>;
  3633. phandle = <0xa0>;
  3634. };
  3635.  
  3636. qos@fe158100 {
  3637. compatible = "rockchip,rk3568-qos\0syscon";
  3638. reg = <0x00 0xfe158100 0x00 0x20>;
  3639. phandle = <0x24>;
  3640. };
  3641.  
  3642. pwm@fe6e0020 {
  3643. pinctrl-names = "active";
  3644. pinctrl-0 = <0x78>;
  3645. clock-names = "pwm\0pclk";
  3646. clocks = <0x0b 0x15a 0x0b 0x159>;
  3647. #pwm-cells = <0x03>;
  3648. compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
  3649. status = "disabled";
  3650. reg = <0x00 0xfe6e0020 0x00 0x10>;
  3651. phandle = <0xd7>;
  3652. };
  3653.  
  3654. qos@fe150000 {
  3655. compatible = "rockchip,rk3568-qos\0syscon";
  3656. reg = <0x00 0xfe150000 0x00 0x20>;
  3657. phandle = <0x29>;
  3658. };
  3659.  
  3660. aliases {
  3661. i2c3 = "/i2c@fe5c0000";
  3662. ethernet0 = "/ethernet@fe010000";
  3663. gpio0 = "/pinctrl/gpio@fdd60000";
  3664. serial7 = "/serial@fe6b0000";
  3665. i2c1 = "/i2c@fe5a0000";
  3666. serial5 = "/serial@fe690000";
  3667. mmc1 = "/mmc@fe310000";
  3668. serial3 = "/serial@fe670000";
  3669. serial1 = "/serial@fe650000";
  3670. gpio3 = "/pinctrl/gpio@fe760000";
  3671. i2c4 = "/i2c@fe5d0000";
  3672. gpio1 = "/pinctrl/gpio@fe740000";
  3673. serial8 = "/serial@fe6c0000";
  3674. i2c2 = "/i2c@fe5b0000";
  3675. serial6 = "/serial@fe6a0000";
  3676. i2c0 = "/i2c@fdd40000";
  3677. serial4 = "/serial@fe680000";
  3678. mmc0 = "/mmc@fe2b0000";
  3679. serial2 = "/serial@fe660000";
  3680. gpio4 = "/pinctrl/gpio@fe770000";
  3681. i2c5 = "/i2c@fe5e0000";
  3682. serial0 = "/serial@fdd50000";
  3683. gpio2 = "/pinctrl/gpio@fe750000";
  3684. serial9 = "/serial@fe6d0000";
  3685. };
  3686.  
  3687. gpio_fan {
  3688. gpio-fan,speed-map = <0x00 0x00 0x1194 0x01>;
  3689. compatible = "gpio-fan";
  3690. phandle = <0x73>;
  3691. gpios = <0x12 0x1d 0x00>;
  3692. #cooling-cells = <0x02>;
  3693. };
  3694.  
  3695. pwm@fe6e0010 {
  3696. pinctrl-names = "active";
  3697. pinctrl-0 = <0x77>;
  3698. clock-names = "pwm\0pclk";
  3699. clocks = <0x0b 0x15a 0x0b 0x159>;
  3700. #pwm-cells = <0x03>;
  3701. compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
  3702. status = "disabled";
  3703. reg = <0x00 0xfe6e0010 0x00 0x10>;
  3704. phandle = <0xd6>;
  3705. };
  3706.  
  3707. qos@fe148000 {
  3708. compatible = "rockchip,rk3568-qos\0syscon";
  3709. reg = <0x00 0xfe148000 0x00 0x20>;
  3710. phandle = <0x1d>;
  3711. };
  3712.  
  3713. firmware {
  3714.  
  3715. scmi {
  3716. shmem = <0x05>;
  3717. #address-cells = <0x01>;
  3718. #size-cells = <0x00>;
  3719. compatible = "arm,scmi-smc";
  3720. phandle = <0x9a>;
  3721. arm,smc-id = <0x82000010>;
  3722.  
  3723. protocol@14 {
  3724. #clock-cells = <0x01>;
  3725. reg = <0x14>;
  3726. phandle = <0x02>;
  3727. };
  3728. };
  3729. };
  3730.  
  3731. serial@fe650000 {
  3732. reg-io-width = <0x04>;
  3733. pinctrl-names = "default";
  3734. pinctrl-0 = <0x60 0x61>;
  3735. clock-names = "baudclk\0apb_pclk";
  3736. interrupts = <0x00 0x75 0x04>;
  3737. clocks = <0x0b 0x11f 0x0b 0x11c>;
  3738. uart-has-rtscts;
  3739. compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart";
  3740. status = "okay";
  3741. reg = <0x00 0xfe650000 0x00 0x100>;
  3742. phandle = <0xc6>;
  3743. dmas = <0x16 0x02 0x16 0x03>;
  3744. reg-shift = <0x02>;
  3745.  
  3746. bluetooth {
  3747. device-wake-gpios = <0x63 0x11 0x00>;
  3748. pinctrl-names = "default";
  3749. pinctrl-0 = <0x64 0x65 0x66>;
  3750. clock-names = "lpo";
  3751. host-wake-gpios = <0x63 0x10 0x00>;
  3752. clocks = <0x62 0x01>;
  3753. shutdown-gpios = <0x63 0x0f 0x00>;
  3754. compatible = "brcm,bcm43438-bt";
  3755. vddio-supply = <0x67>;
  3756. vbat-supply = <0x11>;
  3757. };
  3758. };
  3759.  
  3760. qos@fe190000 {
  3761. compatible = "rockchip,rk3568-qos\0syscon";
  3762. reg = <0x00 0xfe190000 0x00 0x20>;
  3763. phandle = <0x2e>;
  3764. };
  3765.  
  3766. pwm@fe6e0000 {
  3767. pinctrl-names = "active";
  3768. pinctrl-0 = <0x76>;
  3769. clock-names = "pwm\0pclk";
  3770. clocks = <0x0b 0x15a 0x0b 0x159>;
  3771. #pwm-cells = <0x03>;
  3772. compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
  3773. status = "disabled";
  3774. reg = <0x00 0xfe6e0000 0x00 0x10>;
  3775. phandle = <0xd5>;
  3776. };
  3777.  
  3778. pwm@fe700030 {
  3779. pinctrl-names = "active";
  3780. pinctrl-0 = <0x81>;
  3781. clock-names = "pwm\0pclk";
  3782. clocks = <0x0b 0x160 0x0b 0x15f>;
  3783. #pwm-cells = <0x03>;
  3784. compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
  3785. status = "disabled";
  3786. reg = <0x00 0xfe700030 0x00 0x10>;
  3787. phandle = <0xe0>;
  3788. };
  3789.  
  3790. serial@fe690000 {
  3791. reg-io-width = <0x04>;
  3792. pinctrl-names = "default";
  3793. pinctrl-0 = <0x6b>;
  3794. clock-names = "baudclk\0apb_pclk";
  3795. interrupts = <0x00 0x79 0x04>;
  3796. clocks = <0x0b 0x12f 0x0b 0x12c>;
  3797. compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart";
  3798. status = "disabled";
  3799. reg = <0x00 0xfe690000 0x00 0x100>;
  3800. phandle = <0xca>;
  3801. dmas = <0x16 0x0a 0x16 0x0b>;
  3802. reg-shift = <0x02>;
  3803. };
  3804.  
  3805. i2c@fdd40000 {
  3806. pinctrl-names = "default";
  3807. #address-cells = <0x01>;
  3808. pinctrl-0 = <0x10>;
  3809. clock-names = "i2c\0pclk";
  3810. interrupts = <0x00 0x2e 0x04>;
  3811. clocks = <0x0e 0x07 0x0e 0x2d>;
  3812. #size-cells = <0x00>;
  3813. compatible = "rockchip,rk3568-i2c\0rockchip,rk3399-i2c";
  3814. status = "okay";
  3815. reg = <0x00 0xfdd40000 0x00 0x1000>;
  3816. phandle = <0xa2>;
  3817.  
  3818. regulator@1c {
  3819. regulator-max-microvolt = <0x118c30>;
  3820. regulator-boot-on;
  3821. regulator-always-on;
  3822. regulator-min-microvolt = "\0\f5";
  3823. regulator-name = "vdd_cpu";
  3824. regulator-ramp-delay = <0x8fc>;
  3825. fcs,suspend-voltage-selector = <0x01>;
  3826. compatible = "tcs,tcs4525";
  3827. reg = <0x1c>;
  3828. phandle = <0x04>;
  3829. vin-supply = <0x11>;
  3830.  
  3831. regulator-state-mem {
  3832. regulator-off-in-suspend;
  3833. };
  3834. };
  3835.  
  3836. pmic@20 {
  3837. pinctrl-names = "default";
  3838. rockchip,system-power-controller;
  3839. clock-output-names = "rk808-clkout1\0rk808-clkout2";
  3840. pinctrl-0 = <0x13 0x14>;
  3841. clock-names = "mclk";
  3842. assigned-clocks = <0x0b 0x48>;
  3843. assigned-clock-parents = <0x0b 0x196>;
  3844. wakeup-source;
  3845. interrupts = <0x03 0x08>;
  3846. clocks = <0x0b 0x48>;
  3847. #clock-cells = <0x01>;
  3848. interrupt-parent = <0x12>;
  3849. vcc1-supply = <0x11>;
  3850. #sound-dai-cells = <0x00>;
  3851. vcc2-supply = <0x11>;
  3852. compatible = "rockchip,rk817";
  3853. vcc3-supply = <0x11>;
  3854. vcc4-supply = <0x11>;
  3855. vcc5-supply = <0x11>;
  3856. reg = <0x20>;
  3857. phandle = <0x62>;
  3858. vcc6-supply = <0x11>;
  3859. vcc7-supply = <0x11>;
  3860. vcc8-supply = <0x11>;
  3861. vcc9-supply = <0x15>;
  3862.  
  3863. regulators {
  3864.  
  3865. DCDC_REG4 {
  3866. regulator-max-microvolt = <0x325aa0>;
  3867. regulator-boot-on;
  3868. regulator-always-on;
  3869. regulator-min-microvolt = <0x325aa0>;
  3870. regulator-name = "vcc_3v3";
  3871. regulator-initial-mode = <0x02>;
  3872. phandle = <0x3a>;
  3873.  
  3874. regulator-state-mem {
  3875. regulator-off-in-suspend;
  3876. };
  3877. };
  3878.  
  3879. LDO_REG4 {
  3880. regulator-max-microvolt = <0x325aa0>;
  3881. regulator-boot-on;
  3882. regulator-always-on;
  3883. regulator-min-microvolt = <0x325aa0>;
  3884. regulator-name = "vccio_acodec";
  3885. phandle = <0xa6>;
  3886.  
  3887. regulator-state-mem {
  3888. regulator-off-in-suspend;
  3889. };
  3890. };
  3891.  
  3892. DCDC_REG2 {
  3893. regulator-max-microvolt = <0x149970>;
  3894. regulator-boot-on;
  3895. regulator-init-microvolt = <0xdbba0>;
  3896. regulator-always-on;
  3897. regulator-min-microvolt = <0x7a120>;
  3898. regulator-name = "vdd_gpu";
  3899. regulator-ramp-delay = <0x1771>;
  3900. regulator-initial-mode = <0x02>;
  3901. phandle = <0x35>;
  3902.  
  3903. regulator-state-mem {
  3904. regulator-off-in-suspend;
  3905. };
  3906. };
  3907.  
  3908. LDO_REG2 {
  3909. regulator-max-microvolt = <0xdbba0>;
  3910. regulator-boot-on;
  3911. regulator-always-on;
  3912. regulator-min-microvolt = <0xdbba0>;
  3913. regulator-name = "vdda_0v9";
  3914. phandle = <0x4a>;
  3915.  
  3916. regulator-state-mem {
  3917. regulator-off-in-suspend;
  3918. };
  3919. };
  3920.  
  3921. BOOST {
  3922. regulator-max-microvolt = <0x4c4b40>;
  3923. regulator-boot-on;
  3924. regulator-always-on;
  3925. regulator-min-microvolt = <0x4c4b40>;
  3926. regulator-name = "boost";
  3927. phandle = <0x15>;
  3928.  
  3929. regulator-state-mem {
  3930. regulator-off-in-suspend;
  3931. };
  3932. };
  3933.  
  3934. LDO_REG9 {
  3935. regulator-max-microvolt = <0x2ab980>;
  3936. regulator-boot-on;
  3937. regulator-always-on;
  3938. regulator-min-microvolt = <0x2ab980>;
  3939. regulator-name = "vcc2v8_dvp";
  3940. phandle = <0xa9>;
  3941.  
  3942. regulator-state-mem {
  3943. regulator-off-in-suspend;
  3944. };
  3945. };
  3946.  
  3947. LDO_REG7 {
  3948. regulator-max-microvolt = <0x1b7740>;
  3949. regulator-boot-on;
  3950. regulator-always-on;
  3951. regulator-min-microvolt = <0x1b7740>;
  3952. regulator-name = "vcc_1v8";
  3953. phandle = <0x4b>;
  3954.  
  3955. regulator-state-mem {
  3956. regulator-off-in-suspend;
  3957. };
  3958. };
  3959.  
  3960. LDO_REG5 {
  3961. regulator-max-microvolt = <0x325aa0>;
  3962. regulator-boot-on;
  3963. regulator-always-on;
  3964. regulator-min-microvolt = <0x1b7740>;
  3965. regulator-name = "vccio_sd";
  3966. phandle = <0x54>;
  3967.  
  3968. regulator-state-mem {
  3969. regulator-off-in-suspend;
  3970. };
  3971. };
  3972.  
  3973. DCDC_REG3 {
  3974. regulator-max-microvolt = <0x10c8e0>;
  3975. regulator-boot-on;
  3976. regulator-always-on;
  3977. regulator-min-microvolt = <0x10c8e0>;
  3978. regulator-name = "vcc_ddr";
  3979. regulator-initial-mode = <0x02>;
  3980. phandle = <0xa4>;
  3981.  
  3982. regulator-state-mem {
  3983. regulator-on-in-suspend;
  3984. };
  3985. };
  3986.  
  3987. LDO_REG3 {
  3988. regulator-max-microvolt = <0xdbba0>;
  3989. regulator-boot-on;
  3990. regulator-always-on;
  3991. regulator-min-microvolt = <0xdbba0>;
  3992. regulator-name = "vdda0v9_pmu";
  3993. phandle = <0xa5>;
  3994.  
  3995. regulator-state-mem {
  3996. regulator-suspend-microvolt = <0xdbba0>;
  3997. regulator-on-in-suspend;
  3998. };
  3999. };
  4000.  
  4001. DCDC_REG1 {
  4002. regulator-max-microvolt = <0x149970>;
  4003. regulator-boot-on;
  4004. regulator-init-microvolt = <0xdbba0>;
  4005. regulator-always-on;
  4006. regulator-min-microvolt = <0x7a120>;
  4007. regulator-name = "vdd_logic";
  4008. regulator-ramp-delay = <0x1771>;
  4009. regulator-initial-mode = <0x02>;
  4010. phandle = <0xa3>;
  4011.  
  4012. regulator-state-mem {
  4013. regulator-suspend-microvolt = <0xdbba0>;
  4014. regulator-on-in-suspend;
  4015. };
  4016. };
  4017.  
  4018. LDO_REG1 {
  4019. regulator-max-microvolt = <0x1b7740>;
  4020. regulator-boot-on;
  4021. regulator-always-on;
  4022. regulator-min-microvolt = <0x1b7740>;
  4023. regulator-name = "vcca1v8_pmu";
  4024. phandle = <0x67>;
  4025.  
  4026. regulator-state-mem {
  4027. regulator-suspend-microvolt = <0x1b7740>;
  4028. regulator-on-in-suspend;
  4029. };
  4030. };
  4031.  
  4032. OTG_SWITCH {
  4033. regulator-name = "otg_switch";
  4034. phandle = <0xaa>;
  4035.  
  4036. regulator-state-mem {
  4037. regulator-off-in-suspend;
  4038. };
  4039. };
  4040.  
  4041. LDO_REG8 {
  4042. regulator-max-microvolt = <0x1b7740>;
  4043. regulator-boot-on;
  4044. regulator-always-on;
  4045. regulator-min-microvolt = <0x1b7740>;
  4046. regulator-name = "vcc1v8_dvp";
  4047. phandle = <0xa8>;
  4048.  
  4049. regulator-state-mem {
  4050. regulator-off-in-suspend;
  4051. };
  4052. };
  4053.  
  4054. LDO_REG6 {
  4055. regulator-max-microvolt = <0x325aa0>;
  4056. regulator-boot-on;
  4057. regulator-always-on;
  4058. regulator-min-microvolt = <0x325aa0>;
  4059. regulator-name = "vcc3v3_pmu";
  4060. phandle = <0xa7>;
  4061.  
  4062. regulator-state-mem {
  4063. regulator-suspend-microvolt = <0x325aa0>;
  4064. regulator-on-in-suspend;
  4065. };
  4066. };
  4067. };
  4068. };
  4069. };
  4070.  
  4071. pwm@fdd70030 {
  4072. pinctrl-names = "active";
  4073. pinctrl-0 = <0x1b>;
  4074. clock-names = "pwm\0pclk";
  4075. clocks = <0x0e 0x0d 0x0e 0x30>;
  4076. #pwm-cells = <0x03>;
  4077. compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
  4078. status = "disabled";
  4079. reg = <0x00 0xfdd70030 0x00 0x10>;
  4080. phandle = <0xaf>;
  4081. };
  4082.  
  4083. serial@fdd50000 {
  4084. reg-io-width = <0x04>;
  4085. pinctrl-names = "default";
  4086. pinctrl-0 = <0x17>;
  4087. clock-names = "baudclk\0apb_pclk";
  4088. interrupts = <0x00 0x74 0x04>;
  4089. clocks = <0x0e 0x0b 0x0e 0x2c>;
  4090. compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart";
  4091. status = "okay";
  4092. reg = <0x00 0xfdd50000 0x00 0x100>;
  4093. phandle = <0xab>;
  4094. dmas = <0x16 0x00 0x16 0x01>;
  4095. reg-shift = <0x02>;
  4096. };
  4097.  
  4098. pwm@fe700020 {
  4099. pinctrl-names = "active";
  4100. pinctrl-0 = <0x80>;
  4101. clock-names = "pwm\0pclk";
  4102. clocks = <0x0b 0x160 0x0b 0x15f>;
  4103. #pwm-cells = <0x03>;
  4104. compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
  4105. status = "disabled";
  4106. reg = <0x00 0xfe700020 0x00 0x10>;
  4107. phandle = <0xdf>;
  4108. };
  4109.  
  4110. chosen {
  4111. linux,initrd-end = <0x00 0xaa0d7b8>;
  4112. bootargs = "initrd=/initramfs-linux.img root=PARTUUID=77b94d45-bbfa-47d8-aa03-bfdaf9ef8a47 rw earlycon=uart8250,mmio32,0xfe660000 console=tty1 console=ttyS2,1500000n8 quiet splash plymouth.ignore-serial-consoles";
  4113. linux,initrd-start = <0x00 0xa200000>;
  4114. phandle = <0x22d>;
  4115. stdout-path = "serial2:1500000n8";
  4116. };
  4117.  
  4118. pwm@fdd70020 {
  4119. pinctrl-names = "active";
  4120. pinctrl-0 = <0x1a>;
  4121. clock-names = "pwm\0pclk";
  4122. clocks = <0x0e 0x0d 0x0e 0x30>;
  4123. #pwm-cells = <0x03>;
  4124. compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
  4125. status = "disabled";
  4126. reg = <0x00 0xfdd70020 0x00 0x10>;
  4127. phandle = <0xae>;
  4128. };
  4129.  
  4130. pwm@fe700010 {
  4131. pinctrl-names = "active";
  4132. pinctrl-0 = <0x7f>;
  4133. clock-names = "pwm\0pclk";
  4134. clocks = <0x0b 0x160 0x0b 0x15f>;
  4135. #pwm-cells = <0x03>;
  4136. compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
  4137. status = "disabled";
  4138. reg = <0x00 0xfe700010 0x00 0x10>;
  4139. phandle = <0xde>;
  4140. };
  4141.  
  4142. i2c@fe5b0000 {
  4143. pinctrl-names = "default";
  4144. #address-cells = <0x01>;
  4145. pinctrl-0 = <0x5c>;
  4146. clock-names = "i2c\0pclk";
  4147. interrupts = <0x00 0x30 0x04>;
  4148. clocks = <0x0b 0x14a 0x0b 0x149>;
  4149. #size-cells = <0x00>;
  4150. compatible = "rockchip,rk3568-i2c\0rockchip,rk3399-i2c";
  4151. status = "disabled";
  4152. reg = <0x00 0xfe5b0000 0x00 0x1000>;
  4153. phandle = <0xc1>;
  4154. };
  4155.  
  4156. qos@fe190300 {
  4157. compatible = "rockchip,rk3568-qos\0syscon";
  4158. reg = <0x00 0xfe190300 0x00 0x20>;
  4159. phandle = <0x30>;
  4160. };
  4161.  
  4162. pwm@fdd70010 {
  4163. pinctrl-names = "active";
  4164. pinctrl-0 = <0x19>;
  4165. clock-names = "pwm\0pclk";
  4166. clocks = <0x0e 0x0d 0x0e 0x30>;
  4167. #pwm-cells = <0x03>;
  4168. compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
  4169. status = "disabled";
  4170. reg = <0x00 0xfdd70010 0x00 0x10>;
  4171. phandle = <0xad>;
  4172. };
  4173.  
  4174. pwm@fe700000 {
  4175. pinctrl-names = "active";
  4176. pinctrl-0 = <0x7e>;
  4177. clock-names = "pwm\0pclk";
  4178. clocks = <0x0b 0x160 0x0b 0x15f>;
  4179. #pwm-cells = <0x03>;
  4180. compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
  4181. status = "disabled";
  4182. reg = <0x00 0xfe700000 0x00 0x10>;
  4183. phandle = <0xdd>;
  4184. };
  4185.  
  4186. clock-controller@fdd20000 {
  4187. #reset-cells = <0x01>;
  4188. assigned-clocks = <0x0b 0x04 0x0e 0x01>;
  4189. assigned-clock-rates = <0x47868c00 0xbebc200>;
  4190. #clock-cells = <0x01>;
  4191. compatible = "rockchip,rk3568-cru";
  4192. rockchip,grf = <0x0f>;
  4193. reg = <0x00 0xfdd20000 0x00 0x1000>;
  4194. phandle = <0x0b>;
  4195. };
  4196.  
  4197. pwm@fdd70000 {
  4198. pinctrl-names = "active";
  4199. pinctrl-0 = <0x18>;
  4200. clock-names = "pwm\0pclk";
  4201. clocks = <0x0e 0x0d 0x0e 0x30>;
  4202. #pwm-cells = <0x03>;
  4203. compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
  4204. status = "disabled";
  4205. reg = <0x00 0xfdd70000 0x00 0x10>;
  4206. phandle = <0xac>;
  4207. };
  4208.  
  4209. mmc@fe2b0000 {
  4210. fifo-depth = <0x100>;
  4211. pinctrl-names = "default";
  4212. pinctrl-0 = <0x4f 0x50 0x51 0x52>;
  4213. clock-names = "biu\0ciu\0ciu-drive\0ciu-sample";
  4214. cap-sd-highspeed;
  4215. vqmmc-supply = <0x54>;
  4216. bus-width = <0x04>;
  4217. resets = <0x0b 0xd4>;
  4218. interrupts = <0x00 0x62 0x04>;
  4219. clocks = <0x0b 0xb0 0x0b 0xb1 0x0b 0x18a 0x0b 0x18b>;
  4220. vmmc-supply = <0x53>;
  4221. compatible = "rockchip,rk3568-dw-mshc\0rockchip,rk3288-dw-mshc";
  4222. status = "okay";
  4223. disable-wp;
  4224. reg = <0x00 0xfe2b0000 0x00 0x4000>;
  4225. phandle = <0xbd>;
  4226. max-frequency = <0x8f0d180>;
  4227. reset-names = "reset";
  4228. cd-gpios = <0x12 0x04 0x01>;
  4229. };
  4230.  
  4231. pmu {
  4232. interrupt-affinity = <0x06 0x07 0x08 0x09>;
  4233. interrupts = <0x00 0xe4 0x04 0x00 0xe5 0x04 0x00 0xe6 0x04 0x00 0xe7 0x04>;
  4234. compatible = "arm,cortex-a55-pmu";
  4235. };
  4236.  
  4237. dmac@fe550000 {
  4238. clock-names = "apb_pclk";
  4239. interrupts = <0x00 0x10 0x04 0x00 0x0f 0x04>;
  4240. clocks = <0x0b 0x10d>;
  4241. arm,pl330-periph-burst;
  4242. compatible = "arm,pl330\0arm,primecell";
  4243. reg = <0x00 0xfe550000 0x00 0x4000>;
  4244. phandle = <0x55>;
  4245. #dma-cells = <0x01>;
  4246. };
  4247.  
  4248. qos@fe190280 {
  4249. compatible = "rockchip,rk3568-qos\0syscon";
  4250. reg = <0x00 0xfe190280 0x00 0x20>;
  4251. phandle = <0x2f>;
  4252. };
  4253.  
  4254. cpus {
  4255. #address-cells = <0x02>;
  4256. #size-cells = <0x00>;
  4257.  
  4258. cpu@300 {
  4259. cpu-supply = <0x04>;
  4260. device_type = "cpu";
  4261. compatible = "arm,cortex-a55";
  4262. reg = <0x00 0x300>;
  4263. enable-method = "psci";
  4264. phandle = <0x09>;
  4265. operating-points-v2 = <0x03>;
  4266. #cooling-cells = <0x02>;
  4267. };
  4268.  
  4269. cpu@200 {
  4270. cpu-supply = <0x04>;
  4271. device_type = "cpu";
  4272. compatible = "arm,cortex-a55";
  4273. reg = <0x00 0x200>;
  4274. enable-method = "psci";
  4275. phandle = <0x08>;
  4276. operating-points-v2 = <0x03>;
  4277. #cooling-cells = <0x02>;
  4278. };
  4279.  
  4280. cpu@0 {
  4281. cpu-supply = <0x04>;
  4282. clocks = <0x02 0x00>;
  4283. device_type = "cpu";
  4284. compatible = "arm,cortex-a55";
  4285. reg = <0x00 0x00>;
  4286. enable-method = "psci";
  4287. phandle = <0x06>;
  4288. operating-points-v2 = <0x03>;
  4289. #cooling-cells = <0x02>;
  4290. };
  4291.  
  4292. cpu@100 {
  4293. cpu-supply = <0x04>;
  4294. device_type = "cpu";
  4295. compatible = "arm,cortex-a55";
  4296. reg = <0x00 0x100>;
  4297. enable-method = "psci";
  4298. phandle = <0x07>;
  4299. operating-points-v2 = <0x03>;
  4300. #cooling-cells = <0x02>;
  4301. };
  4302. };
  4303.  
  4304. __symbols__ {
  4305. cam_clkout1 = "/pinctrl/cam/cam-clkout1";
  4306. i2c3 = "/i2c@fe5c0000";
  4307. scmi_shmem = "/sram@10f000/sram@0";
  4308. i2s1m1_sdi1 = "/pinctrl/i2s1/i2s1m1-sdi1";
  4309. pmic_pins = "/pinctrl/pmic/pmic-pins";
  4310. pdmm0_sdi3 = "/pinctrl/pdm/pdmm0-sdi3";
  4311. usb_host1_ohci = "/usb@fd8c0000";
  4312. pwm9 = "/pwm@fe6f0010";
  4313. qos_usb3_1 = "/qos@fe190400";
  4314. gmac0_rgmii_bus = "/pinctrl/gmac0/gmac0-rgmii-bus";
  4315. pcie30x2m2_pins = "/pinctrl/pcie30x2/pcie30x2m2-pins";
  4316. i2s2m1_mclk = "/pinctrl/i2s2/i2s2m1-mclk";
  4317. gmac1m1_rx_er = "/pinctrl/gmac1/gmac1m1-rx-er";
  4318. vccio_acodec = "/i2c@fdd40000/pmic@20/regulators/LDO_REG4";
  4319. pdmm2_clk1 = "/pinctrl/pdm/pdmm2-clk1";
  4320. pwm14 = "/pwm@fe700020";
  4321. can2m1_pins = "/pinctrl/can2/can2m1-pins";
  4322. sdmmc2m1_cmd = "/pinctrl/sdmmc2/sdmmc2m1-cmd";
  4323. gmac1m0_rgmii_clk_level2 = "/pinctrl/gmac-txc-level2/gmac1m0-rgmii-clk-level2";
  4324. i2s2m1_lrcktx = "/pinctrl/i2s2/i2s2m1-lrcktx";
  4325. bt656m1_pins = "/pinctrl/bt656/bt656m1-pins";
  4326. pwm0m1_pins = "/pinctrl/pwm0/pwm0m1-pins";
  4327. cpu_crit = "/thermal-zones/cpu-thermal/trips/cpu_crit";
  4328. thermal_zones = "/thermal-zones";
  4329. uart9m0_rtsn = "/pinctrl/uart9/uart9m0-rtsn";
  4330. i2s2m0_lrckrx = "/pinctrl/i2s2/i2s2m0-lrckrx";
  4331. qos_gpu = "/qos@fe128000";
  4332. qos_iep = "/qos@fe158100";
  4333. pcfg_pull_none_drv_level_3 = "/pinctrl/pcfg-pull-none-drv-level-3";
  4334. vp1 = "/vop@fe040000/ports/port@1";
  4335. uart1m1_xfer = "/pinctrl/uart1/uart1m1-xfer";
  4336. i2s1m2_sclkrx = "/pinctrl/i2s1/i2s1m2-sclkrx";
  4337. spdif_sound = "/spdif-sound";
  4338. uart8 = "/serial@fe6c0000";
  4339. qos_vop_m1 = "/qos@fe1a8100";
  4340. i2s3m0_lrck = "/pinctrl/i2s3/i2s3m0-lrck";
  4341. pcfg_pull_none_smt = "/pinctrl/pcfg-pull-none-smt";
  4342. spi0m0_cs0_hs = "/pinctrl/spi0-hs/spi0m0-cs0";
  4343. vp0_out_hdmi = "/vop@fe040000/ports/port@0/endpoint@0";
  4344. spi2m1_cs0 = "/pinctrl/spi2/spi2m1-cs0";
  4345. fspi_cs1 = "/pinctrl/fspi/fspi-cs1";
  4346. vcc5v0_usb20_host_en = "/pinctrl/usb2/vcc5v0-usb20-host-en";
  4347. qos_ebc = "/qos@fe158000";
  4348. pcfg_pull_up_drv_level_15 = "/pinctrl/pcfg-pull-up-drv-level-15";
  4349. gpio0 = "/pinctrl/gpio@fdd60000";
  4350. saradc = "/saradc@fe720000";
  4351. i2s1m0_sdi3 = "/pinctrl/i2s1/i2s1m0-sdi3";
  4352. emmc_rstnout = "/pinctrl/emmc/emmc-rstnout";
  4353. i2s3m1_mclk = "/pinctrl/i2s3/i2s3m1-mclk";
  4354. usb2phy1 = "/usb2-phy@fe8b0000";
  4355. pmu_pins = "/pinctrl/pmu/pmu-pins";
  4356. gmac0_miim = "/pinctrl/gmac0/gmac0-miim";
  4357. spi3m0_cs0 = "/pinctrl/spi3/spi3m0-cs0";
  4358. can0m0_pins = "/pinctrl/can0/can0m0-pins";
  4359. pcfg_pull_up_drv_level_2 = "/pinctrl/pcfg-pull-up-drv-level-2";
  4360. pinctrl = "/pinctrl";
  4361. pcfg_pull_down_drv_level_6 = "/pinctrl/pcfg-pull-down-drv-level-6";
  4362. pwm1m1_pins = "/pinctrl/pwm1/pwm1m1-pins";
  4363. spi3m0_pins_hs = "/pinctrl/spi3-hs/spi3m0-pins";
  4364. i2s2m1_lrckrx = "/pinctrl/i2s2/i2s2m1-lrckrx";
  4365. gmac1m0_rgmii_bus = "/pinctrl/gmac1/gmac1m0-rgmii-bus";
  4366. pdmm0_clk = "/pinctrl/pdm/pdmm0-clk";
  4367. qos_isp = "/qos@fe148000";
  4368. sata2_pins = "/pinctrl/sata2/sata2-pins";
  4369. vdd_logic = "/i2c@fdd40000/pmic@20/regulators/DCDC_REG1";
  4370. uart2m1_xfer = "/pinctrl/uart2/uart2m1-xfer";
  4371. jtag_pins = "/pinctrl/jtag/jtag-pins";
  4372. i2c1 = "/i2c@fe5a0000";
  4373. uart3m0_ctsn = "/pinctrl/uart3/uart3m0-ctsn";
  4374. vopm0_pins = "/pinctrl/vop/vopm0-pins";
  4375. sdmmc2m0_pwren = "/pinctrl/sdmmc2/sdmmc2m0-pwren";
  4376. qos_rkvenc_rd_m0 = "/qos@fe138080";
  4377. pdmm0_sdi1 = "/pinctrl/pdm/pdmm0-sdi1";
  4378. pwm7 = "/pwm@fe6e0030";
  4379. spi0m1_cs0_hs = "/pinctrl/spi0-hs/spi0m1-cs0";
  4380. i2s2m0_sclktx = "/pinctrl/i2s2/i2s2m0-sclktx";
  4381. sdmmc0_pwren = "/pinctrl/sdmmc0/sdmmc0-pwren";
  4382. sdmmc0_clk = "/pinctrl/sdmmc0/sdmmc0-clk";
  4383. pwm3_pins = "/pinctrl/pwm3/pwm3-pins";
  4384. gmac1_clkin = "/external-gmac1-clock";
  4385. pwm12 = "/pwm@fe700000";
  4386. emmc_cmd = "/pinctrl/emmc/emmc-cmd";
  4387. i2s1_8ch = "/i2s@fe410000";
  4388. pcie30x1m1_pins = "/pinctrl/pcie30x1/pcie30x1m1-pins";
  4389. pcfg_pull_none = "/pinctrl/pcfg-pull-none";
  4390. i2s1m0_mclk = "/pinctrl/i2s1/i2s1m0-mclk";
  4391. can1m0_pins = "/pinctrl/can1/can1m0-pins";
  4392. flash_pins = "/pinctrl/flash/flash-pins";
  4393. clk32k_out0 = "/pinctrl/clk32k/clk32k-out0";
  4394. pwm2m1_pins = "/pinctrl/pwm2/pwm2m1-pins";
  4395. i2s1m2_sdo2 = "/pinctrl/i2s1/i2s1m2-sdo2";
  4396. qos_rga_wr = "/qos@fe158300";
  4397. pcfg_pull_none_drv_level_1 = "/pinctrl/pcfg-pull-none-drv-level-1";
  4398. gmac1m1_tx_bus2_level3 = "/pinctrl/gmac-txd-level3/gmac1m1-tx-bus2-level3";
  4399. hdmitxm1_cec = "/pinctrl/hdmitx/hdmitxm1-cec";
  4400. uart6 = "/serial@fe6a0000";
  4401. sdhci = "/mmc@fe310000";
  4402. gmac0_rgmii_bus_level3 = "/pinctrl/gmac-txd-level3/gmac0-rgmii-bus-level3";
  4403. pcfg_pull_none_drv_level_0_smt = "/pinctrl/pcfg-pull-none-drv-level-0-smt";
  4404. uart3m1_xfer = "/pinctrl/uart3/uart3m1-xfer";
  4405. spi2m0_cs1_hs = "/pinctrl/spi2-hs/spi2m0-cs1";
  4406. uart4m0_ctsn = "/pinctrl/uart4/uart4m0-ctsn";
  4407. vcc_sys = "/vcc_sys";
  4408. audiopwm_routp = "/pinctrl/audiopwm/audiopwm-routp";
  4409. i2s2m0_sdo = "/pinctrl/i2s2/i2s2m0-sdo";
  4410. gpu = "/gpu@fde60000";
  4411. i2s2m1_sclktx = "/pinctrl/i2s2/i2s2m1-sclktx";
  4412. pcfg_pull_up_drv_level_13 = "/pinctrl/pcfg-pull-up-drv-level-13";
  4413. i2s2m0_sclkrx = "/pinctrl/i2s2/i2s2m0-sclkrx";
  4414. i2s1m0_sdi1 = "/pinctrl/i2s1/i2s1m0-sdi1";
  4415. usb_host0_ohci = "/usb@fd840000";
  4416. cif_dvp_bus16 = "/pinctrl/cif/cif-dvp-bus16";
  4417. pcie30x2m1_pins = "/pinctrl/pcie30x2/pcie30x2m1-pins";
  4418. i2s2m0_mclk = "/pinctrl/i2s2/i2s2m0-mclk";
  4419. scmi = "/firmware/scmi";
  4420. pcfg_pull_up_drv_level_0 = "/pinctrl/pcfg-pull-up-drv-level-0";
  4421. pdmm1_clk1 = "/pinctrl/pdm/pdmm1-clk1";
  4422. pcfg_pull_down_drv_level_4 = "/pinctrl/pcfg-pull-down-drv-level-4";
  4423. can2m0_pins = "/pinctrl/can2/can2m0-pins";
  4424. sdmmc1_cmd = "/pinctrl/sdmmc1/sdmmc1-cmd";
  4425. bt656m0_pins = "/pinctrl/bt656/bt656m0-pins";
  4426. pwm0m0_pins = "/pinctrl/pwm0/pwm0m0-pins";
  4427. audiopwm_lout = "/pinctrl/audiopwm/audiopwm-lout";
  4428. pcfg_pull_down_drv_level_15 = "/pinctrl/pcfg-pull-down-drv-level-15";
  4429. uart7m2_xfer = "/pinctrl/uart7/uart7m2-xfer";
  4430. pmugrf = "/syscon@fdc20000";
  4431. uart4m1_xfer = "/pinctrl/uart4/uart4m1-xfer";
  4432. pwm5 = "/pwm@fe6e0010";
  4433. spi2m1_cs1_hs = "/pinctrl/spi2-hs/spi2m1-cs1";
  4434. uart1m0_xfer = "/pinctrl/uart1/uart1m0-xfer";
  4435. uart5m0_ctsn = "/pinctrl/uart5/uart5m0-ctsn";
  4436. gmac1m1_miim = "/pinctrl/gmac1/gmac1m1-miim";
  4437. i2s2m1_sclkrx = "/pinctrl/i2s2/i2s2m1-sclkrx";
  4438. pwm10 = "/pwm@fe6f0020";
  4439. sdmmc2m1_clk = "/pinctrl/sdmmc2/sdmmc2m1-clk";
  4440. tsadc_pin = "/pinctrl/tsadc/tsadc-pin";
  4441. pcfg_pull_none_drv_level_14 = "/pinctrl/pcfg-pull-none-drv-level-14";
  4442. i2s3m0_mclk = "/pinctrl/i2s3/i2s3m0-mclk";
  4443. i2s1m2_sdo0 = "/pinctrl/i2s1/i2s1m2-sdo0";
  4444. uart4 = "/serial@fe680000";
  4445. pwm1m0_pins = "/pinctrl/pwm1/pwm1m0-pins";
  4446. spi0m0_cs0 = "/pinctrl/spi0/spi0m0-cs0";
  4447. pdmm2_sdi2 = "/pinctrl/pdm/pdmm2-sdi2";
  4448. pcfg_pull_up_drv_level_9 = "/pinctrl/pcfg-pull-up-drv-level-9";
  4449. pcie30x1_buttonrstn = "/pinctrl/pcie30x1/pcie30x1-buttonrstn";
  4450. u2phy1_host = "/usb2-phy@fe8b0000/host-port";
  4451. qos_sata2 = "/qos@fe190300";
  4452. spi2m0_cs1 = "/pinctrl/spi2/spi2m0-cs1";
  4453. spi2m1_pins_hs = "/pinctrl/spi2-hs/spi2m1-pins";
  4454. uart5m1_xfer = "/pinctrl/uart5/uart5m1-xfer";
  4455. sata1_pins = "/pinctrl/sata1/sata1-pins";
  4456. vcc2v8_dvp = "/i2c@fdd40000/pmic@20/regulators/LDO_REG9";
  4457. uart2m0_xfer = "/pinctrl/uart2/uart2m0-xfer";
  4458. uart6m0_ctsn = "/pinctrl/uart6/uart6m0-ctsn";
  4459. npu_pins = "/pinctrl/npu/npu-pins";
  4460. pcfg_pull_up_drv_level_11 = "/pinctrl/pcfg-pull-up-drv-level-11";
  4461. vdd_gpu = "/i2c@fdd40000/pmic@20/regulators/DCDC_REG2";
  4462. xin32k = "/xin32k";
  4463. cpu0_opp_table = "/opp-table-0";
  4464. cpu_alert0 = "/thermal-zones/cpu-thermal/trips/cpu_alert0";
  4465. spi1m0_cs0_hs = "/pinctrl/spi1-hs/spi1m0-cs0";
  4466. vp1_out_hdmi = "/vop@fe040000/ports/port@1/endpoint@0";
  4467. pcfg_pull_down_drv_level_2 = "/pinctrl/pcfg-pull-down-drv-level-2";
  4468. i2c2m1_xfer = "/pinctrl/i2c2/i2c2m1-xfer";
  4469. pcie30x1m0_pins = "/pinctrl/pcie30x1/pcie30x1m0-pins";
  4470. qos_vicap0 = "/qos@fe148080";
  4471. qos_vpu = "/qos@fe150000";
  4472. audiopwm_loutn = "/pinctrl/audiopwm/audiopwm-loutn";
  4473. cpu_thermal = "/thermal-zones/cpu-thermal";
  4474. qos_pcie2x1 = "/qos@fe190000";
  4475. spi1m0_pins_hs = "/pinctrl/spi1-hs/spi1m0-pins";
  4476. power = "/power-management@fdd90000/power-controller";
  4477. gmac1m1_rgmii_bus_level3 = "/pinctrl/gmac-txd-level3/gmac1m1-rgmii-bus-level3";
  4478. pwm2m0_pins = "/pinctrl/pwm2/pwm2m0-pins";
  4479. i2s1m1_sdo2 = "/pinctrl/i2s1/i2s1m1-sdo2";
  4480. pcfg_pull_down_drv_level_13 = "/pinctrl/pcfg-pull-down-drv-level-13";
  4481. spdif_dit = "/spdif-dit";
  4482. eth0_pins = "/pinctrl/eth0/eth0-pins";
  4483. pwm3 = "/pwm@fdd70030";
  4484. gmac0_tx_bus2 = "/pinctrl/gmac0/gmac0-tx-bus2";
  4485. uart9m2_xfer = "/pinctrl/uart9/uart9m2-xfer";
  4486. i2s1m2_sdi2 = "/pinctrl/i2s1/i2s1m2-sdi2";
  4487. pcfg_pull_none_drv_level_8 = "/pinctrl/pcfg-pull-none-drv-level-8";
  4488. uart6m1_xfer = "/pinctrl/uart6/uart6m1-xfer";
  4489. uart3m0_xfer = "/pinctrl/uart3/uart3m0-xfer";
  4490. uart7m0_ctsn = "/pinctrl/uart7/uart7m0-ctsn";
  4491. bt_enable_h = "/pinctrl/bt/bt-enable-h";
  4492. usb2phy0_grf = "/syscon@fdca0000";
  4493. scmi_clk = "/firmware/scmi/protocol@14";
  4494. emmc_clk = "/pinctrl/emmc/emmc-clk";
  4495. cru = "/clock-controller@fdd20000";
  4496. spdifm1_tx = "/pinctrl/spdif/spdifm1-tx";
  4497. pcfg_pull_none_drv_level_12 = "/pinctrl/pcfg-pull-none-drv-level-12";
  4498. sdmmc2m0_det = "/pinctrl/sdmmc2/sdmmc2m0-det";
  4499. spi1m1_cs0_hs = "/pinctrl/spi1-hs/spi1m1-cs0";
  4500. i2c3m1_xfer = "/pinctrl/i2c3/i2c3m1-xfer";
  4501. pcie30x2m0_pins = "/pinctrl/pcie30x2/pcie30x2m0-pins";
  4502. cpu3 = "/cpus/cpu@300";
  4503. gmac1_stmmac_axi_setup = "/ethernet@fe010000/stmmac-axi-config";
  4504. spi3m1_cs0 = "/pinctrl/spi3/spi3m1-cs0";
  4505. pdmm0_clk1 = "/pinctrl/pdm/pdmm0-clk1";
  4506. gmac1m0_tx_bus2_level3 = "/pinctrl/gmac-txd-level3/gmac1m0-tx-bus2-level3";
  4507. uart2 = "/serial@fe660000";
  4508. pdmm2_sdi0 = "/pinctrl/pdm/pdmm2-sdi0";
  4509. pcfg_pull_up_drv_level_7 = "/pinctrl/pcfg-pull-up-drv-level-7";
  4510. dmac0 = "/dmac@fe530000";
  4511. pcfg_output_low = "/pinctrl/pcfg-output-low";
  4512. pdmm1_clk = "/pinctrl/pdm/pdmm1-clk";
  4513. vcc_sd_h = "/pinctrl/vcc_sd/vcc-sd-h";
  4514. uart7m1_xfer = "/pinctrl/uart7/uart7m1-xfer";
  4515. uart4m0_xfer = "/pinctrl/uart4/uart4m0-xfer";
  4516. uart8m0_ctsn = "/pinctrl/uart8/uart8m0-ctsn";
  4517. gmac1m0_rx_bus2 = "/pinctrl/gmac1/gmac1m0-rx-bus2";
  4518. refclk_pins = "/pinctrl/refclk/refclk-pins";
  4519. qos_rkvenc_wr_m0 = "/qos@fe138180";
  4520. gmac1m0_miim = "/pinctrl/gmac1/gmac1m0-miim";
  4521. pmu_io_domains = "/syscon@fdc20000/io-domains";
  4522. diy_led_enable_h = "/pinctrl/leds/diy-led-enable-h";
  4523. spi3m0_cs1_hs = "/pinctrl/spi3-hs/spi3m0-cs1";
  4524. pcfg_pull_down_drv_level_0 = "/pinctrl/pcfg-pull-down-drv-level-0";
  4525. vcc3v3_sd = "/vcc3v3_sd";
  4526. gic = "/interrupt-controller@fd400000";
  4527. uart0_rtsn = "/pinctrl/uart0/uart0-rtsn";
  4528. gmac0_rgmii_clk_level2 = "/pinctrl/gmac-txc-level2/gmac0-rgmii-clk-level2";
  4529. sdmmc1_clk = "/pinctrl/sdmmc1/sdmmc1-clk";
  4530. i2c4m1_xfer = "/pinctrl/i2c4/i2c4m1-xfer";
  4531. hdmi_in_vp1 = "/hdmi@fe0a0000/ports/port@0/endpoint@1";
  4532. sdmmc2m1_pwren = "/pinctrl/sdmmc2/sdmmc2m1-pwren";
  4533. sdmmc1 = "/mmc@fe2c0000";
  4534. ebc_extern = "/pinctrl/ebc/ebc-extern";
  4535. i2s1m1_sdo0 = "/pinctrl/i2s1/i2s1m1-sdo0";
  4536. sdmmc1_pwren = "/pinctrl/sdmmc1/sdmmc1-pwren";
  4537. pcfg_pull_down_drv_level_11 = "/pinctrl/pcfg-pull-down-drv-level-11";
  4538. pwm1 = "/pwm@fdd70010";
  4539. i2s1m2_sdi0 = "/pinctrl/i2s1/i2s1m2-sdi0";
  4540. pcfg_pull_none_drv_level_6 = "/pinctrl/pcfg-pull-none-drv-level-6";
  4541. pdmm1_sdi2 = "/pinctrl/pdm/pdmm1-sdi2";
  4542. u2phy0_host = "/usb2-phy@fe8a0000/host-port";
  4543. uart8m1_xfer = "/pinctrl/uart8/uart8m1-xfer";
  4544. sata_pins = "/pinctrl/sata/sata-pins";
  4545. uart5m0_xfer = "/pinctrl/uart5/uart5m0-xfer";
  4546. uart9m0_ctsn = "/pinctrl/uart9/uart9m0-ctsn";
  4547. sata0_pins = "/pinctrl/sata0/sata0-pins";
  4548. usb_host1_ehci = "/usb@fd880000";
  4549. xin24m = "/xin24m";
  4550. i2s2m1_sdo = "/pinctrl/i2s2/i2s2m1-sdo";
  4551. pcfg_pull_none_drv_level_10 = "/pinctrl/pcfg-pull-none-drv-level-10";
  4552. tsadc = "/tsadc@fe710000";
  4553. eth1m1_pins = "/pinctrl/eth1/eth1m1-pins";
  4554. mdio1 = "/ethernet@fe010000/mdio";
  4555. gpio3 = "/pinctrl/gpio@fe760000";
  4556. spi3m1_cs1_hs = "/pinctrl/spi3-hs/spi3m1-cs1";
  4557. gpu_opp_table = "/gpu-opp-table";
  4558. pcfg_output_high = "/pinctrl/pcfg-output-high";
  4559. cpu1 = "/cpus/cpu@100";
  4560. i2c5m1_xfer = "/pinctrl/i2c5/i2c5m1-xfer";
  4561. i2c2m0_xfer = "/pinctrl/i2c2/i2c2m0-xfer";
  4562. uart0 = "/serial@fdd50000";
  4563. i2s3m0_sdo = "/pinctrl/i2s3/i2s3m0-sdo";
  4564. pmic_int_l = "/pinctrl/pmic/pmic-int-l";
  4565. pcfg_pull_up_drv_level_5 = "/pinctrl/pcfg-pull-up-drv-level-5";
  4566. pcfg_pull_down_drv_level_9 = "/pinctrl/pcfg-pull-down-drv-level-9";
  4567. i2s2m0_sdi = "/pinctrl/i2s2/i2s2m0-sdi";
  4568. pwm8m1_pins = "/pinctrl/pwm8/pwm8m1-pins";
  4569. spi0m1_pins = "/pinctrl/spi0/spi0m1-pins";
  4570. bt1120_pins = "/pinctrl/bt1120/bt1120-pins";
  4571. spi0m1_pins_hs = "/pinctrl/spi0-hs/spi0m1-pins";
  4572. i2s1m0_sdo2 = "/pinctrl/i2s1/i2s1m0-sdo2";
  4573. u2phy0_otg = "/usb2-phy@fe8a0000/otg-port";
  4574. edpdpm1_pins = "/pinctrl/edpdp/edpdpm1-pins";
  4575. qos_hdcp = "/qos@fe1a8000";
  4576. i2c4 = "/i2c@fe5d0000";
  4577. uart9m1_xfer = "/pinctrl/uart9/uart9m1-xfer";
  4578. i2s1m1_sdi2 = "/pinctrl/i2s1/i2s1m1-sdi2";
  4579. sdmmc1_bus4 = "/pinctrl/sdmmc1/sdmmc1-bus4";
  4580. uart6m0_xfer = "/pinctrl/uart6/uart6m0-xfer";
  4581. vcc3v3_pmu = "/i2c@fdd40000/pmic@20/regulators/LDO_REG6";
  4582. vcc5v0_usb20_host = "/vcc5v0_usb20_host";
  4583. uart1m1_rtsn = "/pinctrl/uart1/uart1m1-rtsn";
  4584. vdd_cpu = "/i2c@fdd40000/regulator@1c";
  4585. qos_jpeg_dec = "/qos@fe158180";
  4586. pwm15 = "/pwm@fe700030";
  4587. vop_mmu = "/iommu@fe043e00";
  4588. gmac1m1_tx_bus2 = "/pinctrl/gmac1/gmac1m1-tx-bus2";
  4589. sdmmc0_det = "/pinctrl/sdmmc0/sdmmc0-det";
  4590. i2c3m0_xfer = "/pinctrl/i2c3/i2c3m0-xfer";
  4591. spdif = "/spdif@fe460000";
  4592. gmac1m1_rgmii_bus = "/pinctrl/gmac1/gmac1m1-rgmii-bus";
  4593. spi2m0_cs0_hs = "/pinctrl/spi2-hs/spi2m0-cs0";
  4594. pwm7_pins = "/pinctrl/pwm7/pwm7-pins";
  4595. vp2_out_hdmi = "/vop@fe040000/ports/port@2/endpoint@0";
  4596. pcfg_pull_none_drv_level_4 = "/pinctrl/pcfg-pull-none-drv-level-4";
  4597. pwm9m1_pins = "/pinctrl/pwm9/pwm9m1-pins";
  4598. pdmm1_sdi0 = "/pinctrl/pdm/pdmm1-sdi0";
  4599. vp2 = "/vop@fe040000/ports/port@2";
  4600. spi1m1_pins = "/pinctrl/spi1/spi1m1-pins";
  4601. uart9 = "/serial@fe6d0000";
  4602. spi0m1_cs0 = "/pinctrl/spi0/spi0m1-cs0";
  4603. gmac0_rgmii_clk = "/pinctrl/gmac0/gmac0-rgmii-clk";
  4604. spi2m1_cs1 = "/pinctrl/spi2/spi2m1-cs1";
  4605. uart7m0_xfer = "/pinctrl/uart7/uart7m0-xfer";
  4606. gmac1m1_rgmii_clk_level2 = "/pinctrl/gmac-txc-level2/gmac1m1-rgmii-clk-level2";
  4607. gpio1 = "/pinctrl/gpio@fe740000";
  4608. tsadcm1_shut = "/pinctrl/tsadc/tsadcm1-shut";
  4609. spi1m0_cs0 = "/pinctrl/spi1/spi1m0-cs0";
  4610. spi3m0_cs1 = "/pinctrl/spi3/spi3m0-cs1";
  4611. vdda0v9_pmu = "/i2c@fdd40000/pmic@20/regulators/LDO_REG3";
  4612. pcfg_pull_up_drv_level_3 = "/pinctrl/pcfg-pull-up-drv-level-3";
  4613. rgmii_phy1 = "/ethernet@fe010000/mdio/ethernet-phy@0";
  4614. i2c4m0_xfer = "/pinctrl/i2c4/i2c4m0-xfer";
  4615. pcfg_pull_down_drv_level_7 = "/pinctrl/pcfg-pull-down-drv-level-7";
  4616. wdt = "/watchdog@fe600000";
  4617. vdda_0v9 = "/i2c@fdd40000/pmic@20/regulators/LDO_REG2";
  4618. qos_rga_rd = "/qos@fe158280";
  4619. spi2m1_cs0_hs = "/pinctrl/spi2-hs/spi2m1-cs0";
  4620. i2s1m0_sdo0 = "/pinctrl/i2s1/i2s1m0-sdo0";
  4621. hdmitx_scl = "/pinctrl/hdmitx/hdmitx-scl";
  4622. hdmitx_sda = "/pinctrl/hdmitx/hdmitx-sda";
  4623. spi2m1_pins = "/pinctrl/spi2/spi2m1-pins";
  4624. cam_clkout0 = "/pinctrl/cam/cam-clkout0";
  4625. i2c2 = "/i2c@fe5b0000";
  4626. i2s1m1_sdi0 = "/pinctrl/i2s1/i2s1m1-sdi0";
  4627. gmac0_rx_er = "/pinctrl/gmac0/gmac0-rx-er";
  4628. qos_rkvenc_rd_m1 = "/qos@fe138100";
  4629. pdmm0_sdi2 = "/pinctrl/pdm/pdmm0-sdi2";
  4630. pwm8 = "/pwm@fe6f0000";
  4631. gmac0_tx_bus2_level3 = "/pinctrl/gmac-txd-level3/gmac0-tx-bus2-level3";
  4632. emmc_bus8 = "/pinctrl/emmc/emmc-bus8";
  4633. qos_usb3_0 = "/qos@fe190380";
  4634. uart8m0_xfer = "/pinctrl/uart8/uart8m0-xfer";
  4635. pwm10m1_pins = "/pinctrl/pwm10/pwm10m1-pins";
  4636. usb_host0_ehci = "/usb@fd800000";
  4637. gmac1 = "/ethernet@fe010000";
  4638. usb2phy1_grf = "/syscon@fdca8000";
  4639. pcie20m2_pins = "/pinctrl/pcie20/pcie20m2-pins";
  4640. pwm13 = "/pwm@fe700010";
  4641. cpu_hot = "/thermal-zones/cpu-thermal/trips/cpu_hot";
  4642. eth1m0_pins = "/pinctrl/eth1/eth1m0-pins";
  4643. gmac1m0_rgmii_clk = "/pinctrl/gmac1/gmac1m0-rgmii-clk";
  4644. cif_dvp_bus8 = "/pinctrl/cif/cif-dvp-bus8";
  4645. sdmmc2m1_det = "/pinctrl/sdmmc2/sdmmc2m1-det";
  4646. tsadc_shutorg = "/pinctrl/tsadc/tsadc-shutorg";
  4647. clk32k_out1 = "/pinctrl/clk32k/clk32k-out1";
  4648. i2c5m0_xfer = "/pinctrl/i2c5/i2c5m0-xfer";
  4649. audiopwm_loutp = "/pinctrl/audiopwm/audiopwm-loutp";
  4650. cif_dvp_clk = "/pinctrl/cif/cif-dvp-clk";
  4651. i2s1m2_sdo3 = "/pinctrl/i2s1/i2s1m2-sdo3";
  4652. fspi_pins = "/pinctrl/fspi/fspi-pins";
  4653. pcfg_pull_none_drv_level_2 = "/pinctrl/pcfg-pull-none-drv-level-2";
  4654. vp0 = "/vop@fe040000/ports/port@0";
  4655. i2c1_xfer = "/pinctrl/i2c1/i2c1-xfer";
  4656. ebc_pins = "/pinctrl/ebc/ebc-pins";
  4657. uart7 = "/serial@fe6b0000";
  4658. qos_vop_m0 = "/qos@fe1a8080";
  4659. vbus = "/vbus";
  4660. pmucru = "/clock-controller@fdd00000";
  4661. spi3m1_pins = "/pinctrl/spi3/spi3m1-pins";
  4662. pwm8m0_pins = "/pinctrl/pwm8/pwm8m0-pins";
  4663. spi0m0_pins = "/pinctrl/spi0/spi0m0-pins";
  4664. vcc_ddr = "/i2c@fdd40000/pmic@20/regulators/DCDC_REG3";
  4665. edpdpm0_pins = "/pinctrl/edpdp/edpdpm0-pins";
  4666. pcfg_pull_up_drv_level_14 = "/pinctrl/pcfg-pull-up-drv-level-14";
  4667. isp_pins = "/pinctrl/isp/isp-pins";
  4668. uart9m0_xfer = "/pinctrl/uart9/uart9m0-xfer";
  4669. i2s1m0_sdi2 = "/pinctrl/i2s1/i2s1m0-sdi2";
  4670. sdmmc0_bus4 = "/pinctrl/sdmmc0/sdmmc0-bus4";
  4671. pwm11m1_pins = "/pinctrl/pwm11/pwm11m1-pins";
  4672. usb2phy0 = "/usb2-phy@fe8a0000";
  4673. uart1m0_rtsn = "/pinctrl/uart1/uart1m0-rtsn";
  4674. pcfg_pull_up_drv_level_1 = "/pinctrl/pcfg-pull-up-drv-level-1";
  4675. pcfg_pull_down_drv_level_5 = "/pinctrl/pcfg-pull-down-drv-level-5";
  4676. vop_out = "/vop@fe040000/ports";
  4677. pcfg_pull_down_smt = "/pinctrl/pcfg-pull-down-smt";
  4678. clk32k_in = "/pinctrl/clk32k/clk32k-in";
  4679. mcu_pins = "/pinctrl/mcu/mcu-pins";
  4680. i2c0 = "/i2c@fdd40000";
  4681. pwm6_pins = "/pinctrl/pwm6/pwm6-pins";
  4682. spi3m1_pins_hs = "/pinctrl/spi3-hs/spi3m1-pins";
  4683. pwm9m0_pins = "/pinctrl/pwm9/pwm9m0-pins";
  4684. pcie30x2_buttonrstn = "/pinctrl/pcie30x2/pcie30x2-buttonrstn";
  4685. pdmm0_sdi0 = "/pinctrl/pdm/pdmm0-sdi0";
  4686. pwm6 = "/pwm@fe6e0020";
  4687. spi1m0_pins = "/pinctrl/spi1/spi1m0-pins";
  4688. spdifm0_tx = "/pinctrl/spdif/spdifm0-tx";
  4689. pwm12m1_pins = "/pinctrl/pwm12/pwm12m1-pins";
  4690. pwm11 = "/pwm@fe6f0030";
  4691. pcie20_buttonrstn = "/pinctrl/pcie20/pcie20-buttonrstn";
  4692. pcfg_pull_none_drv_level_15 = "/pinctrl/pcfg-pull-none-drv-level-15";
  4693. tsadcm0_shut = "/pinctrl/tsadc/tsadcm0-shut";
  4694. i2s1m2_sdo1 = "/pinctrl/i2s1/i2s1m2-sdo1";
  4695. spi2m0_pins_hs = "/pinctrl/spi2-hs/spi2m0-pins";
  4696. pcfg_pull_none_drv_level_0 = "/pinctrl/pcfg-pull-none-drv-level-0";
  4697. cpu_pins = "/pinctrl/cpu/cpu-pins";
  4698. i2s3m1_sdo = "/pinctrl/i2s3/i2s3m1-sdo";
  4699. uart5 = "/serial@fe690000";
  4700. gmac1m0_clkinout = "/pinctrl/gmac1/gmac1m0-clkinout";
  4701. spi0m0_cs1 = "/pinctrl/spi0/spi0m0-cs1";
  4702. pdmm2_sdi3 = "/pinctrl/pdm/pdmm2-sdi3";
  4703. i2s2m1_sdi = "/pinctrl/i2s2/i2s2m1-sdi";
  4704. spi2m0_pins = "/pinctrl/spi2/spi2m0-pins";
  4705. pcfg_pull_up_drv_level_12 = "/pinctrl/pcfg-pull-up-drv-level-12";
  4706. gmac1_mtl_rx_setup = "/ethernet@fe010000/rx-queues-config";
  4707. u2phy1_otg = "/usb2-phy@fe8b0000/otg-port";
  4708. spi3m0_cs0_hs = "/pinctrl/spi3-hs/spi3m0-cs0";
  4709. i2s1m0_sdi0 = "/pinctrl/i2s1/i2s1m0-sdi0";
  4710. spi0m0_cs1_hs = "/pinctrl/spi0-hs/spi0m0-cs1";
  4711. cpu_alert1 = "/thermal-zones/cpu-thermal/trips/cpu_alert1";
  4712. pwm13m1_pins = "/pinctrl/pwm13/pwm13m1-pins";
  4713. i2s3m0_sdi = "/pinctrl/i2s3/i2s3m0-sdi";
  4714. pwm10m0_pins = "/pinctrl/pwm10/pwm10m0-pins";
  4715. pcfg_pull_down_drv_level_3 = "/pinctrl/pcfg-pull-down-drv-level-3";
  4716. uart3m0_rtsn = "/pinctrl/uart3/uart3m0-rtsn";
  4717. vop = "/vop@fe040000";
  4718. pcie20m1_pins = "/pinctrl/pcie20/pcie20m1-pins";
  4719. otg_switch = "/i2c@fdd40000/pmic@20/regulators/OTG_SWITCH";
  4720. cif_clk = "/pinctrl/cif/cif-clk";
  4721. sdmmc2m1_bus4 = "/pinctrl/sdmmc2/sdmmc2m1-bus4";
  4722. qos_vicap1 = "/qos@fe148100";
  4723. sdmmc1_det = "/pinctrl/sdmmc1/sdmmc1-det";
  4724. gmac1m0_rx_er = "/pinctrl/gmac1/gmac1m0-rx-er";
  4725. i2s1m1_sdo3 = "/pinctrl/i2s1/i2s1m1-sdo3";
  4726. pcfg_pull_down_drv_level_14 = "/pinctrl/pcfg-pull-down-drv-level-14";
  4727. gmac0_rx_bus2 = "/pinctrl/gmac0/gmac0-rx-bus2";
  4728. uart0_ctsn = "/pinctrl/uart0/uart0-ctsn";
  4729. i2c0_xfer = "/pinctrl/i2c0/i2c0-xfer";
  4730. pwm4 = "/pwm@fe6e0000";
  4731. i2s1m2_sdi3 = "/pinctrl/i2s1/i2s1m2-sdi3";
  4732. pcfg_pull_none_drv_level_9 = "/pinctrl/pcfg-pull-none-drv-level-9";
  4733. spi3m0_pins = "/pinctrl/spi3/spi3m0-pins";
  4734. i2s3m1_sclk = "/pinctrl/i2s3/i2s3m1-sclk";
  4735. spi3m1_cs0_hs = "/pinctrl/spi3-hs/spi3m1-cs0";
  4736. i2s1m0_lrcktx = "/pinctrl/i2s1/i2s1m0-lrcktx";
  4737. vcca1v8_pmu = "/i2c@fdd40000/pmic@20/regulators/LDO_REG1";
  4738. chosen = "/chosen";
  4739. sdmmc2m0_cmd = "/pinctrl/sdmmc2/sdmmc2m0-cmd";
  4740. pcfg_pull_none_drv_level_13 = "/pinctrl/pcfg-pull-none-drv-level-13";
  4741. pwm14m1_pins = "/pinctrl/pwm14/pwm14m1-pins";
  4742. pwm11m0_pins = "/pinctrl/pwm11/pwm11m0-pins";
  4743. spi1m1_cs0 = "/pinctrl/spi1/spi1m1-cs0";
  4744. uart4m0_rtsn = "/pinctrl/uart4/uart4m0-rtsn";
  4745. pcfg_pull_down = "/pinctrl/pcfg-pull-down";
  4746. spi3m1_cs1 = "/pinctrl/spi3/spi3m1-cs1";
  4747. uart3 = "/serial@fe670000";
  4748. pcfg_pull_up = "/pinctrl/pcfg-pull-up";
  4749. acodec_pins = "/pinctrl/acodec/acodec-pins";
  4750. pdmm2_sdi1 = "/pinctrl/pdm/pdmm2-sdi1";
  4751. pcfg_pull_up_drv_level_8 = "/pinctrl/pcfg-pull-up-drv-level-8";
  4752. dmac1 = "/dmac@fe550000";
  4753. qos_sata1 = "/qos@fe190280";
  4754. spi2m0_cs0 = "/pinctrl/spi2/spi2m0-cs0";
  4755. gmac1m0_rgmii_bus_level3 = "/pinctrl/gmac-txd-level3/gmac1m0-rgmii-bus-level3";
  4756. pcfg_pull_up_drv_level_10 = "/pinctrl/pcfg-pull-up-drv-level-10";
  4757. pwm5_pins = "/pinctrl/pwm5/pwm5-pins";
  4758. gmac1_mtl_tx_setup = "/ethernet@fe010000/tx-queues-config";
  4759. i2s1m2_mclk = "/pinctrl/i2s1/i2s1m2-mclk";
  4760. i2s1m1_lrcktx = "/pinctrl/i2s1/i2s1m1-lrcktx";
  4761. i2s1m0_lrckrx = "/pinctrl/i2s1/i2s1m0-lrckrx";
  4762. vccio_sd = "/i2c@fdd40000/pmic@20/regulators/LDO_REG5";
  4763. vcc_1v8 = "/i2c@fdd40000/pmic@20/regulators/LDO_REG7";
  4764. pwm15m1_pins = "/pinctrl/pwm15/pwm15m1-pins";
  4765. pcfg_pull_down_drv_level_1 = "/pinctrl/pcfg-pull-down-drv-level-1";
  4766. pwm12m0_pins = "/pinctrl/pwm12/pwm12m0-pins";
  4767. uart5m0_rtsn = "/pinctrl/uart5/uart5m0-rtsn";
  4768. hdmi_in_vp2 = "/hdmi@fe0a0000/ports/port@0/endpoint@2";
  4769. bt_host_wake_l = "/pinctrl/bt/bt-host-wake-l";
  4770. sdmmc2 = "/mmc@fe000000";
  4771. i2s1m1_sdo1 = "/pinctrl/i2s1/i2s1m1-sdo1";
  4772. uart1m1_ctsn = "/pinctrl/uart1/uart1m1-ctsn";
  4773. pcfg_pull_down_drv_level_12 = "/pinctrl/pcfg-pull-down-drv-level-12";
  4774. pcfg_pull_up_smt = "/pinctrl/pcfg-pull-up-smt";
  4775. pwm2 = "/pwm@fdd70020";
  4776. audiopwm_routn = "/pinctrl/audiopwm/audiopwm-routn";
  4777. i2s1m2_sdi1 = "/pinctrl/i2s1/i2s1m2-sdi1";
  4778. spi1m1_pins_hs = "/pinctrl/spi1-hs/spi1m1-pins";
  4779. pcfg_pull_none_drv_level_7 = "/pinctrl/pcfg-pull-none-drv-level-7";
  4780. pdmm1_sdi3 = "/pinctrl/pdm/pdmm1-sdi3";
  4781. display_subsystem = "/display-subsystem";
  4782. pmu = "/power-management@fdd90000";
  4783. i2s1m2_lrcktx = "/pinctrl/i2s1/i2s1m2-lrcktx";
  4784. pcfg_pull_none_drv_level_11 = "/pinctrl/pcfg-pull-none-drv-level-11";
  4785. i2s1m1_lrckrx = "/pinctrl/i2s1/i2s1m1-lrckrx";
  4786. bt_wake_l = "/pinctrl/bt/bt-wake-l";
  4787. fan = "/gpio_fan";
  4788. emmc_datastrobe = "/pinctrl/emmc/emmc-datastrobe";
  4789. gpio4 = "/pinctrl/gpio@fe770000";
  4790. pwm13m0_pins = "/pinctrl/pwm13/pwm13m0-pins";
  4791. cpu2 = "/cpus/cpu@200";
  4792. uart6m0_rtsn = "/pinctrl/uart6/uart6m0-rtsn";
  4793. hdmitxm0_cec = "/pinctrl/hdmitx/hdmitxm0-cec";
  4794. gpu_thermal = "/thermal-zones/gpu-thermal";
  4795. audiopwm_rout = "/pinctrl/audiopwm/audiopwm-rout";
  4796. spi0m0_pins_hs = "/pinctrl/spi0-hs/spi0m0-pins";
  4797. uart1 = "/serial@fe650000";
  4798. pcie20m0_pins = "/pinctrl/pcie20/pcie20m0-pins";
  4799. hdmi = "/hdmi@fe0a0000";
  4800. sdmmc2m0_bus4 = "/pinctrl/sdmmc2/sdmmc2m0-bus4";
  4801. pcfg_pull_up_drv_level_6 = "/pinctrl/pcfg-pull-up-drv-level-6";
  4802. i2s1m0_sclktx = "/pinctrl/i2s1/i2s1m0-sclktx";
  4803. gpu_pins = "/pinctrl/gpu/gpu-pins";
  4804. i2s3m1_lrck = "/pinctrl/i2s3/i2s3m1-lrck";
  4805. hdmi_in = "/hdmi@fe0a0000/ports/port@0";
  4806. i2s1m0_sdo3 = "/pinctrl/i2s1/i2s1m0-sdo3";
  4807. vcc12v_dcin = "/vcc12v_dcin";
  4808. i2c5 = "/i2c@fe5e0000";
  4809. qos_rkvdec = "/qos@fe198000";
  4810. i2s1m1_sdi3 = "/pinctrl/i2s1/i2s1m1-sdi3";
  4811. gmac1m1_clkinout = "/pinctrl/gmac1/gmac1m1-clkinout";
  4812. gmac1m0_tx_bus2 = "/pinctrl/gmac1/gmac1m0-tx-bus2";
  4813. i2s3m0_sclk = "/pinctrl/i2s3/i2s3m0-sclk";
  4814. qos_npu = "/qos@fe180000";
  4815. grf = "/syscon@fdc60000";
  4816. qos_jpeg_enc = "/qos@fe158200";
  4817. i2s1m2_lrckrx = "/pinctrl/i2s1/i2s1m2-lrckrx";
  4818. gmac1m1_rx_bus2 = "/pinctrl/gmac1/gmac1m1-rx-bus2";
  4819. scr_pins = "/pinctrl/scr/scr-pins";
  4820. can0m1_pins = "/pinctrl/can0/can0m1-pins";
  4821. hdmi_in_vp0 = "/hdmi@fe0a0000/ports/port@0/endpoint@0";
  4822. sdmmc0_cmd = "/pinctrl/sdmmc0/sdmmc0-cmd";
  4823. pwm14m0_pins = "/pinctrl/pwm14/pwm14m0-pins";
  4824. uart7m0_rtsn = "/pinctrl/uart7/uart7m0-rtsn";
  4825. dcdc_boost = "/i2c@fdd40000/pmic@20/regulators/BOOST";
  4826. sdmmc0 = "/mmc@fe2b0000";
  4827. spi1m0_cs1_hs = "/pinctrl/spi1-hs/spi1m0-cs1";
  4828. pcfg_pull_down_drv_level_10 = "/pinctrl/pcfg-pull-down-drv-level-10";
  4829. i2s1m1_sclktx = "/pinctrl/i2s1/i2s1m1-sclktx";
  4830. pwm0 = "/pwm@fdd70000";
  4831. i2s1m0_sclkrx = "/pinctrl/i2s1/i2s1m0-sclkrx";
  4832. vopm1_pins = "/pinctrl/vop/vopm1-pins";
  4833. pcfg_pull_none_drv_level_5 = "/pinctrl/pcfg-pull-none-drv-level-5";
  4834. pdmm1_sdi1 = "/pinctrl/pdm/pdmm1-sdi1";
  4835. vcc_3v3 = "/i2c@fdd40000/pmic@20/regulators/DCDC_REG4";
  4836. uart0_xfer = "/pinctrl/uart0/uart0-xfer";
  4837. gmac0_clkinout = "/pinctrl/gmac0/gmac0-clkinout";
  4838. sdmmc2m0_clk = "/pinctrl/sdmmc2/sdmmc2m0-clk";
  4839. pwm4_pins = "/pinctrl/pwm4/pwm4-pins";
  4840. rk817 = "/i2c@fdd40000/pmic@20";
  4841. pcie30x1m2_pins = "/pinctrl/pcie30x1/pcie30x1m2-pins";
  4842. i2s1m1_mclk = "/pinctrl/i2s1/i2s1m1-mclk";
  4843. gpio2 = "/pinctrl/gpio@fe750000";
  4844. spi1m0_cs1 = "/pinctrl/spi1/spi1m0-cs1";
  4845. cpu0 = "/cpus/cpu@0";
  4846. lcdc_ctl = "/pinctrl/lcdc/lcdc-ctl";
  4847. can1m1_pins = "/pinctrl/can1/can1m1-pins";
  4848. vcc1v8_dvp = "/i2c@fdd40000/pmic@20/regulators/LDO_REG8";
  4849. spdifm2_tx = "/pinctrl/spdif/spdifm2-tx";
  4850. work_led_enable_h = "/pinctrl/leds/work-led-enable-h";
  4851. i2s3m1_sdi = "/pinctrl/i2s3/i2s3m1-sdi";
  4852. gmac1m1_rgmii_clk = "/pinctrl/gmac1/gmac1m1-rgmii-clk";
  4853. pwm15m0_pins = "/pinctrl/pwm15/pwm15m0-pins";
  4854. i2s2m0_lrcktx = "/pinctrl/i2s2/i2s2m0-lrcktx";
  4855. uart8m0_rtsn = "/pinctrl/uart8/uart8m0-rtsn";
  4856. pcfg_pull_up_drv_level_4 = "/pinctrl/pcfg-pull-up-drv-level-4";
  4857. pcfg_pull_down_drv_level_8 = "/pinctrl/pcfg-pull-down-drv-level-8";
  4858. i2s1m2_sclktx = "/pinctrl/i2s1/i2s1m2-sclktx";
  4859. i2s1m1_sclkrx = "/pinctrl/i2s1/i2s1m1-sclkrx";
  4860. i2s1m0_sdo1 = "/pinctrl/i2s1/i2s1m0-sdo1";
  4861. uart1m0_ctsn = "/pinctrl/uart1/uart1m0-ctsn";
  4862. vcc5v0_usb = "/vcc5v0_usb";
  4863. };
  4864.  
  4865. pwm@fe6f0030 {
  4866. pinctrl-names = "active";
  4867. pinctrl-0 = <0x7d>;
  4868. clock-names = "pwm\0pclk";
  4869. clocks = <0x0b 0x15d 0x0b 0x15c>;
  4870. #pwm-cells = <0x03>;
  4871. compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
  4872. status = "disabled";
  4873. reg = <0x00 0xfe6f0030 0x00 0x10>;
  4874. phandle = <0xdc>;
  4875. };
  4876.  
  4877. serial@fe6d0000 {
  4878. reg-io-width = <0x04>;
  4879. pinctrl-names = "default";
  4880. pinctrl-0 = <0x6f>;
  4881. clock-names = "baudclk\0apb_pclk";
  4882. interrupts = <0x00 0x7d 0x04>;
  4883. clocks = <0x0b 0x13f 0x0b 0x13c>;
  4884. compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart";
  4885. status = "disabled";
  4886. reg = <0x00 0xfe6d0000 0x00 0x100>;
  4887. phandle = <0xce>;
  4888. dmas = <0x16 0x12 0x16 0x13>;
  4889. reg-shift = <0x02>;
  4890. };
  4891.  
  4892. iommu@fe043e00 {
  4893. clock-names = "aclk\0iface";
  4894. interrupts = <0x00 0x94 0x04>;
  4895. clocks = <0x0b 0xdd 0x0b 0xde>;
  4896. #iommu-cells = <0x00>;
  4897. compatible = "rockchip,rk3568-iommu";
  4898. status = "okay";
  4899. interrupt-names = "vop_mmu";
  4900. reg = <0x00 0xfe043e00 0x00 0x100 0x00 0xfe043f00 0x00 0x100>;
  4901. phandle = <0x43>;
  4902. };
  4903.  
  4904. qos@fe138180 {
  4905. compatible = "rockchip,rk3568-qos\0syscon";
  4906. reg = <0x00 0xfe138180 0x00 0x20>;
  4907. phandle = <0x2d>;
  4908. };
  4909.  
  4910. vcc12v_dcin {
  4911. regulator-max-microvolt = <0xb71b00>;
  4912. regulator-boot-on;
  4913. regulator-always-on;
  4914. regulator-min-microvolt = <0xb71b00>;
  4915. regulator-name = "vcc12v_dcin";
  4916. compatible = "regulator-fixed";
  4917. phandle = <0x94>;
  4918. };
  4919.  
  4920. pwm@fe6f0020 {
  4921. pinctrl-names = "active";
  4922. pinctrl-0 = <0x7c>;
  4923. clock-names = "pwm\0pclk";
  4924. clocks = <0x0b 0x15d 0x0b 0x15c>;
  4925. #pwm-cells = <0x03>;
  4926. compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
  4927. status = "disabled";
  4928. reg = <0x00 0xfe6f0020 0x00 0x10>;
  4929. phandle = <0xdb>;
  4930. };
  4931.  
  4932. pwm@fe6f0010 {
  4933. pinctrl-names = "active";
  4934. pinctrl-0 = <0x7b>;
  4935. clock-names = "pwm\0pclk";
  4936. clocks = <0x0b 0x15d 0x0b 0x15c>;
  4937. #pwm-cells = <0x03>;
  4938. compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
  4939. status = "disabled";
  4940. reg = <0x00 0xfe6f0010 0x00 0x10>;
  4941. phandle = <0xda>;
  4942. };
  4943.  
  4944. qos@fe158000 {
  4945. compatible = "rockchip,rk3568-qos\0syscon";
  4946. reg = <0x00 0xfe158000 0x00 0x20>;
  4947. phandle = <0x23>;
  4948. };
  4949.  
  4950. vop@fe040000 {
  4951. power-domains = <0x34 0x09>;
  4952. iommus = <0x43>;
  4953. clock-names = "aclk_vop\0hclk_vop\0dclk_vp0\0dclk_vp1\0dclk_vp2";
  4954. reg-names = "regs\0gamma_lut";
  4955. assigned-clocks = <0x0b 0xdf 0x0b 0xe0>;
  4956. assigned-clock-parents = <0x0e 0x02 0x0b 0x05>;
  4957. interrupts = <0x00 0x94 0x04>;
  4958. clocks = <0x0b 0xdd 0x0b 0xde 0x0b 0xdf 0x0b 0xe0 0x0b 0xe1>;
  4959. compatible = "rockchip,rk3568-vop";
  4960. status = "okay";
  4961. rockchip,grf = <0x0f>;
  4962. reg = <0x00 0xfe040000 0x00 0x3000 0x00 0xfe044000 0x00 0x1000>;
  4963. phandle = <0xb6>;
  4964.  
  4965. ports {
  4966. #address-cells = <0x01>;
  4967. #size-cells = <0x00>;
  4968. phandle = <0x42>;
  4969.  
  4970. port@0 {
  4971. #address-cells = <0x01>;
  4972. #size-cells = <0x00>;
  4973. reg = <0x00>;
  4974. phandle = <0xb7>;
  4975.  
  4976. endpoint@0 {
  4977. remote-endpoint = <0x44>;
  4978. status = "okay";
  4979. reg = <0x00>;
  4980. phandle = <0x4c>;
  4981. };
  4982. };
  4983.  
  4984. port@1 {
  4985. #address-cells = <0x01>;
  4986. #size-cells = <0x00>;
  4987. reg = <0x01>;
  4988. phandle = <0xb8>;
  4989.  
  4990. endpoint@0 {
  4991. remote-endpoint = <0x45>;
  4992. status = "disabled";
  4993. reg = <0x00>;
  4994. phandle = <0x4d>;
  4995. };
  4996. };
  4997.  
  4998. port@2 {
  4999. #address-cells = <0x01>;
  5000. #size-cells = <0x00>;
  5001. reg = <0x02>;
  5002. phandle = <0xb9>;
  5003.  
  5004. endpoint@0 {
  5005. remote-endpoint = <0x46>;
  5006. status = "disabled";
  5007. reg = <0x00>;
  5008. phandle = <0x4e>;
  5009. };
  5010. };
  5011. };
  5012. };
  5013.  
  5014. serial@fe660000 {
  5015. reg-io-width = <0x04>;
  5016. pinctrl-names = "default";
  5017. pinctrl-0 = <0x68>;
  5018. clock-names = "baudclk\0apb_pclk";
  5019. interrupts = <0x00 0x76 0x04>;
  5020. clocks = <0x0b 0x123 0x0b 0x120>;
  5021. compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart";
  5022. status = "okay";
  5023. reg = <0x00 0xfe660000 0x00 0x100>;
  5024. phandle = <0xc7>;
  5025. dmas = <0x16 0x04 0x16 0x05>;
  5026. reg-shift = <0x02>;
  5027. };
  5028.  
  5029. pwm@fe6f0000 {
  5030. pinctrl-names = "active";
  5031. pinctrl-0 = <0x7a>;
  5032. clock-names = "pwm\0pclk";
  5033. clocks = <0x0b 0x15d 0x0b 0x15c>;
  5034. #pwm-cells = <0x03>;
  5035. compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
  5036. status = "disabled";
  5037. reg = <0x00 0xfe6f0000 0x00 0x10>;
  5038. phandle = <0xd9>;
  5039. };
  5040.  
  5041. memory {
  5042. device_type = "memory";
  5043. reg = <0x00 0x200000 0x00 0x8200000 0x00 0x9400000 0x00 0xe6c00000 0x01 0xf0000000 0x00 0x10000000 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
  5044. };
  5045.  
  5046. qos@fe198000 {
  5047. compatible = "rockchip,rk3568-qos\0syscon";
  5048. reg = <0x00 0xfe198000 0x00 0x20>;
  5049. phandle = <0x2a>;
  5050. };
  5051.  
  5052. mmc@fe310000 {
  5053. clock-names = "core\0bus\0axi\0block\0timer";
  5054. vqmmc-supply = <0x4b>;
  5055. assigned-clocks = <0x0b 0x7b 0x0b 0x7d>;
  5056. mmc-hs200-1_8v;
  5057. bus-width = <0x08>;
  5058. non-removable;
  5059. assigned-clock-rates = <0xbebc200 0x16e3600>;
  5060. interrupts = <0x00 0x13 0x04>;
  5061. clocks = <0x0b 0x7c 0x0b 0x7a 0x0b 0x79 0x0b 0x7b 0x0b 0x7d>;
  5062. vmmc-supply = <0x3a>;
  5063. compatible = "rockchip,rk3568-dwcmshc";
  5064. status = "okay";
  5065. reg = <0x00 0xfe310000 0x00 0x10000>;
  5066. phandle = <0xbf>;
  5067. };
  5068.  
  5069. vcc5v0_usb {
  5070. regulator-max-microvolt = <0x4c4b40>;
  5071. regulator-boot-on;
  5072. regulator-always-on;
  5073. regulator-min-microvolt = <0x4c4b40>;
  5074. regulator-name = "vcc5v0_usb";
  5075. compatible = "regulator-fixed";
  5076. phandle = <0x97>;
  5077. vin-supply = <0x94>;
  5078. };
  5079. };
  5080. [root@quartz64 policy0]#
  5081.  
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