testebench6

`timescale 1ns / 1ps

module testbench();

    reg clk1;
    reg clk2;
    wire res;
    reg [7:0] args;
    reg [0:31] error_reg;
    initial begin
        $dumpfile("dump.vcd");
        $dumpvars;

    end
    initial begin
        clk1 = 0;
        clk2 = 0;
        args = 0;
        error_reg = 0;
    end

    always @(posedge clk1) begin
        error_reg[args] = clk2 ~^ res;
        args = args + 1;
        if (args > 6'd100000) begin
            $finish;
        end
    end
    always #10 clk1 = ~clk1;
    always begin
        #10;
        clk2 = ~clk2;
        #270; // change to DIVIDER * 10 - 10
    end
   frequency_divider #(28) freq(.clock_in(clk1), .clock_out(res));
endmodule