Register File

`timescale 1ns / 1ps

// (DECODED OPERAND FETCH | WRITEBACK) = phases of the pipeline referenced in

// clock and reset to all regesters
module Register_file(
                    input clk, RW, rst,
                    input [4:0] DA, AA, BA, // destination address (for writing to a register), A_address, B_address (busses used in datapath)
                    input [31:0] D_DATA, // end of datapath, into register file
                    output reg [31:0] A_DATA, B_DATA // corresponds to AA and BA
                    );
// REGISTER FILE: 32x32

reg [31:0] REGISTER [31:0]; // R0 always 0, or rather REGISTER[31:0][0] = 0;
// what does 32 by 32 mean? 32--32-bit registers, 5 bits count from 0-31

// UPDATE: changed from [31:0] register [4:0] to [31:0] register [31:0]
//          apparently, although addresses are 5 bit to account for 32 different addresses, the second length needs each own bit

integer i;

initial begin // initialize register block to 0
    for(i = 0; i < 32; i = i + 1) begin
        REGISTER[i] = 0;
    end
end
// reading: Potentially reads up to two registers, for bus A and bus B
// DOF phase
always@(*) begin    // asynchronous parts, reading the registers
    A_DATA = REGISTER[AA];
    B_DATA = REGISTER[BA];
end
// WB phase
always@(posedge clk, posedge rst) begin     // synchornous parts, writing to register
    REGISTER[DA] <= ((RW) && (DA == 0))? 0 :            // R0 is ALWAYS 0
                    (RW)? D_DATA : REGISTER[DA];    // if Read write bit is true, then alter the specified register, else don't change anything
    if(rst) begin
            for(i = 0; i < 32; i = i +1) begin
                REGISTER[i] = 0;
            end
    end
end

endmodule