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  1. `timescale 1ns/100ps
  2. `default_nettype none
  3.  
  4. `include "define_state.h"
  5.  
  6. module milestone1(
  7. input logic Clock,
  8. input logic Resetn,
  9. input logic enable,
  10. input logic [15:0] SRAM_read_data,
  11. output logic [15:0] M1_SRAM_write_data,
  12. output logic CSC_we_n,
  13. output logic done,
  14. output logic [17:0] M1_SRAM_address
  15. //test output
  16. /*
  17. output logic [17:0] tb_counter[2:0],
  18. output logic [17:0] common_counter,
  19. output logic[15:0] y_buf_t,
  20. output logic[15:0] u_buf_t,
  21. output logic[7:0] v_buf_t,
  22. output logic[31:0] u_odd_t,
  23. output logic[31:0] u_even_t,
  24. output logic[7:0] tb_u_shift[5:0],
  25. output logic[7:0] tb_v_shift[5:0],
  26. output logic[31:0] RGB_odd_t[2:0],
  27. output logic[7:0] RGB_odd_w_t[2:0],
  28. output logic[31:0] op_t[7:0],
  29. output logic[31:0] mult_t[3:0],
  30. output logic[17:0] t_rounds,
  31. output logic[31:0] u_str_t
  32. */
  33. );
  34.  
  35. M1_state_type M1_state;
  36. // Define the offset for RGB and UV in the memory
  37. parameter U_OFFSET = 18'd38400,
  38. V_OFFSET = 18'd57600,
  39. RGB_OFFSET = 18'd146944;
  40.  
  41. // Data counter for address
  42. logic [17:0] counter[2:0]; //2 for y, 1 for uv 0 for RGB
  43. //test variable
  44. //assign tb_counter=counter;
  45.  
  46.  
  47. //flags
  48. logic flag,lead_out;
  49. //logic [17:0] flag_1;
  50. logic [17:0] rounds;//assign t_rounds=rounds;
  51. assign lead_out=(rounds==159)?1:0;
  52. //multiplier
  53. logic[63:0] mult[3:0];
  54. logic[31:0] mult_32[3:0]; //assign mult_t=mult_32;
  55. logic[31:0] op[7:0]; //assign op_t=op;
  56. assign mult_32[3]=mult[3][31:0];
  57. assign mult_32[2]=mult[2][31:0];
  58. assign mult_32[1]=mult[1][31:0];
  59. assign mult_32[0]=mult[0][31:0];
  60. //YUV buffers & registers
  61. logic[15:0] y_buf;//assign y_buf_t=y_buf;
  62. logic[15:0] u_buf;//assign u_buf_t=u_buf;
  63. logic[7:0] v_buf;//assign v_buf_t=v_buf;
  64. logic[7:0] u_shift[5:0];//assign tb_u_shift=u_shift;
  65. logic[7:0] v_shift[5:0];//assign tb_v_shift=v_shift;
  66. logic[31:0] u_odd;//assign u_odd_t=u_odd;
  67. logic[31:0] u_even;//assign u_even_t=u_even;
  68. logic[31:0] v_odd;
  69. logic[31:0] v_even;
  70. logic[31:0] u_str;//assign u_str_t=u_str;
  71. logic[31:0] v_str;
  72. //CSC registers
  73. logic[31:0] RGB_even[2:0];
  74. logic[7:0] RGB_even_w[2:0];
  75. logic[31:0] y_coe_e;
  76. logic[31:0] RGB_odd[2:0];//assign RGB_odd_t=RGB_even;
  77. logic[7:0] RGB_odd_w[2:0];//assign RGB_odd_w_t=RGB_odd_w;
  78. logic[31:0] y_coe_o;
  79.  
  80. //multiplication
  81. assign mult[0]=op[0]*op[1]; //u_odd
  82. assign mult[1]=op[2]*op[3]; //v_odd
  83. assign mult[2]=op[4]*op[5]; //RGB_odd
  84. assign mult[3]=op[6]*op[7]; //RGB_even
  85.  
  86. //RGB_clipping
  87. assign RGB_even_w[2]=RGB_even[2][31]?0:(|{RGB_even[2][30:24]}?255:{RGB_even[2][23:16]});
  88. assign RGB_even_w[1]=RGB_even[1][31]?0:(|{RGB_even[1][30:24]}?255:{RGB_even[1][23:16]});
  89. assign RGB_even_w[0]=RGB_even[0][31]?0:(|{RGB_even[0][30:24]}?255:{RGB_even[0][23:16]});
  90. assign RGB_odd_w[2]=RGB_odd[2][31]?0:(|{RGB_odd[2][30:24]}?255:{RGB_odd[2][23:16]});
  91. assign RGB_odd_w[1]=RGB_odd[1][31]?0:(|{RGB_odd[1][30:24]}?255:{RGB_odd[1][23:16]});
  92. assign RGB_odd_w[0]=RGB_odd[0][31]?0:(|{RGB_odd[0][30:24]}?255:{RGB_odd[0][23:16]});
  93.  
  94. //operand switch & SRAM_write_data switch
  95. always_comb begin
  96. op[0]=0;op[1]=0;op[2]=0;op[3]=0;
  97. op[4]=0;op[5]=0;op[6]=0;op[7]=0;
  98. M1_SRAM_write_data=0;
  99. case(M1_state)
  100. S_LEAD_IN_7:begin
  101. op[0]=21;op[1]={24'b0,u_shift[0]};
  102. op[2]=21;op[3]={24'b0,v_shift[0]};
  103. end
  104. S_LEAD_IN_8:begin
  105. op[0]=52;op[1]={24'b0,u_shift[0]};
  106. op[2]=52;op[3]={24'b0,v_shift[0]};
  107. end
  108. S_LEAD_IN_9:begin
  109. op[0]=159;op[1]={24'b0,u_shift[0]};
  110. op[2]=159;op[3]={24'b0,v_shift[0]};
  111. end
  112. S_LEAD_IN_10:begin
  113. op[0]=159;op[1]={24'b0,u_shift[0]};
  114. op[2]=159;op[3]={24'b0,v_shift[0]};
  115. end
  116. S_LEAD_IN_11:begin
  117. op[0]=52;op[1]={24'b0,u_shift[0]};
  118. op[2]=52;op[3]={24'b0,v_shift[0]};
  119. end
  120. S_LEAD_IN_12:begin
  121. op[0]=21;op[1]={24'b0,u_shift[0]};
  122. op[2]=21;op[3]={24'b0,v_shift[0]};
  123. end
  124. S_COMMON_0:begin
  125. op[0]=21;op[1]={24'b0,u_shift[0]};
  126. op[2]=21;op[3]={24'b0,v_shift[0]};
  127. op[4]=(y_buf[7:0]-16);op[5]=76284;
  128. op[6]=(y_buf[15:8]-16);op[7]=76284;
  129. M1_SRAM_write_data={RGB_even_w[2],RGB_even_w[1]};
  130. end
  131. S_COMMON_1:begin
  132. op[0]=52;op[1]={24'b0,u_shift[0]};
  133. op[2]=52;op[3]={24'b0,v_shift[0]};
  134. op[4]=(u_str[23:8]-128);op[5]=132251; //u and v only select 16 bit in middle
  135. op[6]=(u_even-128);op[7]=132251;
  136. end
  137. S_COMMON_2:begin
  138. op[0]=159;op[1]={24'b0,u_shift[0]};
  139. op[2]=159;op[3]={24'b0,v_shift[0]};
  140. op[4]=(u_str[23:8]-128);op[5]=25624; //u and v only select 16 bit in middle
  141. op[6]=(u_even-128);op[7]=25624;
  142. end
  143. S_COMMON_3:begin
  144. op[0]=159;op[1]={24'b0,u_shift[0]};
  145. op[2]=159;op[3]={24'b0,v_shift[0]};
  146. op[4]=(v_str[23:8]-128);op[5]=53281; //u and v only select 16 bit in middle
  147. op[6]=(v_even-128);op[7]=53281;
  148.  
  149. end
  150. S_COMMON_4:begin
  151. op[0]=52;op[1]={24'b0,u_shift[0]};
  152. op[2]=52;op[3]={24'b0,v_shift[0]};
  153. op[4]=(v_str[23:8]-128);op[5]=104595; //u and v only select 16 bit in middle
  154. op[6]=(v_even-128);op[7]=104595;
  155. M1_SRAM_write_data={RGB_odd_w[1],RGB_odd_w[0]};
  156. end
  157. S_COMMON_5:begin
  158. op[0]=21;op[1]={24'b0,u_shift[0]};
  159. op[2]=21;op[3]={24'b0,v_shift[0]};
  160. M1_SRAM_write_data={RGB_even_w[0],RGB_odd_w[2]};
  161. end
  162.  
  163. S_LEAD_OUT_0:begin
  164. op[4]=(y_buf[7:0]-16);op[5]=76284;
  165. op[6]=(y_buf[15:8]-16);op[7]=76284;
  166. M1_SRAM_write_data={RGB_even_w[2],RGB_even_w[1]};
  167. end
  168. S_LEAD_OUT_1:begin
  169. op[4]=(u_str[23:8]-128);op[5]=132251; //u and v only select 16 bit in middle
  170. op[6]=(u_even-128);op[7]=132251;
  171. end
  172. S_LEAD_OUT_2:begin
  173. op[4]=(u_str[23:8]-128);op[5]=25624; //u and v only select 16 bit in middle
  174. op[6]=(u_even-128);op[7]=25624;
  175. end
  176. S_LEAD_OUT_3:begin
  177. op[4]=(v_str[23:8]-128);op[5]=53281; //u and v only select 16 bit in middle
  178. op[6]=(v_even-128);op[7]=53281;
  179. end
  180. S_LEAD_OUT_4:begin
  181. op[4]=(v_str[23:8]-128);op[5]=104595; //u and v only select 16 bit in middle
  182. op[6]=(v_even-128);op[7]=104595;
  183. M1_SRAM_write_data={RGB_odd_w[1],RGB_odd_w[0]};
  184. end
  185. S_LEAD_OUT_5:begin
  186. M1_SRAM_write_data={RGB_even_w[0],RGB_odd_w[2]};
  187. end
  188. S_LEAD_OUT_6:begin
  189. M1_SRAM_write_data={RGB_even_w[2],RGB_even_w[1]};
  190. end
  191. endcase
  192. end
  193.  
  194. always_ff @ (posedge Clock or negedge Resetn) begin
  195. if (Resetn == 1'b0) begin
  196. M1_state <= M1_IDLE;
  197.  
  198. M1_SRAM_address <= 18'd0;
  199.  
  200. done<=0;
  201.  
  202. flag<=1;//flag_1<=0;
  203. rounds<=0;
  204. //M1_SRAM_write_data<=0;
  205. CSC_we_n<=1;
  206. counter[2]<=0;counter[1]<=0;counter[0]<=0;
  207.  
  208. y_buf<=0;
  209. u_buf<=0;
  210. v_buf<=0;
  211. u_shift[5]<=0;u_shift[4]<=0;u_shift[3]<=0;
  212. u_shift[2]<=0;u_shift[1]<=0;u_shift[0]<=0;
  213. v_shift[5]<=0;v_shift[4]<=0;v_shift[3]<=0;
  214. v_shift[2]<=0;v_shift[1]<=0;v_shift[0]<=0;
  215. u_odd<=0;u_even<=0;
  216. v_odd<=0;v_even<=0;
  217. u_str=0;
  218. v_str=0;
  219.  
  220. RGB_even[2]<=0;RGB_even[1]<=0;RGB_even[0]<=0;
  221. y_coe_e<=0;
  222. RGB_odd[2]<=0;RGB_odd[1]<=0;RGB_odd[0]<=0;
  223. y_coe_o<=0;
  224. //test
  225. //common_counter<=0;
  226. end else begin
  227. case (M1_state)
  228. M1_IDLE: begin
  229. M1_SRAM_address <= 18'd0;
  230. done<=0;
  231. //M1_SRAM_write_data<=0;
  232. CSC_we_n<=1;
  233. flag<=1;//flag_1<=0;
  234. rounds<=0;
  235. counter[2]<=0;counter[1]<=0;counter[0]<=0;
  236. y_buf<=0;
  237. u_buf<=0;
  238. v_buf<=0;
  239. u_shift[5]<=0;u_shift[4]<=0;u_shift[3]<=0;
  240. u_shift[2]<=0;u_shift[1]<=0;u_shift[0]<=0;
  241. v_shift[5]<=0;v_shift[4]<=0;v_shift[3]<=0;
  242. v_shift[2]<=0;v_shift[1]<=0;v_shift[0]<=0;
  243. u_odd<=0;u_even<=0;
  244. v_odd<=0;v_even<=0;
  245. u_str=0;
  246. v_str=0;
  247. RGB_even[2]<=0;RGB_even[1]<=0;RGB_even[0]<=0;
  248. y_coe_e<=0;
  249. RGB_odd[2]<=0;RGB_odd[1]<=0;RGB_odd[0]<=0;
  250. y_coe_o<=0;
  251. //test
  252. //common_counter<=0;
  253.  
  254. if(!done&&enable)
  255. M1_state<=S_LEAD_IN_0;
  256. end
  257.  
  258.  
  259. S_LEAD_IN_0:begin
  260. M1_SRAM_address<=U_OFFSET+counter[1]+1;
  261.  
  262. M1_state<=S_LEAD_IN_1;
  263. end
  264.  
  265. S_LEAD_IN_1:begin
  266. M1_SRAM_address<= V_OFFSET+counter[1]+1;
  267.  
  268. M1_state<=S_LEAD_IN_2;
  269. end
  270.  
  271. S_LEAD_IN_2:begin
  272. M1_SRAM_address<=U_OFFSET+counter[1];
  273. y_buf<= SRAM_read_data;
  274.  
  275. M1_state<=S_LEAD_IN_3;
  276. end
  277.  
  278. S_LEAD_IN_3:begin
  279. M1_SRAM_address<=V_OFFSET+counter[1];
  280. u_buf<=SRAM_read_data;
  281.  
  282. M1_state<=S_LEAD_IN_4;
  283. end
  284.  
  285. S_LEAD_IN_4:begin
  286.  
  287. v_shift[1]<=SRAM_read_data[15:8];
  288. v_shift[0]<=SRAM_read_data[7:0];
  289. u_shift[1]<=u_buf[15:8];
  290. u_shift[0]<=u_buf[7:0];
  291.  
  292. M1_state<=S_LEAD_IN_5;
  293. end
  294.  
  295. S_LEAD_IN_5:begin
  296. u_buf<=SRAM_read_data;
  297. u_shift[5]<=SRAM_read_data[15:8];
  298. u_shift[4]<=SRAM_read_data[15:8];
  299. u_shift[3]<=SRAM_read_data[15:8];
  300. u_shift[2]<=SRAM_read_data[7:0];
  301. M1_state<=S_LEAD_IN_6;
  302. end
  303.  
  304. S_LEAD_IN_6:begin
  305. v_shift[5]<=SRAM_read_data[15:8];
  306. v_shift[4]<=SRAM_read_data[15:8];
  307. v_shift[3]<=SRAM_read_data[15:8];
  308. v_shift[2]<=SRAM_read_data[7:0];
  309. M1_state<=S_LEAD_IN_7;
  310. end
  311.  
  312. S_LEAD_IN_7:begin
  313. //shift
  314. u_shift[5]<=u_shift[0];u_shift[4]<=u_shift[5];
  315. u_shift[3]<=u_shift[4];u_shift[2]<=u_shift[3];
  316. u_shift[1]<=u_shift[2];u_shift[0]<=u_shift[1];
  317. v_shift[5]<=v_shift[0];v_shift[4]<=v_shift[5];
  318. v_shift[3]<=v_shift[4];v_shift[2]<=v_shift[3];
  319. v_shift[1]<=v_shift[2];v_shift[0]<=v_shift[1];
  320. /*
  321. op[0]<=21;op[1]<={24'b0,u_shift[0]};
  322. op[2]<=21;op[3]<={24'b0,v_shift[0]};*/
  323. u_odd<=mult_32[0];v_odd<=mult_32[1];
  324.  
  325. M1_state<=S_LEAD_IN_8;
  326. end
  327.  
  328. S_LEAD_IN_8:begin
  329. M1_SRAM_address<=U_OFFSET+counter[1]+2;
  330. counter[1]<=counter[1]+2;
  331. //shift
  332. u_shift[5]<=u_shift[0];u_shift[4]<=u_shift[5];
  333. u_shift[3]<=u_shift[4];u_shift[2]<=u_shift[3];
  334. u_shift[1]<=u_shift[2];u_shift[0]<=u_shift[1];
  335. v_shift[5]<=v_shift[0];v_shift[4]<=v_shift[5];
  336. v_shift[3]<=v_shift[4];v_shift[2]<=v_shift[3];
  337. v_shift[1]<=v_shift[2];v_shift[0]<=v_shift[1];
  338. /*
  339. op[0]<=52;op[1]<={24'b0,u_shift[0]};
  340. op[2]<=52;op[3]<={24'b0,v_shift[0]};*/
  341. u_odd<=u_odd-mult_32[0]+128;v_odd<=v_odd-mult_32[1]+128;
  342.  
  343. M1_state<=S_LEAD_IN_9;
  344. end
  345.  
  346. S_LEAD_IN_9:begin
  347. M1_SRAM_address<=V_OFFSET+counter[1];
  348. //shift
  349. u_shift[5]<=u_shift[0];u_shift[4]<=u_shift[5];
  350. u_shift[3]<=u_shift[4];u_shift[2]<=u_shift[3];
  351. u_shift[1]<=u_shift[2];u_shift[0]<=u_shift[1];
  352. v_shift[5]<=v_shift[0];v_shift[4]<=v_shift[5];
  353. v_shift[3]<=v_shift[4];v_shift[2]<=v_shift[3];
  354. v_shift[1]<=v_shift[2];v_shift[0]<=v_shift[1];
  355. /*
  356. op[0]<=159;op[1]<={24'b0,u_shift[0]};
  357. op[2]<=159;op[3]<={24'b0,v_shift[0]};*/
  358. u_odd<=u_odd+mult_32[0];v_odd<=v_odd+mult_32[1];
  359.  
  360. M1_state<=S_LEAD_IN_10;
  361. end
  362.  
  363. S_LEAD_IN_10:begin
  364.  
  365. //shift
  366. u_shift[5]<=u_shift[0];u_shift[4]<=u_shift[5];
  367. u_shift[3]<=u_shift[4];u_shift[2]<=u_shift[3];
  368. u_shift[1]<=u_shift[2];u_shift[0]<=u_shift[1];
  369. v_shift[5]<=v_shift[0];v_shift[4]<=v_shift[5];
  370. v_shift[3]<=v_shift[4];v_shift[2]<=v_shift[3];
  371. v_shift[1]<=v_shift[2];v_shift[0]<=v_shift[1];
  372. /*
  373. op[0]<=159;op[1]<={24'b0,u_shift[0]};
  374. op[2]<=159;op[3]<={24'b0,v_shift[0]};*/
  375. u_odd<=u_odd+mult_32[0];v_odd<=v_odd+mult_32[1];
  376.  
  377. M1_state<=S_LEAD_IN_11;
  378. end
  379.  
  380. S_LEAD_IN_11:begin
  381. //shift
  382. u_shift[5]<=u_shift[0];u_shift[4]<=u_shift[5];
  383. u_shift[3]<=u_shift[4];u_shift[2]<=u_shift[3];
  384. u_shift[1]<=u_shift[2];u_shift[0]<=u_shift[1];
  385. v_shift[5]<=v_shift[0];v_shift[4]<=v_shift[5];
  386. v_shift[3]<=v_shift[4];v_shift[2]<=v_shift[3];
  387. v_shift[1]<=v_shift[2];v_shift[0]<=v_shift[1];
  388. /*
  389. op[0]<=52;op[1]<={24'b0,u_shift[0]};
  390. op[2]<=52;op[3]<={24'b0,v_shift[0]};*/
  391. u_odd<=u_odd-mult_32[0];v_odd<=v_odd-mult_32[1];
  392. //
  393. u_buf<=SRAM_read_data;
  394.  
  395. M1_state<=S_LEAD_IN_12;
  396. end
  397.  
  398. S_LEAD_IN_12:begin
  399. v_buf<=SRAM_read_data[7:0];
  400. //
  401. counter[2]<=counter[2]+1;
  402. //insert new value
  403. u_shift[0]<=u_buf[15:8];v_shift[0]<=SRAM_read_data[15:8];
  404. /*
  405. op[0]<=21;op[1]<={24'b0,u_shift[0]};
  406. op[2]<=21;op[3]<={24'b0,v_shift[0]};*/
  407. u_odd<=u_odd+mult_32[0];v_odd<=v_odd+mult_32[1];
  408. //storage even UV
  409. u_even<={24'b0,u_shift[4]};v_even<={24'b0,v_shift[4]};
  410.  
  411. M1_state<=S_COMMON_0;
  412. end
  413.  
  414.  
  415. S_COMMON_0:begin
  416. //common_counter<=common_counter+1;
  417. //read mode
  418. CSC_we_n<=1;
  419. M1_SRAM_address<=counter[2];
  420. //shift
  421. u_shift[5]<=u_shift[0];u_shift[4]<=u_shift[5];
  422. u_shift[3]<=u_shift[4];u_shift[2]<=u_shift[3];
  423. u_shift[1]<=u_shift[2];u_shift[0]<=u_shift[1];
  424. v_shift[5]<=v_shift[0];v_shift[4]<=v_shift[5];
  425. v_shift[3]<=v_shift[4];v_shift[2]<=v_shift[3];
  426. v_shift[1]<=v_shift[2];v_shift[0]<=v_shift[1];
  427. //
  428.  
  429. rounds<=rounds+1;
  430. /*
  431. op[0]<=21;op[1]<={24'b0,u_shift[0]};
  432. op[2]<=21;op[3]<={24'b0,v_shift[0]};*/
  433. u_odd<=mult_32[0];v_odd<=mult_32[1];
  434. //storage previous odd value
  435. u_str<=u_odd;v_str<=v_odd;
  436. //RGB_odd
  437. //op[4]<=(y_buf[7:0]-16);op[5]<=76284;
  438. y_coe_o<=mult_32[2];
  439. RGB_odd[0]<=mult_32[2];
  440. //RGB_even
  441. //op[6]<=(y_buf[15:8]-16);op[7]<=76284;
  442. y_coe_e<=mult_32[3];
  443. RGB_even[0]<=mult_32[3];
  444. /*
  445. if(flag&&rounds<155)
  446. v_buf<=SRAM_read_data[7:0];
  447.  
  448. if(rounds>0)begin
  449. CSC_we_n<=0;//write mode
  450. M1_SRAM_address<=counter[0]+RGB_OFFSET-2;
  451. M1_SRAM_write_data<={RGB_even_w[2],RGB_even_w[1]};
  452. counter[0]<=counter[0]+1;
  453. end*/
  454.  
  455. if(!flag)
  456. counter[1]<=counter[1]+1;
  457.  
  458. M1_state<=S_COMMON_1;
  459. end
  460.  
  461. S_COMMON_1:begin
  462. //common_counter<=common_counter+1;
  463.  
  464. //counter[0]<=counter[0]+1;
  465. //shift
  466. u_shift[5]<=u_shift[0];u_shift[4]<=u_shift[5];
  467. u_shift[3]<=u_shift[4];u_shift[2]<=u_shift[3];
  468. u_shift[1]<=u_shift[2];u_shift[0]<=u_shift[1];
  469. v_shift[5]<=v_shift[0];v_shift[4]<=v_shift[5];
  470. v_shift[3]<=v_shift[4];v_shift[2]<=v_shift[3];
  471. v_shift[1]<=v_shift[2];v_shift[0]<=v_shift[1];
  472. /*
  473. op[0]<=52;op[1]<={24'b0,u_shift[0]};
  474. op[2]<=52;op[3]<={24'b0,v_shift[0]};*/
  475. u_odd<=u_odd-mult_32[0]+128;v_odd<=v_odd-mult_32[1]+128;
  476. //RGB_odd
  477. //op[4]<=(u_str[23:8]-128);op[5]<=132251; //u and v only select 16 bit in middle
  478. RGB_odd[0]<=mult_32[2]+RGB_odd[0];
  479. //RGB_even
  480. //op[6]<=(u_even-128);op[7]<=132251;
  481. RGB_even[0]<=mult_32[3]+RGB_even[0];
  482. //
  483.  
  484.  
  485. if(!flag)
  486. M1_SRAM_address<=counter[1]+U_OFFSET;
  487.  
  488. M1_state<=S_COMMON_2;
  489. end
  490.  
  491. S_COMMON_2:begin
  492. //common_counter<=common_counter+1;
  493. //shift
  494. u_shift[5]<=u_shift[0];u_shift[4]<=u_shift[5];
  495. u_shift[3]<=u_shift[4];u_shift[2]<=u_shift[3];
  496. u_shift[1]<=u_shift[2];u_shift[0]<=u_shift[1];
  497. v_shift[5]<=v_shift[0];v_shift[4]<=v_shift[5];
  498. v_shift[3]<=v_shift[4];v_shift[2]<=v_shift[3];
  499. v_shift[1]<=v_shift[2];v_shift[0]<=v_shift[1];
  500. /*
  501. op[0]<=159;op[1]<={24'b0,u_shift[0]};
  502. op[2]<=159;op[3]<={24'b0,v_shift[0]};*/
  503. u_odd<=u_odd+mult_32[0];v_odd<=v_odd+mult_32[1];
  504. //RGB_odd
  505. //op[4]<=(u_str[23:8]-128);op[5]<=25624; //u and v only select 16 bit in middle
  506. RGB_odd[1]<=y_coe_o-mult_32[2];
  507. //RGB_even
  508. //op[6]<=(u_even-128);op[7]<=25624;
  509. RGB_even[1]<=y_coe_e-mult_32[3];
  510. if(!flag)
  511. M1_SRAM_address<=counter[1]+V_OFFSET;
  512.  
  513. M1_state<=S_COMMON_3;
  514. end
  515.  
  516. S_COMMON_3:begin
  517. //common_counter<=common_counter+1;
  518. y_buf<=SRAM_read_data;
  519. counter[2]<=counter[2]+1;
  520. //write mode
  521. CSC_we_n<=0;
  522. M1_SRAM_address<=counter[0]+RGB_OFFSET+2;
  523. counter[0]<=counter[0]+1;
  524. //M1_SRAM_write_data<={RGB_odd_w[1],RGB_odd_w[0]};
  525. //shift
  526. u_shift[5]<=u_shift[0];u_shift[4]<=u_shift[5];
  527. u_shift[3]<=u_shift[4];u_shift[2]<=u_shift[3];
  528. u_shift[1]<=u_shift[2];u_shift[0]<=u_shift[1];
  529. v_shift[5]<=v_shift[0];v_shift[4]<=v_shift[5];
  530. v_shift[3]<=v_shift[4];v_shift[2]<=v_shift[3];
  531. v_shift[1]<=v_shift[2];v_shift[0]<=v_shift[1];
  532. /*
  533. op[0]<=159;op[1]<={24'b0,u_shift[0]};
  534. op[2]<=159;op[3]<={24'b0,v_shift[0]};*/
  535. u_odd<=u_odd+mult_32[0];v_odd<=v_odd+mult_32[1];
  536. //RGB_odd
  537. //op[4]<=(v_str[23:8]-128);op[5]<=53281; //u and v only select 16 bit in middle
  538. RGB_odd[1]<=RGB_odd[1]-mult_32[2];
  539. //RGB_even
  540. //op[6]<=(v_even-128);op[7]<=53281;
  541. RGB_even[1]<=RGB_even[1]-mult_32[3];
  542.  
  543. M1_state<=S_COMMON_4;
  544. end
  545.  
  546. S_COMMON_4:begin
  547. //common_counter<=common_counter+1;
  548. //write mode
  549. CSC_we_n<=0;
  550. M1_SRAM_address<=counter[0]+RGB_OFFSET;
  551. counter[0]<=counter[0]+1;
  552. //M1_SRAM_write_data<={RGB_even_w[0],RGB_odd_w[2]};
  553. //shift
  554. u_shift[5]<=u_shift[0];u_shift[4]<=u_shift[5];
  555. u_shift[3]<=u_shift[4];u_shift[2]<=u_shift[3];
  556. u_shift[1]<=u_shift[2];u_shift[0]<=u_shift[1];
  557. v_shift[5]<=v_shift[0];v_shift[4]<=v_shift[5];
  558. v_shift[3]<=v_shift[4];v_shift[2]<=v_shift[3];
  559. v_shift[1]<=v_shift[2];v_shift[0]<=v_shift[1];
  560. /*
  561. op[0]<=52;op[1]<={24'b0,u_shift[0]};
  562. op[2]<=52;op[3]<={24'b0,v_shift[0]};*/
  563. u_odd<=u_odd-mult_32[0];v_odd<=v_odd-mult_32[1];
  564. //RGB_odd
  565. //op[4]<=(v_str[23:8]-128);op[5]<=104595; //u and v only select 16 bit in middle
  566. RGB_odd[2]<=y_coe_o+mult_32[2];
  567. //RGB_even
  568. //op[6]<=(v_even-128);op[7]<=104595;
  569. RGB_even[2]<=y_coe_e+mult_32[3];
  570. //
  571. if(!flag)
  572. u_buf<=SRAM_read_data;
  573.  
  574. M1_state<=S_COMMON_5;
  575. end
  576.  
  577. S_COMMON_5:begin
  578. //common_counter<=0;
  579. //write mode
  580. CSC_we_n<=0;
  581. M1_SRAM_address<=counter[0]+RGB_OFFSET-2;
  582. //M1_SRAM_write_data<={RGB_even_w[2],RGB_even_w[1]};
  583. counter[0]<=counter[0]+1;
  584. /*
  585. op[0]<=21;op[1]<={24'b0,u_shift[0]};
  586. op[2]<=21;op[3]<={24'b0,v_shift[0]};*/
  587. u_odd<=u_odd+mult_32[0];v_odd<=v_odd+mult_32[1];
  588. //even value storage
  589. u_even<={24'b0,u_shift[4]};v_even<={24'b0,v_shift[4]};
  590. //u value update
  591. u_shift[0]<=u_buf[15:8];v_shift[0]<=SRAM_read_data[15:8];
  592. if(flag)begin
  593. //u_buf<=SRAM_read_data;
  594. u_shift[0]<=u_buf[7:0];v_shift[0]<=v_buf;
  595. end
  596.  
  597. if(!flag&&rounds<155)
  598. v_buf<=SRAM_read_data[7:0];
  599. if(lead_out)
  600. M1_state<=S_LEAD_OUT_0;
  601. else begin
  602. M1_state<=S_COMMON_0;
  603. if(rounds<155)
  604. flag<=~flag;
  605. end
  606. end
  607.  
  608. S_LEAD_OUT_0:begin
  609. CSC_we_n<=1;//read mode
  610. M1_SRAM_address<=counter[2];
  611. //clear rounds and flag_1
  612. rounds<=0;
  613. //flag_1<=0;
  614. //
  615. //counter[2]<=counter[2]+1;
  616. //storage previous odd value
  617. u_str<=u_odd;v_str<=v_odd;
  618. //RGB_odd
  619. //op[4]<=(y_buf[7:0]-16);op[5]<=76284;
  620. y_coe_o<=mult_32[2];
  621. RGB_odd[0]<=mult_32[2];
  622. //RGB_even
  623. //op[6]<=(y_buf[15:8]-16);op[7]<=76284;
  624. y_coe_e<=mult_32[3];
  625. RGB_even[0]<=mult_32[3];
  626. //
  627.  
  628. M1_state<=S_LEAD_OUT_1;
  629. end
  630.  
  631. S_LEAD_OUT_1:begin
  632.  
  633. //RGB_odd
  634. //op[4]<=(u_str[23:8]-128);op[5]<=132251; //u and v only select 16 bit in middle
  635. RGB_odd[0]<=mult_32[2]+RGB_odd[0];
  636. //RGB_even
  637. //op[6]<=(u_even-128);op[7]<=132251;
  638. RGB_even[0]<=mult_32[3]+RGB_even[0];
  639. //
  640.  
  641. M1_state<=S_LEAD_OUT_2;
  642. end
  643.  
  644. S_LEAD_OUT_2:begin
  645. //RGB_odd
  646. //op[4]<=(u_str[23:8]-128);op[5]<=25624; //u and v only select 16 bit in middle
  647. RGB_odd[1]<=y_coe_o-mult_32[2];
  648. //RGB_even
  649. //op[6]<=(u_even-128);op[7]<=25624;
  650. RGB_even[1]<=y_coe_e-mult_32[3];
  651.  
  652. M1_state<=S_LEAD_OUT_3;
  653. end
  654.  
  655. S_LEAD_OUT_3:begin
  656. //write mode
  657. CSC_we_n<=0;
  658. M1_SRAM_address<=counter[0]+RGB_OFFSET+2;
  659. counter[0]<=counter[0]+1;
  660. //RGB_odd
  661. //op[4]<=(v_str[23:8]-128);op[5]<=53281; //u and v only select 16 bit in middle
  662. RGB_odd[1]<=RGB_odd[1]-mult_32[2];
  663. //RGB_even
  664. //op[6]<=(v_even-128);op[7]<=53281;
  665. RGB_even[1]<=RGB_even[1]-mult_32[3];
  666. //
  667. M1_state<=S_LEAD_OUT_4;
  668. end
  669.  
  670. S_LEAD_OUT_4:begin
  671. //write mode
  672. CSC_we_n<=0;
  673. M1_SRAM_address<=counter[0]+RGB_OFFSET;
  674. counter[0]<=counter[0]+1;
  675. //M1_SRAM_write_data<={RGB_odd_w[1],RGB_odd_w[0]};
  676. //RGB_odd
  677. //op[4]<=(v_str[23:8]-128);op[5]<=104595; //u and v only select 16 bit in middle
  678. RGB_odd[2]<=y_coe_o+mult_32[2];
  679. //RGB_even
  680. //op[6]<=(v_even-128);op[7]<=104595;
  681. RGB_even[2]<=y_coe_e+mult_32[3];
  682.  
  683. M1_state<=S_LEAD_OUT_5;
  684. end
  685.  
  686. S_LEAD_OUT_5:begin
  687. //write mode
  688. CSC_we_n<=0;
  689. M1_SRAM_address<=counter[0]+RGB_OFFSET-2;
  690. counter[0]<=counter[0]+1;
  691. //M1_SRAM_write_data<={RGB_even_w[0],RGB_odd_w[2]};
  692.  
  693. M1_state<=S_LEAD_OUT_6;
  694. end
  695.  
  696. S_LEAD_OUT_6:begin
  697. CSC_we_n<=1;
  698. counter[1]<=counter[1]+1;
  699. //M1_SRAM_write_data<={RGB_even_w[2],RGB_even_w[1]};
  700. M1_SRAM_address<=counter[2];
  701.  
  702. M1_state<=S_LEAD_IN_0;
  703. if(counter[2]>=U_OFFSET)
  704. M1_state<=S_FINISH_FILL_SRAM;
  705. end
  706.  
  707.  
  708.  
  709. S_FINISH_FILL_SRAM:begin
  710. CSC_we_n <= 1'b1;
  711. done<=1;
  712.  
  713. M1_state<=M1_IDLE;
  714. end
  715.  
  716. default: M1_state<=M1_IDLE;
  717. endcase
  718. end
  719. end
  720.  
  721.  
  722. endmodule
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