Advertisement
Mikek_GodTEc

Fairwaves_xtrx Build with PCI-e

Dec 21st, 2021
100
0
Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
text 331.88 KB | None | 0 0
  1. (Litex_Nov2021) mikek@mike-AERO-17:~/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets$
  2. (Litex_Nov2021) mikek@mike-AERO-17:~/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets$ rm -rf build/fairwaves_xtrx/
  3. (Litex_Nov2021) mikek@mike-AERO-17:~/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets$ ./fairwaves_xtrx.py --uart-name=crossover --with-pcie --build --driver
  4. INFO:SoC: __ _ __ _ __
  5. INFO:SoC: / / (_) /____ | |/_/
  6. INFO:SoC: / /__/ / __/ -_)> <
  7. INFO:SoC: /____/_/\__/\__/_/|_|
  8. INFO:SoC: Build your hardware, easily!
  9. INFO:SoC:--------------------------------------------------------------------------------
  10. INFO:SoC:Creating SoC... (2021-12-21 16:15:41)
  11. INFO:SoC:--------------------------------------------------------------------------------
  12. INFO:SoC:FPGA device : xc7a50tcpg236-2.
  13. INFO:SoC:System clock: 125.000MHz.
  14. INFO:SoCBusHandler:Creating Bus Handler...
  15. INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
  16. INFO:SoCBusHandler:Adding reserved Bus Regions...
  17. INFO:SoCBusHandler:Bus Handler created.
  18. INFO:SoCCSRHandler:Creating CSR Handler...
  19. INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
  20. INFO:SoCCSRHandler:Adding reserved CSRs...
  21. INFO:SoCCSRHandler:CSR Handler created.
  22. INFO:SoCIRQHandler:Creating IRQ Handler...
  23. INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
  24. INFO:SoCIRQHandler:Adding reserved IRQs...
  25. INFO:SoCIRQHandler:IRQ Handler created.
  26. INFO:SoC:--------------------------------------------------------------------------------
  27. INFO:SoC:Initial SoC:
  28. INFO:SoC:--------------------------------------------------------------------------------
  29. INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
  30. INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
  31. INFO:SoC:IRQ Handler (up to 32 Locations).
  32. INFO:SoC:--------------------------------------------------------------------------------
  33. INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False.
  34. INFO:SoC:CPU overriding rom mapping from 0x0 to 0x0.
  35. INFO:SoC:CPU overriding sram mapping from 0x1000000 to 0x10000000.
  36. INFO:SoC:CPU overriding main_ram mapping from 0x40000000 to 0x40000000.
  37. INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
  38. INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
  39. INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00020000, Mode: R, Cached: True Linker: False.
  40. INFO:SoCBusHandler:rom added as Bus Slave.
  41. INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00020000, Mode: R, Cached: True Linker: False.
  42. INFO:SoCBusHandler:sram Region added at Origin: 0x10000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
  43. INFO:SoCBusHandler:sram added as Bus Slave.
  44. INFO:SoC:RAM sram added Origin: 0x10000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
  45. INFO:SoCIRQHandler:uart IRQ allocated at Location 0.
  46. INFO:SoCIRQHandler:timer0 IRQ allocated at Location 1.
  47. INFO:SoCBusHandler:master2 added as Bus Master.
  48. INFO:SoCBusHandler:csr Region added at Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False.
  49. INFO:SoCBusHandler:csr added as Bus Slave.
  50. INFO:SoCCSRHandler:bridge added as CSR Master.
  51. INFO:SoCBusHandler:Interconnect: InterconnectShared (3 <-> 3).
  52. INFO:SoCCSRHandler:ctrl CSR allocated at Location 0.
  53. INFO:SoCCSRHandler:flash CSR allocated at Location 1.
  54. INFO:SoCCSRHandler:flash_cs_n CSR allocated at Location 2.
  55. INFO:SoCCSRHandler:icap CSR allocated at Location 3.
  56. INFO:SoCCSRHandler:identifier_mem CSR allocated at Location 4.
  57. INFO:SoCCSRHandler:leds CSR allocated at Location 5.
  58. INFO:SoCCSRHandler:pcie_dma0 CSR allocated at Location 6.
  59. INFO:SoCCSRHandler:pcie_msi CSR allocated at Location 7.
  60. INFO:SoCCSRHandler:pcie_phy CSR allocated at Location 8.
  61. INFO:SoCCSRHandler:timer0 CSR allocated at Location 9.
  62. INFO:SoCCSRHandler:uart CSR allocated at Location 10.
  63. INFO:SoC:--------------------------------------------------------------------------------
  64. INFO:SoC:Finalized SoC:
  65. INFO:SoC:--------------------------------------------------------------------------------
  66. INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
  67. IO Regions: (1)
  68. io0 : Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False
  69. Bus Regions: (3)
  70. rom : Origin: 0x00000000, Size: 0x00020000, Mode: R, Cached: True Linker: False
  71. sram : Origin: 0x10000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False
  72. csr : Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False
  73. Bus Masters: (3)
  74. - cpu_bus0
  75. - cpu_bus1
  76. - master2
  77. Bus Slaves: (3)
  78. - rom
  79. - sram
  80. - csr
  81. INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
  82. CSR Locations: (11)
  83. - ctrl : 0
  84. - flash : 1
  85. - flash_cs_n : 2
  86. - icap : 3
  87. - identifier_mem : 4
  88. - leds : 5
  89. - pcie_dma0 : 6
  90. - pcie_msi : 7
  91. - pcie_phy : 8
  92. - timer0 : 9
  93. - uart : 10
  94. INFO:SoC:IRQ Handler (up to 32 Locations).
  95. IRQ Locations: (2)
  96. - uart : 0
  97. - timer0 : 1
  98. INFO:SoC:--------------------------------------------------------------------------------
  99. make: Entering directory '/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/libc'
  100. if [ -d "/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex/litex/soc/software/libc/riscv" ]; then \
  101. cp /home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex/litex/soc/software/libc/riscv/* /home/mikek/.local/lib/python3.8/site-packages/pythondata_software_picolibc/data/newlib/libc/machine/riscv/ ;\
  102. fi
  103. meson /home/mikek/.local/lib/python3.8/site-packages/pythondata_software_picolibc/data \
  104. -Dmultilib=false \
  105. -Dpicocrt=false \
  106. -Datomic-ungetc=false \
  107. -Dthread-local-storage=false \
  108. -Dio-long-long=true \
  109. -Dformat-default=integer \
  110. -Dincludedir=picolibc/riscv64-unknown-elf/include \
  111. -Dlibdir=picolibc/riscv64-unknown-elf/lib \
  112. --cross-file cross.txt
  113. WARNING: Unknown CPU family riscv, please report this at https://github.com/mesonbuild/meson/issues/new
  114. The Meson build system
  115. Version: 0.60.2
  116. Source dir: /home/mikek/.local/lib/python3.8/site-packages/pythondata_software_picolibc/data
  117. Build dir: /home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/libc
  118. Build type: cross build
  119. Project name: picolibc
  120. Project version: 1.7.4
  121. C compiler for the host machine: riscv64-unknown-elf-gcc (gcc 8.3.0 "riscv64-unknown-elf-gcc (SiFive GCC 8.3.0-2019.08.0) 8.3.0")
  122. C linker for the host machine: riscv64-unknown-elf-gcc ld.bfd 2.32.0-2019
  123. C compiler for the build machine: ccache cc (gcc 9.3.0 "cc (Ubuntu 9.3.0-17ubuntu1~20.04) 9.3.0")
  124. C linker for the build machine: cc ld.bfd 2.34
  125. Build machine cpu family: x86_64
  126. Build machine cpu: x86_64
  127. Host machine cpu family: riscv
  128. Host machine cpu: vexriscv
  129. Target machine cpu family: riscv
  130. Target machine cpu: vexriscv
  131. Checking if "long double check" : compiles: YES
  132. Checking if "long double same as double" : compiles: NO
  133. Checking if "long double mantissa is 64 bits" : compiles: NO
  134. Checking if "long double mantissa is 113 bits" : compiles: YES
  135. Compiler for C supports arguments -fno-common: YES
  136. Compiler for C supports arguments -frounding-math: YES
  137. Compiler for C supports arguments -Wno-unsupported-floating-point-opt: NO
  138. Compiler for C supports arguments -fno-stack-protector: YES
  139. Program riscv64-unknown-elf-gcc-nm found: YES
  140. Program scripts/duplicate-names found: YES (/home/mikek/.local/lib/python3.8/site-packages/pythondata_software_picolibc/data/scripts/duplicate-names)
  141. Compiler for C supports link arguments -Wl,--defsym=_start=0: YES
  142. Compiler for C supports link arguments -Wl,-alias,main,testalias: NO
  143. Compiler for C supports function attribute alias: YES
  144. Compiler for C supports function attribute format: YES
  145. Configuring picolibc.specs using configuration
  146. Configuring picolibcpp.specs using configuration
  147. Configuring test.specs using configuration
  148. Configuring picolibc.ld using configuration
  149. Configuring picolibcpp.ld using configuration
  150. Compiler for C supports arguments -Werror=implicit-function-declaration: YES
  151. Compiler for C supports arguments -Werror=vla: YES
  152. Compiler for C supports arguments -Warray-bounds: YES
  153. Compiler for C supports arguments -Wold-style-definition: YES
  154. Compiler for C supports arguments -Wno-missing-braces: YES
  155. Compiler for C supports arguments -Wno-implicit-int: YES
  156. Compiler for C supports arguments -Wno-return-type: YES
  157. Compiler for C supports arguments -Wno-unused-command-line-argument: NO
  158. Checking if "packed structs may contain bitfields" : compiles: YES
  159. Checking if "has __builtin_mul_overflow" : links: YES
  160. Checking if "supports _Complex" : compiles: YES
  161. Checking if "has __builtin_expect" : links: YES
  162. Compiler for C supports arguments -Werror: YES
  163. Checking if "attribute __alloc_size__" : compiles: NO
  164. Compiler for C supports arguments -Werror: YES (cached)
  165. Checking if "attributes constructor/destructor" : compiles: YES
  166. Checking if "test for __builtin_alloca" : links: YES
  167. Checking if "test for __builtin_ffs" : links: YES
  168. Checking if "test for __builtin_ffsl" : links: YES
  169. Checking if "test for __builtin_ffsll" : links: YES
  170. Checking if "test for __builtin_ctz" : links: YES
  171. Checking if "test for __builtin_ctzl" : links: YES
  172. Checking if "test for __builtin_ctzll" : links: YES
  173. Checking if "test for __builtin_copysignl" : links: YES
  174. Checking if "test for __builtin_copysign" : links: YES
  175. Checking if "test for __builtin_isinfl" : links: YES
  176. Checking if "test for __builtin_isinf" : links: YES
  177. Checking if "test for __builtin_isnanl" : links: YES
  178. Checking if "test for __builtin_isnan" : links: YES
  179. Checking if "test for __builtin_finitel" : links: YES
  180. Checking if "test for __builtin_isfinite" : links: YES
  181. Compiler for C supports arguments -fno-tree-loop-distribute-patterns: YES
  182. Compiler for C supports arguments -Werror=attributes: YES
  183. Checking if "no_builtin attribute" : compiles: NO
  184. Compiler for C supports function attribute always_inline: YES
  185. Compiler for C supports function attribute gnu_inline: YES
  186. Compiler for C supports arguments -fno-builtin: YES
  187. Compiler for C supports arguments -ffunction-sections: YES
  188. Compiler for C supports arguments -fstack-protector-all: YES
  189. Compiler for C supports arguments -fstack-protector-strong: YES
  190. Compiler for C supports arguments -fno-builtin-malloc: YES
  191. Compiler for C supports arguments -fno-builtin-free: YES
  192. Message: libc/string/memcpy.c: machine overrides generic
  193. Message: libc/string/memmove.S: machine overrides generic
  194. Message: libc/string/memset.S: machine overrides generic
  195. Message: libc/string/strcpy.c: machine overrides generic
  196. Message: libc/string/strlen.c: machine overrides generic
  197. Message: libc/string/strcmp.S: machine overrides generic
  198. Message: libc/include/sys/fenv.h: machine overrides generic
  199. Message: libc/include/machine/math.h: machine overrides generic
  200. Message: libm/math/s_fabs.c: machine overrides generic
  201. Message: libm/math/s_sqrt.c: machine overrides generic
  202. Message: libm/math/sf_fabs.c: machine overrides generic
  203. Message: libm/math/sf_sqrt.c: machine overrides generic
  204. Message: libm/common/s_finite.c: machine overrides generic
  205. Message: libm/common/s_copysign.c: machine overrides generic
  206. Message: libm/common/s_isinf.c: machine overrides generic
  207. Message: libm/common/s_isnan.c: machine overrides generic
  208. Message: libm/common/s_fma.c: machine overrides generic
  209. Message: libm/common/s_fmax.c: machine overrides generic
  210. Message: libm/common/s_fmin.c: machine overrides generic
  211. Message: libm/common/s_fpclassify.c: machine overrides generic
  212. Message: libm/common/s_lrint.c: machine overrides generic
  213. Message: libm/common/s_llrint.c: machine overrides generic
  214. Message: libm/common/s_lround.c: machine overrides generic
  215. Message: libm/common/s_llround.c: machine overrides generic
  216. Message: libm/common/sf_finite.c: machine overrides generic
  217. Message: libm/common/sf_copysign.c: machine overrides generic
  218. Message: libm/common/sf_isinf.c: machine overrides generic
  219. Message: libm/common/sf_isnan.c: machine overrides generic
  220. Message: libm/common/sf_fma.c: machine overrides generic
  221. Message: libm/common/sf_fmax.c: machine overrides generic
  222. Message: libm/common/sf_fmin.c: machine overrides generic
  223. Message: libm/common/sf_fpclassify.c: machine overrides generic
  224. Message: libm/common/sf_lrint.c: machine overrides generic
  225. Message: libm/common/sf_llrint.c: machine overrides generic
  226. Message: libm/common/sf_lround.c: machine overrides generic
  227. Message: libm/common/sf_llround.c: machine overrides generic
  228. Message: libm/fenv/feclearexcept.c: machine overrides generic
  229. Message: libm/fenv/fegetenv.c: machine overrides generic
  230. Message: libm/fenv/fegetexceptflag.c: machine overrides generic
  231. Message: libm/fenv/fegetround.c: machine overrides generic
  232. Message: libm/fenv/feholdexcept.c: machine overrides generic
  233. Message: libm/fenv/feraiseexcept.c: machine overrides generic
  234. Message: libm/fenv/fesetenv.c: machine overrides generic
  235. Message: libm/fenv/fesetexceptflag.c: machine overrides generic
  236. Message: libm/fenv/fesetround.c: machine overrides generic
  237. Message: libm/fenv/fetestexcept.c: machine overrides generic
  238. Message: libm/fenv/feupdateenv.c: machine overrides generic
  239. Configuring picolibc.h using configuration
  240. Build targets in project: 9
  241.  
  242. picolibc 1.7.4
  243.  
  244. User defined options
  245. Cross files : cross.txt
  246. includedir : picolibc/riscv64-unknown-elf/include
  247. libdir : picolibc/riscv64-unknown-elf/lib
  248. atomic-ungetc : false
  249. format-default : integer
  250. io-long-long : true
  251. multilib : false
  252. picocrt : false
  253. thread-local-storage: false
  254.  
  255. Found ninja-1.10.0 at /usr/bin/ninja
  256. meson compile
  257. [851/851] Generating newlib/libc_duplicates with a custom command
  258. cp newlib/libc.a __libc.a
  259. CC _libc.a
  260. AR _libc.a
  261. cp __libc.a _libc.a
  262. CC libc.a
  263. AR libc.a
  264. cp _libc.a libc.a
  265. make: Leaving directory '/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/libc'
  266. make: Entering directory '/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/libcompiler_rt'
  267. CC umodsi3.o
  268. CC udivsi3.o
  269. CC divsi3.o
  270. CC modsi3.o
  271. CC comparesf2.o
  272. /home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-software-compiler_rt/pythondata_software_compiler_rt/data/lib/builtins/comparesf2.c:85:1: warning: function declaration isn't a prototype [-Wstrict-prototypes]
  273. FNALIAS(__cmpsf2, __lesf2);
  274. ^~~~~~~
  275. CC comparedf2.o
  276. /home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-software-compiler_rt/pythondata_software_compiler_rt/data/lib/builtins/comparedf2.c:85:1: warning: function declaration isn't a prototype [-Wstrict-prototypes]
  277. FNALIAS(__cmpdf2, __ledf2);
  278. ^~~~~~~
  279. CC negsf2.o
  280. CC negdf2.o
  281. CC addsf3.o
  282. CC subsf3.o
  283. CC mulsf3.o
  284. CC divsf3.o
  285. CC lshrdi3.o
  286. CC muldi3.o
  287. CC divdi3.o
  288. CC ashldi3.o
  289. CC ashrdi3.o
  290. CC udivmoddi4.o
  291. CC floatsisf.o
  292. CC floatunsisf.o
  293. CC fixsfsi.o
  294. CC fixdfdi.o
  295. CC fixunssfsi.o
  296. CC fixunsdfdi.o
  297. CC adddf3.o
  298. CC subdf3.o
  299. CC muldf3.o
  300. CC divdf3.o
  301. CC floatsidf.o
  302. CC floatunsidf.o
  303. CC floatdidf.o
  304. CC fixdfsi.o
  305. CC fixunsdfsi.o
  306. CC clzsi2.o
  307. CC ctzsi2.o
  308. CC udivdi3.o
  309. CC umoddi3.o
  310. CC moddi3.o
  311. CC ucmpdi2.o
  312. CC mulsi3.o
  313. AR libcompiler_rt.a
  314. make: Leaving directory '/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/libcompiler_rt'
  315. make: Entering directory '/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/libbase'
  316. CC crc16.o
  317. CC crc32.o
  318. CC console.o
  319. CC system.o
  320. CC progress.o
  321. CC memtest.o
  322. CC uart.o
  323. CC spiflash.o
  324. CC i2c.o
  325. AR libbase.a
  326. make: Leaving directory '/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/libbase'
  327. make: Entering directory '/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/libfatfs'
  328. CC ffunicode.o
  329. CC ff.o
  330. AR libfatfs.a
  331. make: Leaving directory '/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/libfatfs'
  332. make: Entering directory '/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/liblitespi'
  333. CC spiflash.o
  334. AR liblitespi.a
  335. make: Leaving directory '/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/liblitespi'
  336. make: Entering directory '/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/liblitedram'
  337. CC sdram.o
  338. CC bist.o
  339. CC sdram_dbg.o
  340. AR liblitedram.a
  341. make: Leaving directory '/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/liblitedram'
  342. make: Entering directory '/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/libliteeth'
  343. CC udp.o
  344. CC tftp.o
  345. /home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex/litex/soc/software/libliteeth/tftp.c: In function 'tftp_get':
  346. /home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex/litex/soc/software/libliteeth/tftp.c:125:19: warning: passing argument 1 of 'udp_set_callback' from incompatible pointer type [-Wincompatible-pointer-types]
  347. udp_set_callback(rx_callback);
  348. ^~~~~~~~~~~
  349. In file included from /home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex/litex/soc/software/libliteeth/tftp.c:15:
  350. /home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex/litex/soc/software/libliteeth/udp.h:19:36: note: expected 'udp_callback' {aka 'void (*)(unsigned int, short unsigned int, short unsigned int, void *, unsigned int)'} but argument is of type 'void (*)(uint32_t, uint16_t, uint16_t, void *, unsigned int)' {aka 'void (*)(long unsigned int, short unsigned int, short unsigned int, void *, unsigned int)'}
  351. void udp_set_callback(udp_callback callback);
  352. ~~~~~~~~~~~~~^~~~~~~~
  353. /home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex/litex/soc/software/libliteeth/tftp.c: In function 'tftp_put':
  354. /home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex/litex/soc/software/libliteeth/tftp.c:181:19: warning: passing argument 1 of 'udp_set_callback' from incompatible pointer type [-Wincompatible-pointer-types]
  355. udp_set_callback(rx_callback);
  356. ^~~~~~~~~~~
  357. In file included from /home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex/litex/soc/software/libliteeth/tftp.c:15:
  358. /home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex/litex/soc/software/libliteeth/udp.h:19:36: note: expected 'udp_callback' {aka 'void (*)(unsigned int, short unsigned int, short unsigned int, void *, unsigned int)'} but argument is of type 'void (*)(uint32_t, uint16_t, uint16_t, void *, unsigned int)' {aka 'void (*)(long unsigned int, short unsigned int, short unsigned int, void *, unsigned int)'}
  359. void udp_set_callback(udp_callback callback);
  360. ~~~~~~~~~~~~~^~~~~~~~
  361. CC mdio.o
  362. AR libliteeth.a
  363. make: Leaving directory '/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/libliteeth'
  364. make: Entering directory '/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/liblitesdcard'
  365. CC sdcard.o
  366. CC spisdcard.o
  367. AR liblitesdcard.a
  368. make: Leaving directory '/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/liblitesdcard'
  369. make: Entering directory '/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/liblitesata'
  370. CC sata.o
  371. AR liblitesata.a
  372. make: Leaving directory '/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/liblitesata'
  373. make: Entering directory '/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/bios'
  374. CC crt0.o
  375. CC isr.o
  376. CC boot-helper.o
  377. CC boot.o
  378. CC helpers.o
  379. CC cmd_bios.o
  380. CC cmd_mem.o
  381. CC cmd_boot.o
  382. CC cmd_i2c.o
  383. CC cmd_spiflash.o
  384. CC cmd_litedram.o
  385. CC cmd_liteeth.o
  386. CC cmd_litesdcard.o
  387. CC cmd_litesata.o
  388. CC sim_debug.o
  389. CC main.o
  390. CC complete.o
  391. CC readline.o
  392. CC bios.elf
  393. chmod -x bios.elf
  394. OBJCOPY bios.bin
  395. chmod -x bios.bin
  396. python3 -m litex.soc.software.mkmscimg bios.bin --little
  397. python3 -m litex.soc.software.memusage bios.elf /home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/bios/../include/generated/regions.ld riscv64-unknown-elf
  398.  
  399. ROM usage: 20.16KiB (15.75%)
  400. RAM usage: 1.60KiB (20.02%)
  401.  
  402. make: Leaving directory '/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/software/bios'
  403. INFO:SoC:Initializing ROM rom with contents (Size: 0x50b0).
  404. INFO:SoC:Auto-Resizing ROM rom from 0x20000 to 0x50b0.
  405.  
  406. ****** Vivado v2021.2 (64-bit)
  407. **** SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
  408. **** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
  409. ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
  410.  
  411. source fairwaves_xtrx.tcl
  412. # create_project -force -name fairwaves_xtrx -part xc7a50tcpg236-2
  413. # set_msg_config -id {Common 17-55} -new_severity {Warning}
  414. # read_verilog {/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v}
  415. # read_verilog {/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litepcie/litepcie/phy/xilinx_s7_gen2/pcie_pipe_clock.v}
  416. # read_verilog {/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litepcie/litepcie/phy/xilinx_s7_gen2/pcie_s7_support.v}
  417. # read_verilog {/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v}
  418. # read_xdc fairwaves_xtrx.xdc
  419. # set_property PROCESSING_ORDER EARLY [get_files fairwaves_xtrx.xdc]
  420. # create_ip -vendor xilinx.com -name pcie_7x -module_name pcie_s7
  421. INFO: [IP_Flow 19-234] Refreshing IP repositories
  422. INFO: [IP_Flow 19-1704] No user IP repositories specified
  423. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/mikek/Documents/Xilinx_FPGA/tools/Vivado/2021.2/data/ip'.
  424. # set obj [get_ips pcie_s7]
  425. # set_property -dict [list \
  426. # CONFIG.Bar0_Scale {Megabytes} \
  427. # CONFIG.Bar0_Size {1} \
  428. # CONFIG.Buf_Opt_BMA {True} \
  429. # CONFIG.Component_Name {pcie} \
  430. # CONFIG.Device_ID {7022} \
  431. # CONFIG.IntX_Generation {False} \
  432. # CONFIG.Interface_Width {64_bit} \
  433. # CONFIG.Legacy_Interrupt {None} \
  434. # CONFIG.Link_Speed {5.0_GT/s} \
  435. # CONFIG.MSI_64b {False} \
  436. # CONFIG.Max_Payload_Size {512_bytes} \
  437. # CONFIG.Maximum_Link_Width {X2} \
  438. # CONFIG.PCIe_Blk_Locn {X0Y0} \
  439. # CONFIG.Ref_Clk_Freq {100_MHz} \
  440. # CONFIG.Trans_Buf_Pipeline {None} \
  441. # CONFIG.Trgt_Link_Speed {4'h2} \
  442. # CONFIG.User_Clk_Freq {125} \
  443. # ] $obj
  444. WARNING: [Vivado 12-3523] Attempt to change 'Component_Name' from 'pcie_s7' to 'pcie' is not allowed and is ignored.
  445. WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'Legacy_Interrupt' from 'NONE' to 'None' has been ignored for IP 'pcie_s7'
  446. # synth_ip $obj
  447. CRITICAL WARNING: [Vivado 12-5447] synth_ip is not supported in project mode, please use non-project mode.
  448. INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'pcie_s7'...
  449. INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'pcie_s7'...
  450. INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'pcie_s7'...
  451. INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'pcie_s7'...
  452. INFO: [IP_Flow 19-234] Refreshing IP repositories
  453. INFO: [IP_Flow 19-1704] No user IP repositories specified
  454. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/mikek/Documents/Xilinx_FPGA/tools/Vivado/2021.2/data/ip'.
  455. Command: synth_design -top pcie_s7 -part xc7a50tcpg236-2 -mode out_of_context
  456. Starting synth_design
  457. Attempting to get a license for feature 'Synthesis' and/or device 'xc7a50t'
  458. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a50t'
  459. INFO: [Device 21-403] Loading part xc7a50tcpg236-2
  460. INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
  461. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
  462. INFO: [Synth 8-7075] Helper process launched with PID 82089
  463. ---------------------------------------------------------------------------------
  464. Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2639.316 ; gain = 0.000 ; free physical = 1733 ; free virtual = 20578
  465. ---------------------------------------------------------------------------------
  466. INFO: [Synth 8-6157] synthesizing module 'pcie_s7' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/synth/pcie_s7.v:66]
  467. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_pcie2_top' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pcie2_top.v:59]
  468. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_core_top' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_core_top.v:65]
  469. INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_single' [/home/mikek/Documents/Xilinx_FPGA/tools/Vivado/2021.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153]
  470. INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_single' (1#1) [/home/mikek/Documents/Xilinx_FPGA/tools/Vivado/2021.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153]
  471. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_pcie_top' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pcie_top.v:62]
  472. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_axi_basic_top' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_axi_basic_top.v:68]
  473. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_axi_basic_rx' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_axi_basic_rx.v:70]
  474. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_axi_basic_rx_pipeline' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_axi_basic_rx_pipeline.v:70]
  475. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_axi_basic_rx_pipeline' (2#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_axi_basic_rx_pipeline.v:70]
  476. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_axi_basic_rx_null_gen' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_axi_basic_rx_null_gen.v:71]
  477. INFO: [Synth 8-226] default block is never used [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_axi_basic_rx_null_gen.v:252]
  478. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_axi_basic_rx_null_gen' (3#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_axi_basic_rx_null_gen.v:71]
  479. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_axi_basic_rx' (4#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_axi_basic_rx.v:70]
  480. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_axi_basic_tx' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_axi_basic_tx.v:70]
  481. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_axi_basic_tx_thrtl_ctl' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_axi_basic_tx_thrtl_ctl.v:71]
  482. INFO: [Synth 8-226] default block is never used [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_axi_basic_tx_thrtl_ctl.v:572]
  483. WARNING: [Synth 8-6014] Unused sequential element trn_rdllp_src_rdy_d_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_axi_basic_tx_thrtl_ctl.v:420]
  484. WARNING: [Synth 8-6014] Unused sequential element reg_tlast_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_axi_basic_tx_thrtl_ctl.v:654]
  485. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_axi_basic_tx_thrtl_ctl' (5#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_axi_basic_tx_thrtl_ctl.v:71]
  486. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_axi_basic_tx_pipeline' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_axi_basic_tx_pipeline.v:71]
  487. WARNING: [Synth 8-6014] Unused sequential element flush_axi_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_axi_basic_tx_pipeline.v:527]
  488. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_axi_basic_tx_pipeline' (6#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_axi_basic_tx_pipeline.v:71]
  489. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_axi_basic_tx' (7#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_axi_basic_tx.v:70]
  490. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_axi_basic_top' (8#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_axi_basic_top.v:68]
  491. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_pcie_7x' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pcie_7x.v:63]
  492. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_pcie_bram_top_7x' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pcie_bram_top_7x.v:72]
  493. WARNING: [Synth 8-639] system function call 'time' not supported [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pcie_bram_top_7x.v:138]
  494. INFO: [Synth 8-251] [1'b0] ROWS_TX 1 COLS_TX 4 [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pcie_bram_top_7x.v:138]
  495. WARNING: [Synth 8-639] system function call 'time' not supported [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pcie_bram_top_7x.v:139]
  496. INFO: [Synth 8-251] [1'b0] ROWS_RX 1 COLS_RX 4 [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pcie_bram_top_7x.v:139]
  497. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_pcie_brams_7x' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pcie_brams_7x.v:65]
  498. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_pcie_bram_7x' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pcie_bram_7x.v:63]
  499. INFO: [Synth 8-6157] synthesizing module 'xil_internal_svlib_BRAM_TDP_MACRO' [/home/mikek/Documents/Xilinx_FPGA/tools/Vivado/2021.2/data/verilog/src/unimacro/BRAM_TDP_MACRO.v:30]
  500. INFO: [Synth 8-6157] synthesizing module 'RAMB36E1' [/home/mikek/Documents/Xilinx_FPGA/tools/Vivado/2021.2/scripts/rt/data/unisim_comp.v:103901]
  501. INFO: [Synth 8-6155] done synthesizing module 'RAMB36E1' (9#1) [/home/mikek/Documents/Xilinx_FPGA/tools/Vivado/2021.2/scripts/rt/data/unisim_comp.v:103901]
  502. INFO: [Synth 8-6155] done synthesizing module 'xil_internal_svlib_BRAM_TDP_MACRO' (10#1) [/home/mikek/Documents/Xilinx_FPGA/tools/Vivado/2021.2/data/verilog/src/unimacro/BRAM_TDP_MACRO.v:30]
  503. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_pcie_bram_7x' (11#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pcie_bram_7x.v:63]
  504. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_pcie_brams_7x' (12#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pcie_brams_7x.v:65]
  505. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_pcie_bram_top_7x' (13#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pcie_bram_top_7x.v:72]
  506. INFO: [Synth 8-6157] synthesizing module 'PCIE_2_1' [/home/mikek/Documents/Xilinx_FPGA/tools/Vivado/2021.2/scripts/rt/data/unisim_comp.v:84723]
  507. INFO: [Synth 8-6155] done synthesizing module 'PCIE_2_1' (14#1) [/home/mikek/Documents/Xilinx_FPGA/tools/Vivado/2021.2/scripts/rt/data/unisim_comp.v:84723]
  508. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_pcie_7x' (15#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pcie_7x.v:63]
  509. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_pcie_pipe_pipeline' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pcie_pipe_pipeline.v:63]
  510. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_pcie_pipe_lane' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pcie_pipe_lane.v:63]
  511. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_pcie_pipe_lane' (16#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pcie_pipe_lane.v:63]
  512. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_pcie_pipe_misc' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pcie_pipe_misc.v:63]
  513. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_pcie_pipe_misc' (17#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pcie_pipe_misc.v:63]
  514. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_pcie_pipe_pipeline' (18#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pcie_pipe_pipeline.v:63]
  515. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_pcie_top' (19#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pcie_top.v:62]
  516. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_gt_top' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_gt_top.v:62]
  517. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_gt_rx_valid_filter_7x' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_gt_rx_valid_filter_7x.v:62]
  518. INFO: [Synth 8-155] case statement is not full and has no default [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_gt_rx_valid_filter_7x.v:190]
  519. WARNING: [Synth 8-6014] Unused sequential element reg_eios_detected_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_gt_rx_valid_filter_7x.v:134]
  520. WARNING: [Synth 8-6014] Unused sequential element gt_rx_is_skp0_q_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_gt_rx_valid_filter_7x.v:143]
  521. WARNING: [Synth 8-6014] Unused sequential element gt_rx_is_skp1_q_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_gt_rx_valid_filter_7x.v:144]
  522. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_gt_rx_valid_filter_7x' (20#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_gt_rx_valid_filter_7x.v:62]
  523. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_pipe_wrapper' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pipe_wrapper.v:156]
  524. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_gtp_pipe_reset' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_gtp_pipe_reset.v:67]
  525. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_gtp_pipe_reset' (21#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_gtp_pipe_reset.v:67]
  526. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_qpll_reset' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_qpll_reset.v:66]
  527. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_qpll_reset' (22#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_qpll_reset.v:66]
  528. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_gtp_pipe_rate' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_gtp_pipe_rate.v:67]
  529. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_gtp_pipe_rate' (23#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_gtp_pipe_rate.v:67]
  530. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_gtp_pipe_drp' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_gtp_pipe_drp.v:67]
  531. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_gtp_pipe_drp' (24#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_gtp_pipe_drp.v:67]
  532. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_pipe_eq' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pipe_eq.v:67]
  533. INFO: [Synth 8-226] default block is never used [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pipe_eq.v:401]
  534. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_rxeq_scan' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_rxeq_scan.v:66]
  535. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_rxeq_scan' (25#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_rxeq_scan.v:66]
  536. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_pipe_eq' (26#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pipe_eq.v:67]
  537. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_gt_common' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_gt_common.v:56]
  538. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_qpll_drp' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_qpll_drp.v:67]
  539. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_qpll_drp' (27#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_qpll_drp.v:67]
  540. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_qpll_wrapper' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_qpll_wrapper.v:67]
  541. INFO: [Synth 8-6157] synthesizing module 'GTPE2_COMMON' [/home/mikek/Documents/Xilinx_FPGA/tools/Vivado/2021.2/scripts/rt/data/unisim_comp.v:36468]
  542. INFO: [Synth 8-6155] done synthesizing module 'GTPE2_COMMON' (28#1) [/home/mikek/Documents/Xilinx_FPGA/tools/Vivado/2021.2/scripts/rt/data/unisim_comp.v:36468]
  543. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_gtp_cpllpd_ovrd' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_gtp_cpllpd_ovrd.v:54]
  544. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_gtp_cpllpd_ovrd' (29#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_gtp_cpllpd_ovrd.v:54]
  545. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_qpll_wrapper' (30#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_qpll_wrapper.v:67]
  546. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_gt_common' (31#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_gt_common.v:56]
  547. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_pipe_user' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pipe_user.v:67]
  548. INFO: [Synth 8-226] default block is never used [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pipe_user.v:353]
  549. WARNING: [Synth 8-6014] Unused sequential element gen3_rdy_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pipe_user.v:561]
  550. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_pipe_user' (32#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pipe_user.v:67]
  551. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_pipe_sync' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pipe_sync.v:71]
  552. WARNING: [Synth 8-6014] Unused sequential element rxsync_fsm_disable.rxsync_done_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pipe_sync.v:612]
  553. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_pipe_sync' (33#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pipe_sync.v:71]
  554. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_gt_wrapper' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_gt_wrapper.v:67]
  555. INFO: [Synth 8-6157] synthesizing module 'GTPE2_CHANNEL' [/home/mikek/Documents/Xilinx_FPGA/tools/Vivado/2021.2/scripts/rt/data/unisim_comp.v:35766]
  556. INFO: [Synth 8-6155] done synthesizing module 'GTPE2_CHANNEL' (34#1) [/home/mikek/Documents/Xilinx_FPGA/tools/Vivado/2021.2/scripts/rt/data/unisim_comp.v:35766]
  557. INFO: [Synth 8-6157] synthesizing module 'pcie_s7_gtx_cpllpd_ovrd' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_gtx_cpllpd_ovrd.v:54]
  558. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_gtx_cpllpd_ovrd' (35#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_gtx_cpllpd_ovrd.v:54]
  559. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_gt_wrapper' (36#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_gt_wrapper.v:67]
  560. INFO: [Synth 8-6157] synthesizing module 'BUFG' [/home/mikek/Documents/Xilinx_FPGA/tools/Vivado/2021.2/scripts/rt/data/unisim_comp.v:1083]
  561. INFO: [Synth 8-6155] done synthesizing module 'BUFG' (37#1) [/home/mikek/Documents/Xilinx_FPGA/tools/Vivado/2021.2/scripts/rt/data/unisim_comp.v:1083]
  562. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_pipe_wrapper' (38#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pipe_wrapper.v:156]
  563. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_gt_top' (39#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_gt_top.v:62]
  564. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_core_top' (40#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_core_top.v:65]
  565. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7_pcie2_top' (41#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7_pcie2_top.v:59]
  566. WARNING: [Synth 8-7071] port 'pipe_debug_0' of module 'pcie_s7_pcie2_top' is unconnected for instance 'inst' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/synth/pcie_s7.v:815]
  567. WARNING: [Synth 8-7023] instance 'inst' of module 'pcie_s7_pcie2_top' has 290 connections declared, but only 289 given [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/synth/pcie_s7.v:815]
  568. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7' (42#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/synth/pcie_s7.v:66]
  569. WARNING: [Synth 8-7129] Port GT_RXDISPERR[7] in module pcie_s7_gt_wrapper is either unconnected or has no load
  570. WARNING: [Synth 8-7129] Port GT_RXDISPERR[6] in module pcie_s7_gt_wrapper is either unconnected or has no load
  571. WARNING: [Synth 8-7129] Port GT_RXDISPERR[5] in module pcie_s7_gt_wrapper is either unconnected or has no load
  572. WARNING: [Synth 8-7129] Port GT_RXDISPERR[4] in module pcie_s7_gt_wrapper is either unconnected or has no load
  573. WARNING: [Synth 8-7129] Port GT_RXNOTINTABLE[7] in module pcie_s7_gt_wrapper is either unconnected or has no load
  574. WARNING: [Synth 8-7129] Port GT_RXNOTINTABLE[6] in module pcie_s7_gt_wrapper is either unconnected or has no load
  575. WARNING: [Synth 8-7129] Port GT_RXNOTINTABLE[5] in module pcie_s7_gt_wrapper is either unconnected or has no load
  576. WARNING: [Synth 8-7129] Port GT_RXNOTINTABLE[4] in module pcie_s7_gt_wrapper is either unconnected or has no load
  577. WARNING: [Synth 8-7129] Port GT_RXCHBONDO[4] in module pcie_s7_gt_wrapper is either unconnected or has no load
  578. WARNING: [Synth 8-7129] Port GT_GEN3 in module pcie_s7_gt_wrapper is either unconnected or has no load
  579. WARNING: [Synth 8-7129] Port GT_RX_CONVERGE in module pcie_s7_gt_wrapper is either unconnected or has no load
  580. WARNING: [Synth 8-7129] Port GT_GTREFCLK0 in module pcie_s7_gt_wrapper is either unconnected or has no load
  581. WARNING: [Synth 8-7129] Port GT_CPLLPD in module pcie_s7_gt_wrapper is either unconnected or has no load
  582. WARNING: [Synth 8-7129] Port GT_CPLLRESET in module pcie_s7_gt_wrapper is either unconnected or has no load
  583. WARNING: [Synth 8-7129] Port GT_RXDFELPMRESET in module pcie_s7_gt_wrapper is either unconnected or has no load
  584. WARNING: [Synth 8-7129] Port GT_RXCHBONDI[4] in module pcie_s7_gt_wrapper is either unconnected or has no load
  585. WARNING: [Synth 8-7129] Port INT_QPLLLOCK_OUT[1] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  586. WARNING: [Synth 8-7129] Port INT_QPLLOUTCLK_OUT[1] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  587. WARNING: [Synth 8-7129] Port INT_QPLLOUTREFCLK_OUT[1] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  588. WARNING: [Synth 8-7129] Port QPLL_QPLLRESET[1] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  589. WARNING: [Synth 8-7129] Port PIPE_MMCM_RST_N in module pcie_s7_pipe_wrapper is either unconnected or has no load
  590. WARNING: [Synth 8-7129] Port INT_PCLK_SEL_SLAVE[1] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  591. WARNING: [Synth 8-7129] Port INT_PCLK_SEL_SLAVE[0] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  592. WARNING: [Synth 8-7129] Port PIPE_RXOUTCLK_IN[1] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  593. WARNING: [Synth 8-7129] Port PIPE_RXOUTCLK_IN[0] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  594. WARNING: [Synth 8-7129] Port QPLL_DRP_CRSCODE[11] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  595. WARNING: [Synth 8-7129] Port QPLL_DRP_CRSCODE[10] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  596. WARNING: [Synth 8-7129] Port QPLL_DRP_CRSCODE[9] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  597. WARNING: [Synth 8-7129] Port QPLL_DRP_CRSCODE[8] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  598. WARNING: [Synth 8-7129] Port QPLL_DRP_CRSCODE[7] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  599. WARNING: [Synth 8-7129] Port QPLL_DRP_CRSCODE[6] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  600. WARNING: [Synth 8-7129] Port QPLL_DRP_CRSCODE[5] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  601. WARNING: [Synth 8-7129] Port QPLL_DRP_CRSCODE[4] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  602. WARNING: [Synth 8-7129] Port QPLL_DRP_CRSCODE[3] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  603. WARNING: [Synth 8-7129] Port QPLL_DRP_CRSCODE[2] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  604. WARNING: [Synth 8-7129] Port QPLL_DRP_CRSCODE[1] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  605. WARNING: [Synth 8-7129] Port QPLL_DRP_CRSCODE[0] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  606. WARNING: [Synth 8-7129] Port QPLL_DRP_FSM[17] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  607. WARNING: [Synth 8-7129] Port QPLL_DRP_FSM[16] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  608. WARNING: [Synth 8-7129] Port QPLL_DRP_FSM[15] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  609. WARNING: [Synth 8-7129] Port QPLL_DRP_FSM[14] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  610. WARNING: [Synth 8-7129] Port QPLL_DRP_FSM[13] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  611. WARNING: [Synth 8-7129] Port QPLL_DRP_FSM[12] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  612. WARNING: [Synth 8-7129] Port QPLL_DRP_FSM[11] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  613. WARNING: [Synth 8-7129] Port QPLL_DRP_FSM[10] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  614. WARNING: [Synth 8-7129] Port QPLL_DRP_FSM[9] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  615. WARNING: [Synth 8-7129] Port QPLL_DRP_FSM[8] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  616. WARNING: [Synth 8-7129] Port QPLL_DRP_FSM[7] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  617. WARNING: [Synth 8-7129] Port QPLL_DRP_FSM[6] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  618. WARNING: [Synth 8-7129] Port QPLL_DRP_FSM[5] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  619. WARNING: [Synth 8-7129] Port QPLL_DRP_FSM[4] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  620. WARNING: [Synth 8-7129] Port QPLL_DRP_FSM[3] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  621. WARNING: [Synth 8-7129] Port QPLL_DRP_FSM[2] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  622. WARNING: [Synth 8-7129] Port QPLL_DRP_FSM[1] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  623. WARNING: [Synth 8-7129] Port QPLL_DRP_FSM[0] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  624. WARNING: [Synth 8-7129] Port QPLL_DRP_DONE[1] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  625. WARNING: [Synth 8-7129] Port QPLL_DRP_DONE[0] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  626. WARNING: [Synth 8-7129] Port QPLL_DRP_RESET[1] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  627. WARNING: [Synth 8-7129] Port QPLL_DRP_RESET[0] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  628. WARNING: [Synth 8-7129] Port QPLL_QPLLLOCK[1] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  629. WARNING: [Synth 8-7129] Port QPLL_QPLLLOCK[0] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  630. WARNING: [Synth 8-7129] Port QPLL_QPLLOUTCLK[1] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  631. WARNING: [Synth 8-7129] Port QPLL_QPLLOUTCLK[0] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  632. WARNING: [Synth 8-7129] Port QPLL_QPLLOUTREFCLK[1] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  633. WARNING: [Synth 8-7129] Port QPLL_QPLLOUTREFCLK[0] in module pcie_s7_pipe_wrapper is either unconnected or has no load
  634. WARNING: [Synth 8-7129] Port PIPE_JTAG_EN in module pcie_s7_pipe_wrapper is either unconnected or has no load
  635. WARNING: [Synth 8-7129] Port PLM_IN_RS in module pcie_s7_gt_rx_valid_filter_7x is either unconnected or has no load
  636. WARNING: [Synth 8-7129] Port pipe_tx_reset in module pcie_s7_gt_top is either unconnected or has no load
  637. WARNING: [Synth 8-7129] Port pipe_rx2_polarity in module pcie_s7_gt_top is either unconnected or has no load
  638. WARNING: [Synth 8-7129] Port pipe_tx2_compliance in module pcie_s7_gt_top is either unconnected or has no load
  639. WARNING: [Synth 8-7129] Port pipe_tx2_char_is_k[1] in module pcie_s7_gt_top is either unconnected or has no load
  640. WARNING: [Synth 8-7129] Port pipe_tx2_char_is_k[0] in module pcie_s7_gt_top is either unconnected or has no load
  641. WARNING: [Synth 8-7129] Port pipe_tx2_data[15] in module pcie_s7_gt_top is either unconnected or has no load
  642. WARNING: [Synth 8-7129] Port pipe_tx2_data[14] in module pcie_s7_gt_top is either unconnected or has no load
  643. WARNING: [Synth 8-7129] Port pipe_tx2_data[13] in module pcie_s7_gt_top is either unconnected or has no load
  644. WARNING: [Synth 8-7129] Port pipe_tx2_data[12] in module pcie_s7_gt_top is either unconnected or has no load
  645. WARNING: [Synth 8-7129] Port pipe_tx2_data[11] in module pcie_s7_gt_top is either unconnected or has no load
  646. WARNING: [Synth 8-7129] Port pipe_tx2_data[10] in module pcie_s7_gt_top is either unconnected or has no load
  647. WARNING: [Synth 8-7129] Port pipe_tx2_data[9] in module pcie_s7_gt_top is either unconnected or has no load
  648. WARNING: [Synth 8-7129] Port pipe_tx2_data[8] in module pcie_s7_gt_top is either unconnected or has no load
  649. WARNING: [Synth 8-7129] Port pipe_tx2_data[7] in module pcie_s7_gt_top is either unconnected or has no load
  650. WARNING: [Synth 8-7129] Port pipe_tx2_data[6] in module pcie_s7_gt_top is either unconnected or has no load
  651. WARNING: [Synth 8-7129] Port pipe_tx2_data[5] in module pcie_s7_gt_top is either unconnected or has no load
  652. WARNING: [Synth 8-7129] Port pipe_tx2_data[4] in module pcie_s7_gt_top is either unconnected or has no load
  653. WARNING: [Synth 8-7129] Port pipe_tx2_data[3] in module pcie_s7_gt_top is either unconnected or has no load
  654. WARNING: [Synth 8-7129] Port pipe_tx2_data[2] in module pcie_s7_gt_top is either unconnected or has no load
  655. WARNING: [Synth 8-7129] Port pipe_tx2_data[1] in module pcie_s7_gt_top is either unconnected or has no load
  656. WARNING: [Synth 8-7129] Port pipe_tx2_data[0] in module pcie_s7_gt_top is either unconnected or has no load
  657. WARNING: [Synth 8-7129] Port pipe_tx2_elec_idle in module pcie_s7_gt_top is either unconnected or has no load
  658. WARNING: [Synth 8-7129] Port pipe_tx2_powerdown[1] in module pcie_s7_gt_top is either unconnected or has no load
  659. WARNING: [Synth 8-7129] Port pipe_tx2_powerdown[0] in module pcie_s7_gt_top is either unconnected or has no load
  660. WARNING: [Synth 8-7129] Port pipe_rx3_polarity in module pcie_s7_gt_top is either unconnected or has no load
  661. WARNING: [Synth 8-7129] Port pipe_tx3_compliance in module pcie_s7_gt_top is either unconnected or has no load
  662. WARNING: [Synth 8-7129] Port pipe_tx3_char_is_k[1] in module pcie_s7_gt_top is either unconnected or has no load
  663. WARNING: [Synth 8-7129] Port pipe_tx3_char_is_k[0] in module pcie_s7_gt_top is either unconnected or has no load
  664. WARNING: [Synth 8-7129] Port pipe_tx3_data[15] in module pcie_s7_gt_top is either unconnected or has no load
  665. WARNING: [Synth 8-7129] Port pipe_tx3_data[14] in module pcie_s7_gt_top is either unconnected or has no load
  666. WARNING: [Synth 8-7129] Port pipe_tx3_data[13] in module pcie_s7_gt_top is either unconnected or has no load
  667. WARNING: [Synth 8-7129] Port pipe_tx3_data[12] in module pcie_s7_gt_top is either unconnected or has no load
  668. WARNING: [Synth 8-7129] Port pipe_tx3_data[11] in module pcie_s7_gt_top is either unconnected or has no load
  669. INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
  670. ---------------------------------------------------------------------------------
  671. Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2639.316 ; gain = 0.000 ; free physical = 2530 ; free virtual = 21376
  672. ---------------------------------------------------------------------------------
  673. ---------------------------------------------------------------------------------
  674. Start Handling Custom Attributes
  675. ---------------------------------------------------------------------------------
  676. ---------------------------------------------------------------------------------
  677. Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2639.316 ; gain = 0.000 ; free physical = 2535 ; free virtual = 21381
  678. ---------------------------------------------------------------------------------
  679. ---------------------------------------------------------------------------------
  680. Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2639.316 ; gain = 0.000 ; free physical = 2535 ; free virtual = 21381
  681. ---------------------------------------------------------------------------------
  682. Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2639.316 ; gain = 0.000 ; free physical = 2524 ; free virtual = 21370
  683. INFO: [Netlist 29-17] Analyzing 8 Unisim elements for replacement
  684. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
  685. INFO: [Project 1-570] Preparing netlist for logic optimization
  686.  
  687. Processing XDC Constraints
  688. Initializing timing engine
  689. Parsing XDC File [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/synth/pcie_s7_ooc.xdc] for cell 'inst'
  690. Finished Parsing XDC File [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/synth/pcie_s7_ooc.xdc] for cell 'inst'
  691. Parsing XDC File [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7-PCIE_X0Y0.xdc] for cell 'inst'
  692. Finished Parsing XDC File [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7-PCIE_X0Y0.xdc] for cell 'inst'
  693. INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7-PCIE_X0Y0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/pcie_s7_propImpl.xdc].
  694. Resolution: To avoid this warning, move constraints listed in [.Xil/pcie_s7_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
  695. INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/mikek/Documents/Xilinx_FPGA/tools/Vivado/2021.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/pcie_s7_propImpl.xdc].
  696. Resolution: To avoid this warning, move constraints listed in [.Xil/pcie_s7_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
  697. INFO: [Project 1-1714] 2 XPM XDC files have been applied to the design.
  698. Completed Processing XDC Constraints
  699.  
  700. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2703.129 ; gain = 0.000 ; free physical = 2426 ; free virtual = 21272
  701. INFO: [Project 1-111] Unisim Transformation Summary:
  702. No Unisim elements were transformed.
  703.  
  704. Constraint Validation Runtime : Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2703.129 ; gain = 0.000 ; free physical = 2425 ; free virtual = 21271
  705. ---------------------------------------------------------------------------------
  706. Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2703.129 ; gain = 63.812 ; free physical = 2511 ; free virtual = 21358
  707. ---------------------------------------------------------------------------------
  708. ---------------------------------------------------------------------------------
  709. Start Loading Part and Timing Information
  710. ---------------------------------------------------------------------------------
  711. Loading part: xc7a50tcpg236-2
  712. ---------------------------------------------------------------------------------
  713. Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2703.129 ; gain = 63.812 ; free physical = 2511 ; free virtual = 21358
  714. ---------------------------------------------------------------------------------
  715. ---------------------------------------------------------------------------------
  716. Start Applying 'set_property' XDC Constraints
  717. ---------------------------------------------------------------------------------
  718. Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file auto generated constraint).
  719. Applied set_property KEEP_HIERARCHY = SOFT for inst/inst/phy_lnk_up_cdc. (constraint file auto generated constraint).
  720. Applied set_property KEEP_HIERARCHY = SOFT for inst/inst/pl_received_hot_rst_cdc. (constraint file auto generated constraint).
  721. ---------------------------------------------------------------------------------
  722. Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2703.129 ; gain = 63.812 ; free physical = 2511 ; free virtual = 21358
  723. ---------------------------------------------------------------------------------
  724. INFO: [Synth 8-802] inferred FSM for state register 'reg_state_eios_det_reg' in module 'pcie_s7_gt_rx_valid_filter_7x'
  725. INFO: [Synth 8-802] inferred FSM for state register 'fsm_reg' in module 'pcie_s7_gtp_pipe_reset'
  726. INFO: [Synth 8-802] inferred FSM for state register 'fsm_reg' in module 'pcie_s7_qpll_reset'
  727. INFO: [Synth 8-802] inferred FSM for state register 'fsm_reg' in module 'pcie_s7_gtp_pipe_rate'
  728. INFO: [Synth 8-802] inferred FSM for state register 'fsm_reg' in module 'pcie_s7_rxeq_scan'
  729. INFO: [Synth 8-802] inferred FSM for state register 'fsm_tx_reg' in module 'pcie_s7_pipe_eq'
  730. INFO: [Synth 8-802] inferred FSM for state register 'fsm_rx_reg' in module 'pcie_s7_pipe_eq'
  731. INFO: [Synth 8-802] inferred FSM for state register 'fsm_reg' in module 'pcie_s7_qpll_drp'
  732. INFO: [Synth 8-802] inferred FSM for state register 'resetovrd.fsm_reg' in module 'pcie_s7_pipe_user'
  733. INFO: [Synth 8-802] inferred FSM for state register 'txsync_fsm.fsm_tx_reg' in module 'pcie_s7_pipe_sync'
  734. ---------------------------------------------------------------------------------------------------
  735. State | New Encoding | Previous Encoding
  736. ---------------------------------------------------------------------------------------------------
  737. *
  738. EIOS_DET_IDL | 00001 | 00001
  739. EIOS_DET_NO_STR0 | 00010 | 00010
  740. EIOS_DET_STR0 | 00100 | 00100
  741. EIOS_DET_STR1 | 01000 | 01000
  742. EIOS_DET_DONE | 10000 | 10000
  743. ---------------------------------------------------------------------------------------------------
  744. INFO: [Synth 8-3898] No Re-encoding of one hot register 'reg_state_eios_det_reg' in module 'pcie_s7_gt_rx_valid_filter_7x'
  745. ---------------------------------------------------------------------------------------------------
  746. State | New Encoding | Previous Encoding
  747. ---------------------------------------------------------------------------------------------------
  748. FSM_CFG_WAIT | 000000000000001 | 00001
  749. FSM_PLLRESET | 001000000000000 | 00010
  750. FSM_DRP_X16_START | 000001000000000 | 00011
  751. FSM_DRP_X16_DONE | 000010000000000 | 00100
  752. FSM_PLLLOCK | 000000100000000 | 00101
  753. FSM_GTRESET | 000000001000000 | 00110
  754. FSM_RXPMARESETDONE_1 | 000000000000100 | 00111
  755. FSM_RXPMARESETDONE_2 | 000000000001000 | 01000
  756. FSM_DRP_X20_START | 000000000010000 | 01001
  757. FSM_DRP_X20_DONE | 000000000100000 | 01010
  758. FSM_MMCM_LOCK | 100000000000000 | 01011
  759. FSM_RESETDONE | 010000000000000 | 01100
  760. FSM_TXSYNC_START | 000100000000000 | 01101
  761. FSM_TXSYNC_DONE | 000000010000000 | 01110
  762. FSM_IDLE | 000000000000010 | 00000
  763. ---------------------------------------------------------------------------------------------------
  764. INFO: [Synth 8-3354] encoded FSM with state register 'fsm_reg' using encoding 'one-hot' in module 'pcie_s7_gtp_pipe_reset'
  765. ---------------------------------------------------------------------------------------------------
  766. State | New Encoding | Previous Encoding
  767. ---------------------------------------------------------------------------------------------------
  768. FSM_WAIT_LOCK | 00000001 | 0010
  769. FSM_MMCM_LOCK | 00000010 | 0011
  770. FSM_DRP_START_NOM | 00000100 | 0100
  771. FSM_DRP_DONE_NOM | 00001000 | 0101
  772. FSM_QPLLLOCK | 00010000 | 0110
  773. FSM_QPLL_PDRESET | 00100000 | 1011
  774. FSM_QPLL_PD | 01000000 | 1100
  775. FSM_IDLE | 10000000 | 0001
  776. ---------------------------------------------------------------------------------------------------
  777. INFO: [Synth 8-3354] encoded FSM with state register 'fsm_reg' using encoding 'one-hot' in module 'pcie_s7_qpll_reset'
  778. ---------------------------------------------------------------------------------------------------
  779. State | New Encoding | Previous Encoding
  780. ---------------------------------------------------------------------------------------------------
  781. FSM_IDLE | 0000000010000 | 0000
  782. FSM_TXDATA_WAIT | 0000100000000 | 0001
  783. FSM_PCLK_SEL | 0000000001000 | 0010
  784. FSM_DRP_X16_START | 0000000000001 | 0011
  785. FSM_DRP_X16_DONE | 0000000000010 | 0100
  786. FSM_RATE_SEL | 0000000000100 | 0101
  787. FSM_RXPMARESETDONE | 1000000000000 | 0110
  788. FSM_DRP_X20_START | 0001000000000 | 0111
  789. FSM_DRP_X20_DONE | 0010000000000 | 1000
  790. FSM_RATE_DONE | 0100000000000 | 1001
  791. FSM_TXSYNC_START | 0000010000000 | 1010
  792. FSM_TXSYNC_DONE | 0000001000000 | 1011
  793. FSM_DONE | 0000000100000 | 1100
  794. ---------------------------------------------------------------------------------------------------
  795. INFO: [Synth 8-3354] encoded FSM with state register 'fsm_reg' using encoding 'one-hot' in module 'pcie_s7_gtp_pipe_rate'
  796. ---------------------------------------------------------------------------------------------------
  797. State | New Encoding | Previous Encoding
  798. ---------------------------------------------------------------------------------------------------
  799. iSTATE | 00001 | 0000
  800. *
  801. FSM_IDLE | 00010 | 0001
  802. FSM_PRESET | 00100 | 0010
  803. FSM_CONVERGE | 01000 | 0100
  804. FSM_NEW_TXCOEFF_REQ | 10000 | 1000
  805. ---------------------------------------------------------------------------------------------------
  806. INFO: [Synth 8-3354] encoded FSM with state register 'fsm_reg' using encoding 'one-hot' in module 'pcie_s7_rxeq_scan'
  807. ---------------------------------------------------------------------------------------------------
  808. State | New Encoding | Previous Encoding
  809. ---------------------------------------------------------------------------------------------------
  810. iSTATE | 000 | 000000
  811. *
  812. FSM_TXEQ_IDLE | 001 | 000001
  813. FSM_TXEQ_PRESET | 010 | 000010
  814. FSM_TXEQ_TXCOEFF | 011 | 000100
  815. FSM_TXEQ_REMAP | 100 | 001000
  816. FSM_TXEQ_QUERY | 101 | 010000
  817. FSM_TXEQ_DONE | 110 | 100000
  818. ---------------------------------------------------------------------------------------------------
  819. INFO: [Synth 8-3354] encoded FSM with state register 'fsm_tx_reg' using encoding 'sequential' in module 'pcie_s7_pipe_eq'
  820. ---------------------------------------------------------------------------------------------------
  821. State | New Encoding | Previous Encoding
  822. ---------------------------------------------------------------------------------------------------
  823. iSTATE | 0000001 | 000000
  824. *
  825. FSM_RXEQ_IDLE | 0000010 | 000001
  826. FSM_RXEQ_PRESET | 0000100 | 000010
  827. FSM_RXEQ_TXCOEFF | 0001000 | 000100
  828. FSM_RXEQ_LF | 0010000 | 001000
  829. FSM_RXEQ_NEW_TXCOEFF_REQ | 0100000 | 010000
  830. FSM_RXEQ_DONE | 1000000 | 100000
  831. ---------------------------------------------------------------------------------------------------
  832. INFO: [Synth 8-3354] encoded FSM with state register 'fsm_rx_reg' using encoding 'one-hot' in module 'pcie_s7_pipe_eq'
  833. ---------------------------------------------------------------------------------------------------
  834. State | New Encoding | Previous Encoding
  835. ---------------------------------------------------------------------------------------------------
  836. *
  837. FSM_IDLE | 000000001 | 000000001
  838. FSM_LOAD | 000000010 | 000000010
  839. FSM_READ | 000000100 | 000000100
  840. FSM_RRDY | 000001000 | 000001000
  841. FSM_WRITE | 000010000 | 000010000
  842. FSM_WRDY | 000100000 | 000100000
  843. FSM_DONE | 001000000 | 001000000
  844. FSM_QPLLRESET | 010000000 | 010000000
  845. FSM_QPLLLOCK | 100000000 | 100000000
  846. ---------------------------------------------------------------------------------------------------
  847. INFO: [Synth 8-3898] No Re-encoding of one hot register 'fsm_reg' in module 'pcie_s7_qpll_drp'
  848. ---------------------------------------------------------------------------------------------------
  849. State | New Encoding | Previous Encoding
  850. ---------------------------------------------------------------------------------------------------
  851. FSM_IDLE | 0010 | 00
  852. FSM_RESETOVRD | 1000 | 01
  853. FSM_RESET_INIT | 0100 | 10
  854. FSM_RESET | 0001 | 11
  855. ---------------------------------------------------------------------------------------------------
  856. INFO: [Synth 8-3354] encoded FSM with state register 'resetovrd.fsm_reg' using encoding 'one-hot' in module 'pcie_s7_pipe_user'
  857. ---------------------------------------------------------------------------------------------------
  858. State | New Encoding | Previous Encoding
  859. ---------------------------------------------------------------------------------------------------
  860. iSTATE | 0000001 | 000000
  861. *
  862. FSM_TXSYNC_IDLE | 0000010 | 000001
  863. FSM_MMCM_LOCK | 0000100 | 000010
  864. FSM_TXSYNC_START | 0001000 | 000100
  865. FSM_TXPHINITDONE | 0010000 | 001000
  866. FSM_TXSYNC_DONE1 | 0100000 | 010000
  867. FSM_TXSYNC_DONE2 | 1000000 | 100000
  868. ---------------------------------------------------------------------------------------------------
  869. INFO: [Synth 8-3354] encoded FSM with state register 'txsync_fsm.fsm_tx_reg' using encoding 'one-hot' in module 'pcie_s7_pipe_sync'
  870. ---------------------------------------------------------------------------------
  871. Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 2703.129 ; gain = 63.812 ; free physical = 2501 ; free virtual = 21349
  872. ---------------------------------------------------------------------------------
  873. ---------------------------------------------------------------------------------
  874. Start RTL Component Statistics
  875. ---------------------------------------------------------------------------------
  876. Detailed RTL Component Info :
  877. +---Adders :
  878. 2 Input 22 Bit Adders := 2
  879. 2 Input 12 Bit Adders := 1
  880. 2 Input 11 Bit Adders := 1
  881. 2 Input 8 Bit Adders := 2
  882. 2 Input 6 Bit Adders := 2
  883. 2 Input 5 Bit Adders := 2
  884. 2 Input 4 Bit Adders := 6
  885. 2 Input 3 Bit Adders := 4
  886. 2 Input 2 Bit Adders := 8
  887. 2 Input 1 Bit Adders := 3
  888. +---Registers :
  889. 128 Bit Registers := 3
  890. 96 Bit Registers := 3
  891. 64 Bit Registers := 3
  892. 22 Bit Registers := 3
  893. 19 Bit Registers := 2
  894. 18 Bit Registers := 16
  895. 16 Bit Registers := 15
  896. 12 Bit Registers := 1
  897. 9 Bit Registers := 2
  898. 8 Bit Registers := 8
  899. 7 Bit Registers := 3
  900. 6 Bit Registers := 27
  901. 5 Bit Registers := 3
  902. 4 Bit Registers := 23
  903. 3 Bit Registers := 25
  904. 2 Bit Registers := 52
  905. 1 Bit Registers := 349
  906. +---Muxes :
  907. 2 Input 64 Bit Muxes := 1
  908. 2 Input 22 Bit Muxes := 5
  909. 5 Input 22 Bit Muxes := 2
  910. 2 Input 19 Bit Muxes := 2
  911. 7 Input 19 Bit Muxes := 2
  912. 2 Input 18 Bit Muxes := 6
  913. 24 Input 18 Bit Muxes := 2
  914. 7 Input 18 Bit Muxes := 4
  915. 2 Input 16 Bit Muxes := 2
  916. 15 Input 15 Bit Muxes := 1
  917. 2 Input 15 Bit Muxes := 13
  918. 13 Input 13 Bit Muxes := 2
  919. 2 Input 13 Bit Muxes := 20
  920. 2 Input 12 Bit Muxes := 4
  921. 2 Input 10 Bit Muxes := 1
  922. 2 Input 9 Bit Muxes := 6
  923. 10 Input 9 Bit Muxes := 1
  924. 3 Input 9 Bit Muxes := 1
  925. 5 Input 8 Bit Muxes := 1
  926. 2 Input 8 Bit Muxes := 12
  927. 8 Input 8 Bit Muxes := 2
  928. 2 Input 7 Bit Muxes := 25
  929. 7 Input 7 Bit Muxes := 4
  930. 4 Input 7 Bit Muxes := 2
  931. 2 Input 6 Bit Muxes := 3
  932. 7 Input 6 Bit Muxes := 6
  933. 8 Input 6 Bit Muxes := 1
  934. 2 Input 5 Bit Muxes := 32
  935. 3 Input 5 Bit Muxes := 1
  936. 6 Input 5 Bit Muxes := 2
  937. 15 Input 5 Bit Muxes := 1
  938. 8 Input 5 Bit Muxes := 2
  939. 5 Input 5 Bit Muxes := 2
  940. 2 Input 4 Bit Muxes := 25
  941. 8 Input 4 Bit Muxes := 1
  942. 7 Input 4 Bit Muxes := 2
  943. 4 Input 4 Bit Muxes := 2
  944. 2 Input 3 Bit Muxes := 27
  945. 3 Input 3 Bit Muxes := 1
  946. 13 Input 3 Bit Muxes := 2
  947. 7 Input 3 Bit Muxes := 6
  948. 4 Input 3 Bit Muxes := 2
  949. 10 Input 3 Bit Muxes := 1
  950. 4 Input 2 Bit Muxes := 1
  951. 2 Input 2 Bit Muxes := 10
  952. 7 Input 2 Bit Muxes := 2
  953. 2 Input 1 Bit Muxes := 78
  954. 6 Input 1 Bit Muxes := 6
  955. 15 Input 1 Bit Muxes := 3
  956. 8 Input 1 Bit Muxes := 9
  957. 13 Input 1 Bit Muxes := 2
  958. 5 Input 1 Bit Muxes := 16
  959. 4 Input 1 Bit Muxes := 4
  960. 7 Input 1 Bit Muxes := 34
  961. 10 Input 1 Bit Muxes := 3
  962. ---------------------------------------------------------------------------------
  963. Finished RTL Component Statistics
  964. ---------------------------------------------------------------------------------
  965. ---------------------------------------------------------------------------------
  966. Start Part Resource Summary
  967. ---------------------------------------------------------------------------------
  968. Part Resources:
  969. DSPs: 120 (col length:60)
  970. BRAMs: 150 (col length: RAMB18 60 RAMB36 30)
  971. ---------------------------------------------------------------------------------
  972. Finished Part Resource Summary
  973. ---------------------------------------------------------------------------------
  974. ---------------------------------------------------------------------------------
  975. Start Cross Boundary and Area Optimization
  976. ---------------------------------------------------------------------------------
  977. WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
  978. INFO: [Synth 8-3332] Sequential element (inst/gt_top_i/pipe_wrapper_i/qpll_reset.qpll_reset_i/FSM_onehot_fsm_reg[7]) is unused and will be removed from module pcie_s7_pcie2_top.
  979. INFO: [Synth 8-3332] Sequential element (inst/gt_top_i/pipe_wrapper_i/qpll_reset.qpll_reset_i/FSM_onehot_fsm_reg[6]) is unused and will be removed from module pcie_s7_pcie2_top.
  980. INFO: [Synth 8-3332] Sequential element (inst/gt_top_i/pipe_wrapper_i/qpll_reset.qpll_reset_i/FSM_onehot_fsm_reg[5]) is unused and will be removed from module pcie_s7_pcie2_top.
  981. INFO: [Synth 8-3332] Sequential element (inst/gt_top_i/pipe_wrapper_i/qpll_reset.qpll_reset_i/FSM_onehot_fsm_reg[4]) is unused and will be removed from module pcie_s7_pcie2_top.
  982. INFO: [Synth 8-3332] Sequential element (inst/gt_top_i/pipe_wrapper_i/qpll_reset.qpll_reset_i/FSM_onehot_fsm_reg[3]) is unused and will be removed from module pcie_s7_pcie2_top.
  983. INFO: [Synth 8-3332] Sequential element (inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_eq.pipe_eq_i/rxeq_scan_i/FSM_onehot_fsm_reg[0]) is unused and will be removed from module pcie_s7_pcie2_top.
  984. INFO: [Synth 8-3332] Sequential element (inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_eq.pipe_eq_i/FSM_onehot_fsm_rx_reg[0]) is unused and will be removed from module pcie_s7_pcie2_top.
  985. INFO: [Synth 8-3332] Sequential element (inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_sync_i/FSM_onehot_txsync_fsm.fsm_tx_reg[0]) is unused and will be removed from module pcie_s7_pcie2_top.
  986. INFO: [Synth 8-3332] Sequential element (inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].pipe_eq.pipe_eq_i/rxeq_scan_i/FSM_onehot_fsm_reg[0]) is unused and will be removed from module pcie_s7_pcie2_top.
  987. INFO: [Synth 8-3332] Sequential element (inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].pipe_eq.pipe_eq_i/FSM_onehot_fsm_rx_reg[0]) is unused and will be removed from module pcie_s7_pcie2_top.
  988. INFO: [Synth 8-3332] Sequential element (inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].pipe_sync_i/FSM_onehot_txsync_fsm.fsm_tx_reg[0]) is unused and will be removed from module pcie_s7_pcie2_top.
  989. ---------------------------------------------------------------------------------
  990. Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2703.129 ; gain = 63.812 ; free physical = 2476 ; free virtual = 21332
  991. ---------------------------------------------------------------------------------
  992. ---------------------------------------------------------------------------------
  993. Start Applying XDC Timing Constraints
  994. ---------------------------------------------------------------------------------
  995. ---------------------------------------------------------------------------------
  996. Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 2703.129 ; gain = 63.812 ; free physical = 2266 ; free virtual = 21122
  997. ---------------------------------------------------------------------------------
  998. ---------------------------------------------------------------------------------
  999. Start Timing Optimization
  1000. ---------------------------------------------------------------------------------
  1001. ---------------------------------------------------------------------------------
  1002. Finished Timing Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2703.129 ; gain = 63.812 ; free physical = 2252 ; free virtual = 21108
  1003. ---------------------------------------------------------------------------------
  1004. ---------------------------------------------------------------------------------
  1005. Start Technology Mapping
  1006. ---------------------------------------------------------------------------------
  1007. ---------------------------------------------------------------------------------
  1008. Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2703.137 ; gain = 63.820 ; free physical = 2248 ; free virtual = 21104
  1009. ---------------------------------------------------------------------------------
  1010. ---------------------------------------------------------------------------------
  1011. Start IO Insertion
  1012. ---------------------------------------------------------------------------------
  1013. ---------------------------------------------------------------------------------
  1014. Start Flattening Before IO Insertion
  1015. ---------------------------------------------------------------------------------
  1016. ---------------------------------------------------------------------------------
  1017. Finished Flattening Before IO Insertion
  1018. ---------------------------------------------------------------------------------
  1019. ---------------------------------------------------------------------------------
  1020. Start Final Netlist Cleanup
  1021. ---------------------------------------------------------------------------------
  1022. ---------------------------------------------------------------------------------
  1023. Finished Final Netlist Cleanup
  1024. ---------------------------------------------------------------------------------
  1025. ---------------------------------------------------------------------------------
  1026. Finished IO Insertion : Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 2703.137 ; gain = 63.820 ; free physical = 2248 ; free virtual = 21103
  1027. ---------------------------------------------------------------------------------
  1028. ---------------------------------------------------------------------------------
  1029. Start Renaming Generated Instances
  1030. ---------------------------------------------------------------------------------
  1031. ---------------------------------------------------------------------------------
  1032. Finished Renaming Generated Instances : Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 2703.137 ; gain = 63.820 ; free physical = 2248 ; free virtual = 21103
  1033. ---------------------------------------------------------------------------------
  1034. ---------------------------------------------------------------------------------
  1035. Start Rebuilding User Hierarchy
  1036. ---------------------------------------------------------------------------------
  1037. ---------------------------------------------------------------------------------
  1038. Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 2703.137 ; gain = 63.820 ; free physical = 2247 ; free virtual = 21103
  1039. ---------------------------------------------------------------------------------
  1040. ---------------------------------------------------------------------------------
  1041. Start Renaming Generated Ports
  1042. ---------------------------------------------------------------------------------
  1043. ---------------------------------------------------------------------------------
  1044. Finished Renaming Generated Ports : Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 2703.137 ; gain = 63.820 ; free physical = 2247 ; free virtual = 21103
  1045. ---------------------------------------------------------------------------------
  1046. ---------------------------------------------------------------------------------
  1047. Start Handling Custom Attributes
  1048. ---------------------------------------------------------------------------------
  1049. ---------------------------------------------------------------------------------
  1050. Finished Handling Custom Attributes : Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 2703.137 ; gain = 63.820 ; free physical = 2247 ; free virtual = 21103
  1051. ---------------------------------------------------------------------------------
  1052. ---------------------------------------------------------------------------------
  1053. Start Renaming Generated Nets
  1054. ---------------------------------------------------------------------------------
  1055. ---------------------------------------------------------------------------------
  1056. Finished Renaming Generated Nets : Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 2703.137 ; gain = 63.820 ; free physical = 2247 ; free virtual = 21103
  1057. ---------------------------------------------------------------------------------
  1058. ---------------------------------------------------------------------------------
  1059. Start ROM, RAM, DSP, Shift Register and Retiming Reporting
  1060. ---------------------------------------------------------------------------------
  1061.  
  1062. Static Shift Register Report:
  1063. +------------------+---------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
  1064. |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E |
  1065. +------------------+---------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
  1066. |pcie_s7_pcie2_top | inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i/qpll_wrapper_i/cpllPDInst/cpllpd_wait_reg[95] | 96 | 1 | NO | NO | YES | 0 | 3 |
  1067. |pcie_s7_pcie2_top | inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i/qpll_wrapper_i/cpllPDInst/cpllreset_wait_reg[127] | 128 | 1 | NO | NO | YES | 0 | 4 |
  1068. |pcie_s7_pcie2_top | inst/ltssm_reg2_reg[5] | 3 | 6 | NO | NO | YES | 6 | 0 |
  1069. +------------------+---------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
  1070.  
  1071. ---------------------------------------------------------------------------------
  1072. Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
  1073. ---------------------------------------------------------------------------------
  1074. ---------------------------------------------------------------------------------
  1075. Start Writing Synthesis Report
  1076. ---------------------------------------------------------------------------------
  1077.  
  1078. Report BlackBoxes:
  1079. +-+--------------+----------+
  1080. | |BlackBox name |Instances |
  1081. +-+--------------+----------+
  1082. +-+--------------+----------+
  1083.  
  1084. Report Cell Usage:
  1085. +------+--------------+------+
  1086. | |Cell |Count |
  1087. +------+--------------+------+
  1088. |1 |BUFG | 1|
  1089. |2 |CARRY4 | 18|
  1090. |3 |GTPE2_CHANNEL | 2|
  1091. |4 |GTPE2_COMMON | 1|
  1092. |5 |LUT1 | 54|
  1093. |6 |LUT2 | 165|
  1094. |7 |LUT3 | 193|
  1095. |8 |LUT4 | 142|
  1096. |9 |LUT5 | 221|
  1097. |10 |LUT6 | 206|
  1098. |11 |PCIE_2 | 1|
  1099. |12 |RAMB36E1 | 8|
  1100. |13 |SRL16E | 6|
  1101. |14 |SRLC32E | 7|
  1102. |15 |FDCE | 9|
  1103. |16 |FDPE | 2|
  1104. |17 |FDRE | 1598|
  1105. |18 |FDSE | 54|
  1106. +------+--------------+------+
  1107. ---------------------------------------------------------------------------------
  1108. Finished Writing Synthesis Report : Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 2703.137 ; gain = 63.820 ; free physical = 2247 ; free virtual = 21103
  1109. ---------------------------------------------------------------------------------
  1110. Synthesis finished with 0 errors, 0 critical warnings and 327 warnings.
  1111. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2703.137 ; gain = 0.008 ; free physical = 2297 ; free virtual = 21153
  1112. Synthesis Optimization Complete : Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 2703.145 ; gain = 63.820 ; free physical = 2297 ; free virtual = 21153
  1113. INFO: [Project 1-571] Translating synthesized netlist
  1114. Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2703.145 ; gain = 0.000 ; free physical = 2389 ; free virtual = 21244
  1115. INFO: [Netlist 29-17] Analyzing 26 Unisim elements for replacement
  1116. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
  1117. INFO: [Project 1-570] Preparing netlist for logic optimization
  1118. Parsing XDC File [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/synth/pcie_s7_ooc.xdc] for cell 'inst'
  1119. Finished Parsing XDC File [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/synth/pcie_s7_ooc.xdc] for cell 'inst'
  1120. Parsing XDC File [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7-PCIE_X0Y0.xdc] for cell 'inst'
  1121. Finished Parsing XDC File [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7-PCIE_X0Y0.xdc] for cell 'inst'
  1122. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  1123. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2756.934 ; gain = 0.000 ; free physical = 2318 ; free virtual = 21174
  1124. INFO: [Project 1-111] Unisim Transformation Summary:
  1125. No Unisim elements were transformed.
  1126.  
  1127. Synth Design complete, checksum: 9e37d154
  1128. INFO: [Common 17-83] Releasing license: Synthesis
  1129. 145 Infos, 113 Warnings, 0 Critical Warnings and 0 Errors encountered.
  1130. synth_design completed successfully
  1131. synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:30 . Memory (MB): peak = 2756.934 ; gain = 117.836 ; free physical = 2620 ; free virtual = 21475
  1132. INFO: [Coretcl 2-1174] Renamed 10 cell refs.
  1133. INFO: [Timing 38-35] Done setting XDC timing constraints.
  1134. INFO: [Timing 38-480] Writing timing data to binary archive.
  1135. Writing placer database...
  1136. Writing XDEF routing.
  1137. Writing XDEF routing logical nets.
  1138. Writing XDEF routing special nets.
  1139. Write XDEF Complete: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2947.734 ; gain = 2.969 ; free physical = 2323 ; free virtual = 21180
  1140. INFO: [Common 17-1381] The checkpoint '/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/pcie_s7.dcp' has been generated.
  1141. INFO: [Vivado 12-3441] generate_netlist_ip - operation complete
  1142. synth_ip: Time (s): cpu = 00:00:39 ; elapsed = 00:00:36 . Memory (MB): peak = 2947.734 ; gain = 308.637 ; free physical = 2414 ; free virtual = 21264
  1143. # synth_design -directive default -top fairwaves_xtrx -part xc7a50tcpg236-2
  1144. Command: synth_design -directive default -top fairwaves_xtrx -part xc7a50tcpg236-2
  1145. Starting synth_design
  1146. Attempting to get a license for feature 'Synthesis' and/or device 'xc7a50t'
  1147. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a50t'
  1148. INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
  1149. ---------------------------------------------------------------------------------
  1150. Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2952.387 ; gain = 4.652 ; free physical = 1201 ; free virtual = 20051
  1151. ---------------------------------------------------------------------------------
  1152. INFO: [Synth 8-6157] synthesizing module 'fairwaves_xtrx' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:20]
  1153. INFO: [Synth 8-3876] $readmem data file 'mem.init' is read successfully [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9234]
  1154. INFO: [Synth 8-3876] $readmem data file 'mem_1.init' is read successfully [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9249]
  1155. INFO: [Synth 8-3876] $readmem data file 'mem_2.init' is read successfully [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9272]
  1156. INFO: [Synth 8-226] default block is never used [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:3821]
  1157. INFO: [Synth 8-155] case statement is not full and has no default [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:4255]
  1158. INFO: [Synth 8-155] case statement is not full and has no default [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:5877]
  1159. INFO: [Synth 8-155] case statement is not full and has no default [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:5906]
  1160. INFO: [Synth 8-155] case statement is not full and has no default [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:5931]
  1161. INFO: [Synth 8-155] case statement is not full and has no default [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:5985]
  1162. INFO: [Synth 8-155] case statement is not full and has no default [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:7460]
  1163. INFO: [Synth 8-155] case statement is not full and has no default [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:7480]
  1164. INFO: [Synth 8-155] case statement is not full and has no default [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8413]
  1165. INFO: [Synth 8-155] case statement is not full and has no default [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8458]
  1166. INFO: [Synth 8-155] case statement is not full and has no default [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8481]
  1167. INFO: [Synth 8-155] case statement is not full and has no default [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8531]
  1168. INFO: [Synth 8-155] case statement is not full and has no default [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8543]
  1169. INFO: [Synth 8-155] case statement is not full and has no default [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8584]
  1170. INFO: [Synth 8-155] case statement is not full and has no default [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8596]
  1171. INFO: [Synth 8-155] case statement is not full and has no default [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8728]
  1172. INFO: [Synth 8-155] case statement is not full and has no default [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8751]
  1173. INFO: [Synth 8-155] case statement is not full and has no default [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8780]
  1174. INFO: [Synth 8-155] case statement is not full and has no default [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8835]
  1175. INFO: [Synth 8-6157] synthesizing module 'IBUFDS_GTE2' [/home/mikek/Documents/Xilinx_FPGA/tools/Vivado/2021.2/scripts/rt/data/unisim_comp.v:55358]
  1176. INFO: [Synth 8-6155] done synthesizing module 'IBUFDS_GTE2' (1#1) [/home/mikek/Documents/Xilinx_FPGA/tools/Vivado/2021.2/scripts/rt/data/unisim_comp.v:55358]
  1177. WARNING: [Synth 8-7071] port 'ODIV2' of module 'IBUFDS_GTE2' is unconnected for instance 'IBUFDS_GTE2' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9344]
  1178. WARNING: [Synth 8-7023] instance 'IBUFDS_GTE2' of module 'IBUFDS_GTE2' has 5 connections declared, but only 4 given [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9344]
  1179. INFO: [Synth 8-6157] synthesizing module 'ICAPE2' [/home/mikek/Documents/Xilinx_FPGA/tools/Vivado/2021.2/scripts/rt/data/unisim_comp.v:57041]
  1180. Parameter ICAP_WIDTH bound to: X32 - type: string
  1181. INFO: [Synth 8-6155] done synthesizing module 'ICAPE2' (2#1) [/home/mikek/Documents/Xilinx_FPGA/tools/Vivado/2021.2/scripts/rt/data/unisim_comp.v:57041]
  1182. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9541]
  1183. INFO: [Synth 8-6157] synthesizing module 'STARTUPE2' [/home/mikek/Documents/Xilinx_FPGA/tools/Vivado/2021.2/scripts/rt/data/unisim_comp.v:106169]
  1184. INFO: [Synth 8-6155] done synthesizing module 'STARTUPE2' (3#1) [/home/mikek/Documents/Xilinx_FPGA/tools/Vivado/2021.2/scripts/rt/data/unisim_comp.v:106169]
  1185. WARNING: [Synth 8-7071] port 'CFGCLK' of module 'STARTUPE2' is unconnected for instance 'STARTUPE2' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9541]
  1186. WARNING: [Synth 8-7071] port 'CFGMCLK' of module 'STARTUPE2' is unconnected for instance 'STARTUPE2' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9541]
  1187. WARNING: [Synth 8-7071] port 'EOS' of module 'STARTUPE2' is unconnected for instance 'STARTUPE2' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9541]
  1188. WARNING: [Synth 8-7071] port 'PREQ' of module 'STARTUPE2' is unconnected for instance 'STARTUPE2' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9541]
  1189. WARNING: [Synth 8-7023] instance 'STARTUPE2' of module 'STARTUPE2' has 13 connections declared, but only 9 given [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9541]
  1190. INFO: [Synth 8-6157] synthesizing module 'VexRiscv' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:46]
  1191. INFO: [Synth 8-6157] synthesizing module 'InstructionCache' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:6025]
  1192. WARNING: [Synth 8-6014] Unused sequential element decodeStage_mmuRsp_isIoAccess_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:6302]
  1193. WARNING: [Synth 8-6014] Unused sequential element decodeStage_mmuRsp_allowRead_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:6304]
  1194. WARNING: [Synth 8-6014] Unused sequential element decodeStage_mmuRsp_allowWrite_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:6305]
  1195. WARNING: [Synth 8-6014] Unused sequential element decodeStage_mmuRsp_bypassTranslation_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:6309]
  1196. INFO: [Synth 8-6155] done synthesizing module 'InstructionCache' (4#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:6025]
  1197. INFO: [Synth 8-6157] synthesizing module 'DataCache' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:5194]
  1198. WARNING: [Synth 8-6014] Unused sequential element tagsWriteLastCmd_valid_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:5899]
  1199. WARNING: [Synth 8-6014] Unused sequential element tagsWriteLastCmd_payload_way_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:5900]
  1200. WARNING: [Synth 8-6014] Unused sequential element tagsWriteLastCmd_payload_address_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:5901]
  1201. WARNING: [Synth 8-6014] Unused sequential element tagsWriteLastCmd_payload_data_valid_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:5902]
  1202. WARNING: [Synth 8-6014] Unused sequential element tagsWriteLastCmd_payload_data_error_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:5903]
  1203. WARNING: [Synth 8-6014] Unused sequential element tagsWriteLastCmd_payload_data_address_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:5904]
  1204. WARNING: [Synth 8-6014] Unused sequential element stageA_request_totalyConsistent_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:5908]
  1205. WARNING: [Synth 8-6014] Unused sequential element stageB_request_totalyConsistent_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:5922]
  1206. WARNING: [Synth 8-6014] Unused sequential element stageB_mmuRsp_allowExecute_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:5930]
  1207. WARNING: [Synth 8-6014] Unused sequential element stageB_mmuRsp_bypassTranslation_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:5933]
  1208. WARNING: [Synth 8-6014] Unused sequential element stageB_tagsReadRsp_0_valid_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:5936]
  1209. WARNING: [Synth 8-6014] Unused sequential element stageB_tagsReadRsp_0_address_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:5938]
  1210. WARNING: [Synth 8-3848] Net io_cpu_writeBack_exclusiveOk in module/entity DataCache does not have driver. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:5236]
  1211. INFO: [Synth 8-6155] done synthesizing module 'DataCache' (5#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:5194]
  1212. WARNING: [Synth 8-6014] Unused sequential element IBusCachedPlugin_fetchPc_correctionReg_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:2953]
  1213. WARNING: [Synth 8-6014] Unused sequential element IBusCachedPlugin_injector_nextPcCalc_valids_2_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:3061]
  1214. WARNING: [Synth 8-6014] Unused sequential element IBusCachedPlugin_injector_nextPcCalc_valids_3_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:3062]
  1215. WARNING: [Synth 8-6014] Unused sequential element IBusCachedPlugin_injector_nextPcCalc_valids_4_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:3063]
  1216. WARNING: [Synth 8-6014] Unused sequential element IBusCachedPlugin_rspCounter_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:4599]
  1217. WARNING: [Synth 8-6014] Unused sequential element DBusCachedPlugin_rspCounter_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:4603]
  1218. WARNING: [Synth 8-6014] Unused sequential element execute_CsrPlugin_wfiWake_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:4622]
  1219. WARNING: [Synth 8-6014] Unused sequential element dataCache_1_io_mem_cmd_rData_uncached_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:3257]
  1220. WARNING: [Synth 8-6014] Unused sequential element dataCache_1_io_mem_cmd_rData_last_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:3262]
  1221. WARNING: [Synth 8-6014] Unused sequential element dataCache_1_io_mem_cmd_s2mPipe_rData_uncached_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:3273]
  1222. WARNING: [Synth 8-6014] Unused sequential element dataCache_1_io_mem_cmd_s2mPipe_rData_last_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:3278]
  1223. WARNING: [Synth 8-6014] Unused sequential element CsrPlugin_mcycle_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:4885]
  1224. WARNING: [Synth 8-6014] Unused sequential element CsrPlugin_minstret_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:4887]
  1225. WARNING: [Synth 8-6014] Unused sequential element decode_to_execute_FORMAL_PC_NEXT_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:2492]
  1226. WARNING: [Synth 8-6014] Unused sequential element execute_to_memory_FORMAL_PC_NEXT_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:2491]
  1227. WARNING: [Synth 8-6014] Unused sequential element memory_to_writeBack_FORMAL_PC_NEXT_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:2490]
  1228. WARNING: [Synth 8-6014] Unused sequential element decode_to_execute_CSR_READ_OPCODE_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:2505]
  1229. WARNING: [Synth 8-6014] Unused sequential element CsrPlugin_mtvec_mode_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:5179]
  1230. WARNING: [Synth 8-3848] Net IBusCachedPlugin_cache_io_cpu_fetch_isRemoved in module/entity VexRiscv does not have driver. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:80]
  1231. WARNING: [Synth 8-3848] Net IBusCachedPlugin_mmuBus_rsp_bypassTranslation in module/entity VexRiscv does not have driver. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:643]
  1232. WARNING: [Synth 8-3848] Net DBusCachedPlugin_mmuBus_rsp_bypassTranslation in module/entity VexRiscv does not have driver. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:671]
  1233. WARNING: [Synth 8-3848] Net dataCache_1_io_cpu_writeBack_fence_SW in module/entity VexRiscv does not have driver. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:94]
  1234. WARNING: [Synth 8-3848] Net dataCache_1_io_cpu_writeBack_fence_SR in module/entity VexRiscv does not have driver. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:95]
  1235. WARNING: [Synth 8-3848] Net dataCache_1_io_cpu_writeBack_fence_SO in module/entity VexRiscv does not have driver. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:96]
  1236. WARNING: [Synth 8-3848] Net dataCache_1_io_cpu_writeBack_fence_SI in module/entity VexRiscv does not have driver. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:97]
  1237. WARNING: [Synth 8-3848] Net dataCache_1_io_cpu_writeBack_fence_PW in module/entity VexRiscv does not have driver. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:98]
  1238. WARNING: [Synth 8-3848] Net dataCache_1_io_cpu_writeBack_fence_PR in module/entity VexRiscv does not have driver. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:99]
  1239. WARNING: [Synth 8-3848] Net dataCache_1_io_cpu_writeBack_fence_PO in module/entity VexRiscv does not have driver. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:100]
  1240. WARNING: [Synth 8-3848] Net dataCache_1_io_cpu_writeBack_fence_PI in module/entity VexRiscv does not have driver. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:101]
  1241. WARNING: [Synth 8-3848] Net dataCache_1_io_cpu_writeBack_fence_FM in module/entity VexRiscv does not have driver. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:102]
  1242. WARNING: [Synth 8-3848] Net dBus_rsp_payload_last in module/entity VexRiscv does not have driver. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:656]
  1243. INFO: [Synth 8-6155] done synthesizing module 'VexRiscv' (6#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:46]
  1244. INFO: [Synth 8-6157] synthesizing module 'pcie_support' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litepcie/litepcie/phy/xilinx_s7_gen2/pcie_s7_support.v:61]
  1245. Parameter LINK_CAP_MAX_LINK_WIDTH bound to: 2'b10
  1246. Parameter C_DATA_WIDTH bound to: 7'b1000000
  1247. Parameter KEEP_WIDTH bound to: 4'b1000
  1248. Parameter PCIE_REFCLK_FREQ bound to: 1'b0
  1249. Parameter PCIE_USERCLK1_FREQ bound to: 2'b11
  1250. Parameter PCIE_USERCLK2_FREQ bound to: 2'b11
  1251. Parameter PCIE_GT_DEVICE bound to: GTP - type: string
  1252. INFO: [Synth 8-6157] synthesizing module 'pcie_pipe_clock' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litepcie/litepcie/phy/xilinx_s7_gen2/pcie_pipe_clock.v:67]
  1253. Parameter PCIE_ASYNC_EN bound to: FALSE - type: string
  1254. Parameter PCIE_TXBUF_EN bound to: FALSE - type: string
  1255. Parameter PCIE_LANE bound to: 2'b10
  1256. Parameter PCIE_REFCLK_FREQ bound to: 1'b0
  1257. Parameter PCIE_USERCLK1_FREQ bound to: 2'b11
  1258. Parameter PCIE_USERCLK2_FREQ bound to: 2'b11
  1259. Parameter PCIE_DEBUG_MODE bound to: 0 - type: integer
  1260. INFO: [Synth 8-6157] synthesizing module 'BUFG' [/home/mikek/Documents/Xilinx_FPGA/tools/Vivado/2021.2/scripts/rt/data/unisim_comp.v:1083]
  1261. INFO: [Synth 8-6155] done synthesizing module 'BUFG' (7#1) [/home/mikek/Documents/Xilinx_FPGA/tools/Vivado/2021.2/scripts/rt/data/unisim_comp.v:1083]
  1262. INFO: [Synth 8-6157] synthesizing module 'BUFGCTRL' [/home/mikek/Documents/Xilinx_FPGA/tools/Vivado/2021.2/scripts/rt/data/unisim_comp.v:1144]
  1263. INFO: [Synth 8-6155] done synthesizing module 'BUFGCTRL' (8#1) [/home/mikek/Documents/Xilinx_FPGA/tools/Vivado/2021.2/scripts/rt/data/unisim_comp.v:1144]
  1264. INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/home/mikek/Documents/Xilinx_FPGA/tools/Vivado/2021.2/scripts/rt/data/unisim_comp.v:63510]
  1265. Parameter BANDWIDTH bound to: OPTIMIZED - type: string
  1266. Parameter CLKFBOUT_MULT_F bound to: 10.000000 - type: double
  1267. Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double
  1268. Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string
  1269. Parameter CLKIN1_PERIOD bound to: 10.000000 - type: double
  1270. Parameter CLKOUT0_DIVIDE_F bound to: 8.000000 - type: double
  1271. Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double
  1272. Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double
  1273. Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string
  1274. Parameter CLKOUT1_DIVIDE bound to: 4 - type: integer
  1275. Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double
  1276. Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double
  1277. Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string
  1278. Parameter CLKOUT2_DIVIDE bound to: 8 - type: integer
  1279. Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: double
  1280. Parameter CLKOUT2_PHASE bound to: 0.000000 - type: double
  1281. Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string
  1282. Parameter CLKOUT3_DIVIDE bound to: 8 - type: integer
  1283. Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double
  1284. Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double
  1285. Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string
  1286. Parameter CLKOUT4_CASCADE bound to: FALSE - type: string
  1287. Parameter CLKOUT4_DIVIDE bound to: 20 - type: integer
  1288. Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double
  1289. Parameter CLKOUT4_PHASE bound to: 0.000000 - type: double
  1290. Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string
  1291. Parameter COMPENSATION bound to: ZHOLD - type: string
  1292. Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
  1293. Parameter REF_JITTER1 bound to: 0.010000 - type: double
  1294. Parameter STARTUP_WAIT bound to: FALSE - type: string
  1295. INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (9#1) [/home/mikek/Documents/Xilinx_FPGA/tools/Vivado/2021.2/scripts/rt/data/unisim_comp.v:63510]
  1296. WARNING: [Synth 8-6014] Unused sequential element pclk_sel_slave_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litepcie/litepcie/phy/xilinx_s7_gen2/pcie_pipe_clock.v:589]
  1297. INFO: [Synth 8-6155] done synthesizing module 'pcie_pipe_clock' (10#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litepcie/litepcie/phy/xilinx_s7_gen2/pcie_pipe_clock.v:67]
  1298. INFO: [Synth 8-6157] synthesizing module 'pcie_s7' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/.Xil/Vivado-82070-mike-AERO-17/realtime/pcie_s7_stub.v:6]
  1299. INFO: [Synth 8-6155] done synthesizing module 'pcie_s7' (11#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/.Xil/Vivado-82070-mike-AERO-17/realtime/pcie_s7_stub.v:6]
  1300. INFO: [Synth 8-6155] done synthesizing module 'pcie_support' (12#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litepcie/litepcie/phy/xilinx_s7_gen2/pcie_s7_support.v:61]
  1301. WARNING: [Synth 8-689] width (1) of port connection 'cfg_dcommand2' does not match port width (16) of module 'pcie_support' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9676]
  1302. WARNING: [Synth 8-689] width (1) of port connection 'cfg_dstatus' does not match port width (16) of module 'pcie_support' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9678]
  1303. WARNING: [Synth 8-689] width (1) of port connection 'cfg_interrupt_do' does not match port width (8) of module 'pcie_support' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9682]
  1304. WARNING: [Synth 8-689] width (1) of port connection 'cfg_interrupt_mmenable' does not match port width (3) of module 'pcie_support' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9683]
  1305. WARNING: [Synth 8-689] width (1) of port connection 'cfg_lcommand' does not match port width (16) of module 'pcie_support' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9688]
  1306. WARNING: [Synth 8-689] width (1) of port connection 'cfg_lstatus' does not match port width (16) of module 'pcie_support' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9689]
  1307. WARNING: [Synth 8-689] width (1) of port connection 'cfg_mgmt_do' does not match port width (32) of module 'pcie_support' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9690]
  1308. WARNING: [Synth 8-689] width (1) of port connection 'cfg_msg_data' does not match port width (16) of module 'pcie_support' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9692]
  1309. WARNING: [Synth 8-689] width (1) of port connection 'cfg_pcie_link_state' does not match port width (3) of module 'pcie_support' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9709]
  1310. WARNING: [Synth 8-689] width (1) of port connection 'cfg_pmcsr_powerstate' does not match port width (2) of module 'pcie_support' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9712]
  1311. WARNING: [Synth 8-689] width (1) of port connection 'cfg_status' does not match port width (16) of module 'pcie_support' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9719]
  1312. WARNING: [Synth 8-689] width (1) of port connection 'cfg_vc_tcvc_map' does not match port width (7) of module 'pcie_support' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9721]
  1313. WARNING: [Synth 8-689] width (1) of port connection 'fc_cpld' does not match port width (12) of module 'pcie_support' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9722]
  1314. WARNING: [Synth 8-689] width (1) of port connection 'fc_cplh' does not match port width (8) of module 'pcie_support' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9723]
  1315. WARNING: [Synth 8-689] width (1) of port connection 'fc_npd' does not match port width (12) of module 'pcie_support' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9724]
  1316. WARNING: [Synth 8-689] width (1) of port connection 'fc_nph' does not match port width (8) of module 'pcie_support' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9725]
  1317. WARNING: [Synth 8-689] width (1) of port connection 'fc_pd' does not match port width (12) of module 'pcie_support' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9726]
  1318. WARNING: [Synth 8-689] width (1) of port connection 'fc_ph' does not match port width (8) of module 'pcie_support' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9727]
  1319. WARNING: [Synth 8-689] width (32) of port connection 'm_axis_rx_tuser' does not match port width (22) of module 'pcie_support' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9731]
  1320. WARNING: [Synth 8-689] width (1) of port connection 'pcie_drp_do' does not match port width (16) of module 'pcie_support' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9735]
  1321. WARNING: [Synth 8-689] width (1) of port connection 'pipe_rxoutclk_out' does not match port width (2) of module 'pcie_support' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9741]
  1322. WARNING: [Synth 8-689] width (1) of port connection 'pl_initial_link_width' does not match port width (3) of module 'pcie_support' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9746]
  1323. WARNING: [Synth 8-689] width (1) of port connection 'pl_lane_reversal_mode' does not match port width (2) of module 'pcie_support' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9747]
  1324. WARNING: [Synth 8-689] width (1) of port connection 'pl_rx_pm_state' does not match port width (2) of module 'pcie_support' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9754]
  1325. WARNING: [Synth 8-689] width (1) of port connection 'pl_tx_pm_state' does not match port width (3) of module 'pcie_support' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9757]
  1326. WARNING: [Synth 8-689] width (1) of port connection 'tx_buf_av' does not match port width (6) of module 'pcie_support' [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9759]
  1327. WARNING: [Synth 8-6014] Unused sequential element s7pciephy_tx_datapath_pipe_ready_sink_d_ready_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:7512]
  1328. WARNING: [Synth 8-6014] Unused sequential element s7pciephy_tx_datapath_pipe_ready_sink_d_first_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:7513]
  1329. WARNING: [Synth 8-6014] Unused sequential element s7pciephy_rx_datapath_pipe_ready_sink_d_ready_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:7527]
  1330. WARNING: [Synth 8-6014] Unused sequential element s7pciephy_rx_datapath_pipe_valid_source_first_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:3426]
  1331. WARNING: [Synth 8-6014] Unused sequential element s7pciephy_rx_datapath_pipe_valid_source_payload_be_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:3429]
  1332. WARNING: [Synth 8-6014] Unused sequential element basesoc_depacketizer_header_extracter_be_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:7098]
  1333. WARNING: [Synth 8-6014] Unused sequential element basesoc_depacketizer_dispatcher_ongoing1_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:3853]
  1334. WARNING: [Synth 8-6014] Unused sequential element basesoc_packetizer_status0_first_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:7771]
  1335. WARNING: [Synth 8-6014] Unused sequential element basesoc_packetizer_status1_first_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:7779]
  1336. WARNING: [Synth 8-6014] Unused sequential element subfragments_status0_first_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8033]
  1337. WARNING: [Synth 8-6014] Unused sequential element subfragments_status1_first_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8041]
  1338. WARNING: [Synth 8-6014] Unused sequential element basesoc_writer_splitter_litepciedmadescriptorsplitter_desc_id_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8132]
  1339. WARNING: [Synth 8-6014] Unused sequential element basesoc_writer_splitter_bufferizeendpoints_source_first_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8136]
  1340. WARNING: [Synth 8-6014] Unused sequential element basesoc_writer_splitter_bufferizeendpoints_source_payload_user_id_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:5310]
  1341. WARNING: [Synth 8-6014] Unused sequential element basesoc_reader_splitter_bufferizeendpoints_source_first_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8256]
  1342. WARNING: [Synth 8-6014] Unused sequential element basesoc_reader_splitter_bufferizeendpoints_source_payload_last_disable_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8261]
  1343. WARNING: [Synth 8-6014] Unused sequential element basesoc_buffering_reader_fifo_produce_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8325]
  1344. WARNING: [Synth 8-6014] Unused sequential element basesoc_buffering_reader_fifo_consume_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:5814]
  1345. WARNING: [Synth 8-6014] Unused sequential element flash_pads_cs_n_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8373]
  1346. WARNING: [Synth 8-6014] Unused sequential element basesoc_basesoc_scratch_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8477]
  1347. WARNING: [Synth 8-6014] Unused sequential element basesoc_basesoc_bus_errors_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8478]
  1348. WARNING: [Synth 8-6014] Unused sequential element flash_status_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8512]
  1349. WARNING: [Synth 8-6014] Unused sequential element flash_mosi_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8519]
  1350. WARNING: [Synth 8-6014] Unused sequential element flash_miso_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8520]
  1351. WARNING: [Synth 8-6014] Unused sequential element flash_cs_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8524]
  1352. WARNING: [Synth 8-6014] Unused sequential element flash_loopback_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8528]
  1353. WARNING: [Synth 8-6014] Unused sequential element flash_cs_n_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8540]
  1354. WARNING: [Synth 8-6014] Unused sequential element icap_addr_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8564]
  1355. WARNING: [Synth 8-6014] Unused sequential element icap_data_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8571]
  1356. WARNING: [Synth 8-6014] Unused sequential element icap_write_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8575]
  1357. WARNING: [Synth 8-6014] Unused sequential element icap_done_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8576]
  1358. WARNING: [Synth 8-6014] Unused sequential element icap_read_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8580]
  1359. WARNING: [Synth 8-6014] Unused sequential element basesoc_writer_enable_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8665]
  1360. WARNING: [Synth 8-6014] Unused sequential element basesoc_writer_value_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8672]
  1361. WARNING: [Synth 8-6014] Unused sequential element basesoc_writer_loop_prog_n_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8680]
  1362. WARNING: [Synth 8-6014] Unused sequential element basesoc_writer_loop_status_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8681]
  1363. WARNING: [Synth 8-6014] Unused sequential element basesoc_writer_level_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8682]
  1364. WARNING: [Synth 8-6014] Unused sequential element basesoc_reader_enable_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8690]
  1365. WARNING: [Synth 8-6014] Unused sequential element basesoc_reader_value_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8697]
  1366. WARNING: [Synth 8-6014] Unused sequential element basesoc_reader_loop_prog_n_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8705]
  1367. WARNING: [Synth 8-6014] Unused sequential element basesoc_reader_loop_status_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8706]
  1368. WARNING: [Synth 8-6014] Unused sequential element basesoc_reader_level_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8707]
  1369. WARNING: [Synth 8-6014] Unused sequential element basesoc_loopback_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8715]
  1370. WARNING: [Synth 8-6014] Unused sequential element basesoc_buffering_reader_fifo_control_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8719]
  1371. WARNING: [Synth 8-6014] Unused sequential element basesoc_buffering_writer_fifo_control_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8724]
  1372. WARNING: [Synth 8-6014] Unused sequential element basesoc_msi_enable_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8743]
  1373. WARNING: [Synth 8-6014] Unused sequential element basesoc_msi_vector_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8748]
  1374. WARNING: [Synth 8-6014] Unused sequential element s7pciephy_link_status_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8772]
  1375. WARNING: [Synth 8-6014] Unused sequential element s7pciephy_msi_enable_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8773]
  1376. WARNING: [Synth 8-6014] Unused sequential element s7pciephy_msix_enable_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8774]
  1377. WARNING: [Synth 8-6014] Unused sequential element s7pciephy_bus_master_enable_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8775]
  1378. WARNING: [Synth 8-6014] Unused sequential element s7pciephy_max_request_size_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8776]
  1379. WARNING: [Synth 8-6014] Unused sequential element s7pciephy_max_payload_size_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8777]
  1380. WARNING: [Synth 8-6014] Unused sequential element basesoc_basesoc_load_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8810]
  1381. WARNING: [Synth 8-6014] Unused sequential element basesoc_basesoc_reload_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8814]
  1382. WARNING: [Synth 8-6014] Unused sequential element basesoc_basesoc_en_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8818]
  1383. WARNING: [Synth 8-6014] Unused sequential element basesoc_basesoc_value_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8823]
  1384. WARNING: [Synth 8-6014] Unused sequential element basesoc_basesoc_status_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8824]
  1385. WARNING: [Synth 8-6014] Unused sequential element basesoc_basesoc_enable_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8832]
  1386. WARNING: [Synth 8-6014] Unused sequential element basesoc_basesoc_uartcrossover_txfull_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8886]
  1387. WARNING: [Synth 8-6014] Unused sequential element basesoc_basesoc_uartcrossover_rxempty_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8887]
  1388. WARNING: [Synth 8-6014] Unused sequential element basesoc_basesoc_uartcrossover_status_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8888]
  1389. WARNING: [Synth 8-6014] Unused sequential element basesoc_basesoc_uartcrossover_enable_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8896]
  1390. WARNING: [Synth 8-6014] Unused sequential element basesoc_basesoc_uartcrossover_txempty_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8897]
  1391. WARNING: [Synth 8-6014] Unused sequential element basesoc_basesoc_uartcrossover_rxfull_re_reg was removed. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:8898]
  1392. INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
  1393. WARNING: [Synth 8-3936] Found unconnected internal register 'basesoc_packetizer_tlp_raw_payload_header_reg' and it is trimmed from '128' to '96' bits. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:3977]
  1394. WARNING: [Synth 8-3936] Found unconnected internal register 'basesoc_packetizer_tlp_raw_req_payload_header_reg' and it is trimmed from '128' to '96' bits. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:3898]
  1395. WARNING: [Synth 8-3936] Found unconnected internal register 'basesoc_packetizer_tlp_raw_cmp_payload_header_reg' and it is trimmed from '128' to '96' bits. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:3955]
  1396. WARNING: [Synth 8-3936] Found unconnected internal register 'storage_5_dat1_reg' and it is trimmed from '10' to '8' bits. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9405]
  1397. WARNING: [Synth 8-3936] Found unconnected internal register 'basesoc_packetizer_tlp_raw_payload_be_reg' and it is trimmed from '8' to '4' bits. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:3979]
  1398. INFO: [Synth 8-6155] done synthesizing module 'fairwaves_xtrx' (13#1) [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:20]
  1399. WARNING: [Synth 8-7129] Port CLK_CLK in module pcie_pipe_clock is either unconnected or has no load
  1400. WARNING: [Synth 8-7129] Port CLK_RXOUTCLK_IN[1] in module pcie_pipe_clock is either unconnected or has no load
  1401. WARNING: [Synth 8-7129] Port CLK_RXOUTCLK_IN[0] in module pcie_pipe_clock is either unconnected or has no load
  1402. WARNING: [Synth 8-7129] Port io_cpu_writeBack_exclusiveOk in module DataCache is either unconnected or has no load
  1403. WARNING: [Synth 8-7129] Port io_cpu_execute_address[31] in module DataCache is either unconnected or has no load
  1404. WARNING: [Synth 8-7129] Port io_cpu_execute_address[30] in module DataCache is either unconnected or has no load
  1405. WARNING: [Synth 8-7129] Port io_cpu_execute_address[29] in module DataCache is either unconnected or has no load
  1406. WARNING: [Synth 8-7129] Port io_cpu_execute_address[28] in module DataCache is either unconnected or has no load
  1407. WARNING: [Synth 8-7129] Port io_cpu_execute_address[27] in module DataCache is either unconnected or has no load
  1408. WARNING: [Synth 8-7129] Port io_cpu_execute_address[26] in module DataCache is either unconnected or has no load
  1409. WARNING: [Synth 8-7129] Port io_cpu_execute_address[25] in module DataCache is either unconnected or has no load
  1410. WARNING: [Synth 8-7129] Port io_cpu_execute_address[24] in module DataCache is either unconnected or has no load
  1411. WARNING: [Synth 8-7129] Port io_cpu_execute_address[23] in module DataCache is either unconnected or has no load
  1412. WARNING: [Synth 8-7129] Port io_cpu_execute_address[22] in module DataCache is either unconnected or has no load
  1413. WARNING: [Synth 8-7129] Port io_cpu_execute_address[21] in module DataCache is either unconnected or has no load
  1414. WARNING: [Synth 8-7129] Port io_cpu_execute_address[20] in module DataCache is either unconnected or has no load
  1415. WARNING: [Synth 8-7129] Port io_cpu_execute_address[19] in module DataCache is either unconnected or has no load
  1416. WARNING: [Synth 8-7129] Port io_cpu_execute_address[18] in module DataCache is either unconnected or has no load
  1417. WARNING: [Synth 8-7129] Port io_cpu_execute_address[17] in module DataCache is either unconnected or has no load
  1418. WARNING: [Synth 8-7129] Port io_cpu_execute_address[16] in module DataCache is either unconnected or has no load
  1419. WARNING: [Synth 8-7129] Port io_cpu_execute_address[15] in module DataCache is either unconnected or has no load
  1420. WARNING: [Synth 8-7129] Port io_cpu_execute_address[14] in module DataCache is either unconnected or has no load
  1421. WARNING: [Synth 8-7129] Port io_cpu_execute_address[13] in module DataCache is either unconnected or has no load
  1422. WARNING: [Synth 8-7129] Port io_cpu_execute_address[12] in module DataCache is either unconnected or has no load
  1423. WARNING: [Synth 8-7129] Port io_cpu_execute_args_totalyConsistent in module DataCache is either unconnected or has no load
  1424. WARNING: [Synth 8-7129] Port io_cpu_memory_address[31] in module DataCache is either unconnected or has no load
  1425. WARNING: [Synth 8-7129] Port io_cpu_memory_address[30] in module DataCache is either unconnected or has no load
  1426. WARNING: [Synth 8-7129] Port io_cpu_memory_address[29] in module DataCache is either unconnected or has no load
  1427. WARNING: [Synth 8-7129] Port io_cpu_memory_address[28] in module DataCache is either unconnected or has no load
  1428. WARNING: [Synth 8-7129] Port io_cpu_memory_address[27] in module DataCache is either unconnected or has no load
  1429. WARNING: [Synth 8-7129] Port io_cpu_memory_address[26] in module DataCache is either unconnected or has no load
  1430. WARNING: [Synth 8-7129] Port io_cpu_memory_address[25] in module DataCache is either unconnected or has no load
  1431. WARNING: [Synth 8-7129] Port io_cpu_memory_address[24] in module DataCache is either unconnected or has no load
  1432. WARNING: [Synth 8-7129] Port io_cpu_memory_address[23] in module DataCache is either unconnected or has no load
  1433. WARNING: [Synth 8-7129] Port io_cpu_memory_address[22] in module DataCache is either unconnected or has no load
  1434. WARNING: [Synth 8-7129] Port io_cpu_memory_address[21] in module DataCache is either unconnected or has no load
  1435. WARNING: [Synth 8-7129] Port io_cpu_memory_address[20] in module DataCache is either unconnected or has no load
  1436. WARNING: [Synth 8-7129] Port io_cpu_memory_address[19] in module DataCache is either unconnected or has no load
  1437. WARNING: [Synth 8-7129] Port io_cpu_memory_address[18] in module DataCache is either unconnected or has no load
  1438. WARNING: [Synth 8-7129] Port io_cpu_memory_address[17] in module DataCache is either unconnected or has no load
  1439. WARNING: [Synth 8-7129] Port io_cpu_memory_address[16] in module DataCache is either unconnected or has no load
  1440. WARNING: [Synth 8-7129] Port io_cpu_memory_address[15] in module DataCache is either unconnected or has no load
  1441. WARNING: [Synth 8-7129] Port io_cpu_memory_address[14] in module DataCache is either unconnected or has no load
  1442. WARNING: [Synth 8-7129] Port io_cpu_memory_address[13] in module DataCache is either unconnected or has no load
  1443. WARNING: [Synth 8-7129] Port io_cpu_memory_address[12] in module DataCache is either unconnected or has no load
  1444. WARNING: [Synth 8-7129] Port io_cpu_memory_mmuRsp_allowExecute in module DataCache is either unconnected or has no load
  1445. WARNING: [Synth 8-7129] Port io_cpu_memory_mmuRsp_bypassTranslation in module DataCache is either unconnected or has no load
  1446. WARNING: [Synth 8-7129] Port io_cpu_writeBack_isUser in module DataCache is either unconnected or has no load
  1447. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[31] in module DataCache is either unconnected or has no load
  1448. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[30] in module DataCache is either unconnected or has no load
  1449. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[29] in module DataCache is either unconnected or has no load
  1450. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[28] in module DataCache is either unconnected or has no load
  1451. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[27] in module DataCache is either unconnected or has no load
  1452. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[26] in module DataCache is either unconnected or has no load
  1453. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[25] in module DataCache is either unconnected or has no load
  1454. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[24] in module DataCache is either unconnected or has no load
  1455. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[23] in module DataCache is either unconnected or has no load
  1456. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[22] in module DataCache is either unconnected or has no load
  1457. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[21] in module DataCache is either unconnected or has no load
  1458. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[20] in module DataCache is either unconnected or has no load
  1459. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[19] in module DataCache is either unconnected or has no load
  1460. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[18] in module DataCache is either unconnected or has no load
  1461. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[17] in module DataCache is either unconnected or has no load
  1462. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[16] in module DataCache is either unconnected or has no load
  1463. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[15] in module DataCache is either unconnected or has no load
  1464. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[14] in module DataCache is either unconnected or has no load
  1465. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[13] in module DataCache is either unconnected or has no load
  1466. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[12] in module DataCache is either unconnected or has no load
  1467. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[11] in module DataCache is either unconnected or has no load
  1468. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[10] in module DataCache is either unconnected or has no load
  1469. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[9] in module DataCache is either unconnected or has no load
  1470. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[8] in module DataCache is either unconnected or has no load
  1471. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[7] in module DataCache is either unconnected or has no load
  1472. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[6] in module DataCache is either unconnected or has no load
  1473. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[5] in module DataCache is either unconnected or has no load
  1474. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[4] in module DataCache is either unconnected or has no load
  1475. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[3] in module DataCache is either unconnected or has no load
  1476. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[2] in module DataCache is either unconnected or has no load
  1477. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[1] in module DataCache is either unconnected or has no load
  1478. WARNING: [Synth 8-7129] Port io_cpu_writeBack_address[0] in module DataCache is either unconnected or has no load
  1479. WARNING: [Synth 8-7129] Port io_cpu_writeBack_fence_SW in module DataCache is either unconnected or has no load
  1480. WARNING: [Synth 8-7129] Port io_cpu_writeBack_fence_SR in module DataCache is either unconnected or has no load
  1481. WARNING: [Synth 8-7129] Port io_cpu_writeBack_fence_SO in module DataCache is either unconnected or has no load
  1482. WARNING: [Synth 8-7129] Port io_cpu_writeBack_fence_SI in module DataCache is either unconnected or has no load
  1483. WARNING: [Synth 8-7129] Port io_cpu_writeBack_fence_PW in module DataCache is either unconnected or has no load
  1484. WARNING: [Synth 8-7129] Port io_cpu_writeBack_fence_PR in module DataCache is either unconnected or has no load
  1485. WARNING: [Synth 8-7129] Port io_cpu_writeBack_fence_PO in module DataCache is either unconnected or has no load
  1486. WARNING: [Synth 8-7129] Port io_cpu_writeBack_fence_PI in module DataCache is either unconnected or has no load
  1487. WARNING: [Synth 8-7129] Port io_cpu_writeBack_fence_FM[3] in module DataCache is either unconnected or has no load
  1488. WARNING: [Synth 8-7129] Port io_cpu_writeBack_fence_FM[2] in module DataCache is either unconnected or has no load
  1489. WARNING: [Synth 8-7129] Port io_cpu_writeBack_fence_FM[1] in module DataCache is either unconnected or has no load
  1490. WARNING: [Synth 8-7129] Port io_cpu_writeBack_fence_FM[0] in module DataCache is either unconnected or has no load
  1491. WARNING: [Synth 8-7129] Port io_mem_rsp_payload_last in module DataCache is either unconnected or has no load
  1492. WARNING: [Synth 8-7129] Port io_cpu_prefetch_isValid in module InstructionCache is either unconnected or has no load
  1493. WARNING: [Synth 8-7129] Port io_cpu_prefetch_pc[31] in module InstructionCache is either unconnected or has no load
  1494. WARNING: [Synth 8-7129] Port io_cpu_prefetch_pc[30] in module InstructionCache is either unconnected or has no load
  1495. WARNING: [Synth 8-7129] Port io_cpu_prefetch_pc[29] in module InstructionCache is either unconnected or has no load
  1496. WARNING: [Synth 8-7129] Port io_cpu_prefetch_pc[28] in module InstructionCache is either unconnected or has no load
  1497. WARNING: [Synth 8-7129] Port io_cpu_prefetch_pc[27] in module InstructionCache is either unconnected or has no load
  1498. WARNING: [Synth 8-7129] Port io_cpu_prefetch_pc[26] in module InstructionCache is either unconnected or has no load
  1499. INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
  1500. ---------------------------------------------------------------------------------
  1501. Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3081.293 ; gain = 133.559 ; free physical = 2050 ; free virtual = 20901
  1502. ---------------------------------------------------------------------------------
  1503. ---------------------------------------------------------------------------------
  1504. Start Handling Custom Attributes
  1505. ---------------------------------------------------------------------------------
  1506. ---------------------------------------------------------------------------------
  1507. Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.137 ; gain = 148.402 ; free physical = 2070 ; free virtual = 20921
  1508. ---------------------------------------------------------------------------------
  1509. ---------------------------------------------------------------------------------
  1510. Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3096.137 ; gain = 148.402 ; free physical = 2070 ; free virtual = 20921
  1511. ---------------------------------------------------------------------------------
  1512. Netlist sorting complete. Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.10 . Memory (MB): peak = 3096.137 ; gain = 0.000 ; free physical = 2059 ; free virtual = 20909
  1513. WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'pcie_support/pipe_clock_i/pclk_i1_bufgctrl.pclk_i1' of type 'BUFGCTRL' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist.
  1514. INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement
  1515. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
  1516. INFO: [Project 1-570] Preparing netlist for logic optimization
  1517.  
  1518. Processing XDC Constraints
  1519. Initializing timing engine
  1520. Parsing XDC File [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/pcie_s7/pcie_s7_in_context.xdc] for cell 'pcie_support/pcie_i'
  1521. Finished Parsing XDC File [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/pcie_s7/pcie_s7_in_context.xdc] for cell 'pcie_support/pcie_i'
  1522. Parsing XDC File [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc]
  1523. INFO: [Timing 38-2] Deriving generated clocks [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc:76]
  1524. WARNING: [Vivado 12-3521] Clock specified in more than one group: pcie_support/pcie_i/user_clk_out [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc:76]
  1525. WARNING: [Vivado 12-180] No cells matched 'get_cells -hierarchical -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}'. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc:87]
  1526. WARNING: [Vivado 12-508] No pins matched 'get_pins -filter {REF_PIN_NAME == PRE} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]'. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc:87]
  1527. WARNING: [Vivado 12-180] No cells matched 'get_cells -hierarchical -filter {ars_ff1 == TRUE}'. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc:89]
  1528. WARNING: [Vivado 12-508] No pins matched 'get_pins -filter {REF_PIN_NAME == C} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE}]'. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc:89]
  1529. WARNING: [Vivado 12-180] No cells matched 'get_cells -hierarchical -filter {ars_ff2 == TRUE}'. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc:89]
  1530. WARNING: [Vivado 12-508] No pins matched 'get_pins -filter {REF_PIN_NAME == D} -of_objects [get_cells -hierarchical -filter {ars_ff2 == TRUE}]'. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc:89]
  1531. Finished Parsing XDC File [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc]
  1532. INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fairwaves_xtrx_propImpl.xdc].
  1533. Resolution: To avoid this warning, move constraints listed in [.Xil/fairwaves_xtrx_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
  1534. Completed Processing XDC Constraints
  1535.  
  1536. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3218.871 ; gain = 0.000 ; free physical = 1965 ; free virtual = 20816
  1537. INFO: [Project 1-111] Unisim Transformation Summary:
  1538. No Unisim elements were transformed.
  1539.  
  1540. Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3218.871 ; gain = 0.000 ; free physical = 1965 ; free virtual = 20816
  1541. ---------------------------------------------------------------------------------
  1542. Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 3218.871 ; gain = 271.137 ; free physical = 2057 ; free virtual = 20908
  1543. ---------------------------------------------------------------------------------
  1544. ---------------------------------------------------------------------------------
  1545. Start Loading Part and Timing Information
  1546. ---------------------------------------------------------------------------------
  1547. Loading part: xc7a50tcpg236-2
  1548. ---------------------------------------------------------------------------------
  1549. Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 3218.871 ; gain = 271.137 ; free physical = 2057 ; free virtual = 20908
  1550. ---------------------------------------------------------------------------------
  1551. ---------------------------------------------------------------------------------
  1552. Start Applying 'set_property' XDC Constraints
  1553. ---------------------------------------------------------------------------------
  1554. Applied set_property KEEP_HIERARCHY = SOFT for pcie_support/pcie_i. (constraint file auto generated constraint).
  1555. ---------------------------------------------------------------------------------
  1556. Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 3218.871 ; gain = 271.137 ; free physical = 2057 ; free virtual = 20908
  1557. ---------------------------------------------------------------------------------
  1558. WARNING: [Synth 8-3936] Found unconnected internal register 'memory_to_writeBack_INSTRUCTION_reg' and it is trimmed from '32' to '30' bits. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:2725]
  1559. WARNING: [Synth 8-3936] Found unconnected internal register 'execute_to_memory_INSTRUCTION_reg' and it is trimmed from '32' to '30' bits. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:2530]
  1560. WARNING: [Synth 8-3936] Found unconnected internal register 'storage_13_dat1_reg' and it is trimmed from '21' to '19' bits. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9804]
  1561. WARNING: [Synth 8-3936] Found unconnected internal register 'storage_12_dat1_reg' and it is trimmed from '5' to '3' bits. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9783]
  1562. WARNING: [Synth 8-3936] Found unconnected internal register 'storage_1_dat1_reg' and it is trimmed from '10' to '8' bits. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9317]
  1563. WARNING: [Synth 8-3936] Found unconnected internal register 'storage_2_dat1_reg' and it is trimmed from '10' to '8' bits. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:9338]
  1564. INFO: [Synth 8-802] inferred FSM for state register 'subfragments_resetinserter_state_reg' in module 'fairwaves_xtrx'
  1565. INFO: [Synth 8-802] inferred FSM for state register 'subfragments_litepcietlpdepacketizer_state_reg' in module 'fairwaves_xtrx'
  1566. INFO: [Synth 8-802] inferred FSM for state register 'subfragments_litepcietlppacketizer_state_reg' in module 'fairwaves_xtrx'
  1567. INFO: [Synth 8-802] inferred FSM for state register 'subfragments_fsm0_state_reg' in module 'fairwaves_xtrx'
  1568. INFO: [Synth 8-802] inferred FSM for state register 'subfragments_fsm1_state_reg' in module 'fairwaves_xtrx'
  1569. INFO: [Synth 8-802] inferred FSM for state register 'subfragments_litepciewishbonemaster_state_reg' in module 'fairwaves_xtrx'
  1570. INFO: [Synth 8-802] inferred FSM for state register 'subfragments_s7spiflash_state_reg' in module 'fairwaves_xtrx'
  1571. INFO: [Synth 8-802] inferred FSM for state register 'basesoc_grant_reg' in module 'fairwaves_xtrx'
  1572. ---------------------------------------------------------------------------------------------------
  1573. State | New Encoding | Previous Encoding
  1574. ---------------------------------------------------------------------------------------------------
  1575. iSTATE | 0 | 00
  1576. *
  1577. iSTATE1 | 1 | 10
  1578. ---------------------------------------------------------------------------------------------------
  1579. INFO: [Synth 8-3354] encoded FSM with state register 'subfragments_fsm0_state_reg' using encoding 'sequential' in module 'fairwaves_xtrx'
  1580. ---------------------------------------------------------------------------------------------------
  1581. State | New Encoding | Previous Encoding
  1582. ---------------------------------------------------------------------------------------------------
  1583. iSTATE1 | 00 | 00
  1584. *
  1585. iSTATE | 01 | 01
  1586. iSTATE0 | 10 | 10
  1587. ---------------------------------------------------------------------------------------------------
  1588. INFO: [Synth 8-3354] encoded FSM with state register 'subfragments_fsm1_state_reg' using encoding 'sequential' in module 'fairwaves_xtrx'
  1589. ---------------------------------------------------------------------------------------------------
  1590. State | New Encoding | Previous Encoding
  1591. ---------------------------------------------------------------------------------------------------
  1592. iSTATE | 00 | 00
  1593. *
  1594. iSTATE0 | 01 | 01
  1595. iSTATE1 | 10 | 10
  1596. ---------------------------------------------------------------------------------------------------
  1597. INFO: [Synth 8-3354] encoded FSM with state register 'subfragments_litepcietlpdepacketizer_state_reg' using encoding 'sequential' in module 'fairwaves_xtrx'
  1598. ---------------------------------------------------------------------------------------------------
  1599. State | New Encoding | Previous Encoding
  1600. ---------------------------------------------------------------------------------------------------
  1601. iSTATE1 | 00 | 00
  1602. *
  1603. iSTATE | 01 | 01
  1604. iSTATE0 | 10 | 10
  1605. iSTATE2 | 11 | 11
  1606. ---------------------------------------------------------------------------------------------------
  1607. INFO: [Synth 8-3354] encoded FSM with state register 'subfragments_s7spiflash_state_reg' using encoding 'sequential' in module 'fairwaves_xtrx'
  1608. ---------------------------------------------------------------------------------------------------
  1609. State | New Encoding | Previous Encoding
  1610. ---------------------------------------------------------------------------------------------------
  1611. iSTATE4 | 000 | 000
  1612. *
  1613. iSTATE | 001 | 001
  1614. iSTATE3 | 010 | 010
  1615. iSTATE2 | 011 | 011
  1616. iSTATE0 | 100 | 100
  1617. iSTATE1 | 101 | 101
  1618. ---------------------------------------------------------------------------------------------------
  1619. INFO: [Synth 8-3354] encoded FSM with state register 'subfragments_resetinserter_state_reg' using encoding 'sequential' in module 'fairwaves_xtrx'
  1620. ---------------------------------------------------------------------------------------------------
  1621. State | New Encoding | Previous Encoding
  1622. ---------------------------------------------------------------------------------------------------
  1623. iSTATE1 | 00 | 00
  1624. *
  1625. iSTATE | 01 | 01
  1626. iSTATE0 | 10 | 10
  1627. ---------------------------------------------------------------------------------------------------
  1628. INFO: [Synth 8-3354] encoded FSM with state register 'subfragments_litepcietlppacketizer_state_reg' using encoding 'sequential' in module 'fairwaves_xtrx'
  1629. ---------------------------------------------------------------------------------------------------
  1630. State | New Encoding | Previous Encoding
  1631. ---------------------------------------------------------------------------------------------------
  1632. iSTATE | 00 | 00
  1633. *
  1634. iSTATE2 | 01 | 01
  1635. iSTATE1 | 10 | 10
  1636. iSTATE0 | 11 | 11
  1637. ---------------------------------------------------------------------------------------------------
  1638. INFO: [Synth 8-3354] encoded FSM with state register 'subfragments_litepciewishbonemaster_state_reg' using encoding 'sequential' in module 'fairwaves_xtrx'
  1639. ---------------------------------------------------------------------------------------------------
  1640. State | New Encoding | Previous Encoding
  1641. ---------------------------------------------------------------------------------------------------
  1642. iSTATE1 | 001 | 00
  1643. iSTATE | 010 | 10
  1644. iSTATE0 | 100 | 01
  1645. ---------------------------------------------------------------------------------------------------
  1646. INFO: [Synth 8-3354] encoded FSM with state register 'basesoc_grant_reg' using encoding 'one-hot' in module 'fairwaves_xtrx'
  1647. ---------------------------------------------------------------------------------
  1648. Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 3218.871 ; gain = 271.137 ; free physical = 2036 ; free virtual = 20884
  1649. ---------------------------------------------------------------------------------
  1650. ---------------------------------------------------------------------------------
  1651. Start RTL Component Statistics
  1652. ---------------------------------------------------------------------------------
  1653. Detailed RTL Component Info :
  1654. +---Adders :
  1655. 2 Input 64 Bit Adders := 1
  1656. 3 Input 52 Bit Adders := 1
  1657. 2 Input 33 Bit Adders := 1
  1658. 3 Input 33 Bit Adders := 1
  1659. 2 Input 32 Bit Adders := 11
  1660. 3 Input 32 Bit Adders := 3
  1661. 2 Input 30 Bit Adders := 1
  1662. 2 Input 24 Bit Adders := 2
  1663. 2 Input 16 Bit Adders := 2
  1664. 4 Input 12 Bit Adders := 1
  1665. 2 Input 11 Bit Adders := 3
  1666. 2 Input 9 Bit Adders := 12
  1667. 2 Input 8 Bit Adders := 40
  1668. 2 Input 7 Bit Adders := 2
  1669. 2 Input 6 Bit Adders := 3
  1670. 2 Input 5 Bit Adders := 3
  1671. 2 Input 4 Bit Adders := 14
  1672. 2 Input 3 Bit Adders := 15
  1673. 2 Input 1 Bit Adders := 2
  1674. +---XORs :
  1675. 2 Input 32 Bit XORs := 1
  1676. 2 Input 3 Bit XORs := 6
  1677. 2 Input 1 Bit XORs := 2
  1678. +---Registers :
  1679. 166 Bit Registers := 8
  1680. 128 Bit Registers := 1
  1681. 74 Bit Registers := 2
  1682. 66 Bit Registers := 3
  1683. 65 Bit Registers := 1
  1684. 64 Bit Registers := 7
  1685. 58 Bit Registers := 2
  1686. 52 Bit Registers := 1
  1687. 40 Bit Registers := 4
  1688. 34 Bit Registers := 1
  1689. 33 Bit Registers := 1
  1690. 32 Bit Registers := 71
  1691. 30 Bit Registers := 4
  1692. 24 Bit Registers := 5
  1693. 22 Bit Registers := 2
  1694. 19 Bit Registers := 1
  1695. 17 Bit Registers := 1
  1696. 16 Bit Registers := 12
  1697. 12 Bit Registers := 1
  1698. 11 Bit Registers := 3
  1699. 10 Bit Registers := 2
  1700. 9 Bit Registers := 11
  1701. 8 Bit Registers := 42
  1702. 7 Bit Registers := 1
  1703. 6 Bit Registers := 4
  1704. 5 Bit Registers := 5
  1705. 4 Bit Registers := 18
  1706. 3 Bit Registers := 30
  1707. 2 Bit Registers := 23
  1708. 1 Bit Registers := 234
  1709. +---RAMs :
  1710. 132K Bit (2048 X 66 bit) RAMs := 1
  1711. 64K Bit (2048 X 32 bit) RAMs := 1
  1712. 41K Bit (256 X 166 bit) RAMs := 8
  1713. 32K Bit (1024 X 32 bit) RAMs := 1
  1714. 16K Bit (256 X 66 bit) RAMs := 1
  1715. 15K Bit (256 X 60 bit) RAMs := 2
  1716. 8K Bit (1024 X 8 bit) RAMs := 4
  1717. 8K Bit (128 X 66 bit) RAMs := 1
  1718. 2K Bit (128 X 22 bit) RAMs := 2
  1719. 1024 Bit (32 X 32 bit) RAMs := 1
  1720. 296 Bit (4 X 74 bit) RAMs := 2
  1721. 168 Bit (8 X 21 bit) RAMs := 1
  1722. 160 Bit (16 X 10 bit) RAMs := 3
  1723. 40 Bit (8 X 5 bit) RAMs := 1
  1724. 32 Bit (4 X 8 bit) RAMs := 1
  1725. +---ROMs :
  1726. ROMs := 1
  1727. +---Muxes :
  1728. 2 Input 96 Bit Muxes := 1
  1729. 2 Input 64 Bit Muxes := 17
  1730. 8 Input 64 Bit Muxes := 8
  1731. 3 Input 64 Bit Muxes := 2
  1732. 2 Input 40 Bit Muxes := 1
  1733. 2 Input 33 Bit Muxes := 3
  1734. 2 Input 32 Bit Muxes := 117
  1735. 3 Input 32 Bit Muxes := 7
  1736. 4 Input 32 Bit Muxes := 7
  1737. 6 Input 32 Bit Muxes := 1
  1738. 10 Input 32 Bit Muxes := 1
  1739. 2 Input 30 Bit Muxes := 3
  1740. 4 Input 30 Bit Muxes := 1
  1741. 2 Input 25 Bit Muxes := 1
  1742. 2 Input 24 Bit Muxes := 6
  1743. 7 Input 16 Bit Muxes := 2
  1744. 2 Input 16 Bit Muxes := 17
  1745. 8 Input 16 Bit Muxes := 16
  1746. 2 Input 14 Bit Muxes := 2
  1747. 2 Input 12 Bit Muxes := 1
  1748. 2 Input 10 Bit Muxes := 10
  1749. 8 Input 10 Bit Muxes := 8
  1750. 4 Input 8 Bit Muxes := 1
  1751. 2 Input 8 Bit Muxes := 12
  1752. 3 Input 8 Bit Muxes := 1
  1753. 2 Input 7 Bit Muxes := 10
  1754. 8 Input 7 Bit Muxes := 8
  1755. 2 Input 6 Bit Muxes := 4
  1756. 4 Input 6 Bit Muxes := 1
  1757. 2 Input 5 Bit Muxes := 5
  1758. 4 Input 4 Bit Muxes := 3
  1759. 2 Input 4 Bit Muxes := 12
  1760. 5 Input 4 Bit Muxes := 1
  1761. 6 Input 4 Bit Muxes := 2
  1762. 3 Input 4 Bit Muxes := 1
  1763. 2 Input 3 Bit Muxes := 23
  1764. 3 Input 3 Bit Muxes := 4
  1765. 8 Input 3 Bit Muxes := 4
  1766. 6 Input 3 Bit Muxes := 2
  1767. 2 Input 2 Bit Muxes := 32
  1768. 8 Input 2 Bit Muxes := 2
  1769. 3 Input 2 Bit Muxes := 3
  1770. 4 Input 2 Bit Muxes := 2
  1771. 2 Input 1 Bit Muxes := 301
  1772. 3 Input 1 Bit Muxes := 25
  1773. 4 Input 1 Bit Muxes := 15
  1774. 8 Input 1 Bit Muxes := 49
  1775. 7 Input 1 Bit Muxes := 2
  1776. 10 Input 1 Bit Muxes := 2
  1777. 6 Input 1 Bit Muxes := 6
  1778. ---------------------------------------------------------------------------------
  1779. Finished RTL Component Statistics
  1780. ---------------------------------------------------------------------------------
  1781. ---------------------------------------------------------------------------------
  1782. Start Part Resource Summary
  1783. ---------------------------------------------------------------------------------
  1784. Part Resources:
  1785. DSPs: 120 (col length:60)
  1786. BRAMs: 150 (col length: RAMB18 60 RAMB36 30)
  1787. ---------------------------------------------------------------------------------
  1788. Finished Part Resource Summary
  1789. ---------------------------------------------------------------------------------
  1790. ---------------------------------------------------------------------------------
  1791. Start Cross Boundary and Area Optimization
  1792. ---------------------------------------------------------------------------------
  1793. WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
  1794. WARNING: [Synth 8-3936] Found unconnected internal register 'memory_to_writeBack_MUL_HH_reg' and it is trimmed from '34' to '32' bits. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:2500]
  1795. WARNING: [Synth 8-3936] Found unconnected internal register 'execute_to_memory_MUL_HH_reg' and it is trimmed from '34' to '32' bits. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v:2444]
  1796. DSP Report: Generating DSP memory_to_writeBack_MUL_HH_reg, operation Mode is: (A*B)'.
  1797. DSP Report: register memory_to_writeBack_MUL_HH_reg is absorbed into DSP memory_to_writeBack_MUL_HH_reg.
  1798. DSP Report: register execute_to_memory_MUL_HH_reg is absorbed into DSP memory_to_writeBack_MUL_HH_reg.
  1799. DSP Report: operator execute_MUL_HH is absorbed into DSP memory_to_writeBack_MUL_HH_reg.
  1800. DSP Report: Generating DSP execute_to_memory_MUL_LH_reg, operation Mode is: (A*B)'.
  1801. DSP Report: register execute_to_memory_MUL_LH_reg is absorbed into DSP execute_to_memory_MUL_LH_reg.
  1802. DSP Report: operator execute_MUL_LH is absorbed into DSP execute_to_memory_MUL_LH_reg.
  1803. DSP Report: Generating DSP execute_to_memory_MUL_HL_reg, operation Mode is: (A*B)'.
  1804. DSP Report: register execute_to_memory_MUL_HL_reg is absorbed into DSP execute_to_memory_MUL_HL_reg.
  1805. DSP Report: operator execute_MUL_HL is absorbed into DSP execute_to_memory_MUL_HL_reg.
  1806. DSP Report: Generating DSP execute_to_memory_MUL_LL_reg, operation Mode is: (A*B)'.
  1807. DSP Report: register execute_to_memory_MUL_LL_reg is absorbed into DSP execute_to_memory_MUL_LL_reg.
  1808. DSP Report: operator execute_MUL_LL is absorbed into DSP execute_to_memory_MUL_LL_reg.
  1809. INFO: [Synth 8-3971] The signal "VexRiscv/RegFilePlugin_regFile_reg" was recognized as a true dual port RAM template.
  1810. INFO: [Synth 8-5784] Optimized 49 bits of RAM "storage_14_reg" due to constant propagation. Old ram width 166 bits, new ram width 117 bits.
  1811. INFO: [Synth 8-5784] Optimized 48 bits of RAM "storage_15_reg" due to constant propagation. Old ram width 166 bits, new ram width 118 bits.
  1812. INFO: [Synth 8-5784] Optimized 48 bits of RAM "storage_16_reg" due to constant propagation. Old ram width 166 bits, new ram width 118 bits.
  1813. INFO: [Synth 8-5784] Optimized 47 bits of RAM "storage_17_reg" due to constant propagation. Old ram width 166 bits, new ram width 119 bits.
  1814. INFO: [Synth 8-5784] Optimized 48 bits of RAM "storage_18_reg" due to constant propagation. Old ram width 166 bits, new ram width 118 bits.
  1815. INFO: [Synth 8-5784] Optimized 47 bits of RAM "storage_19_reg" due to constant propagation. Old ram width 166 bits, new ram width 119 bits.
  1816. INFO: [Synth 8-5784] Optimized 47 bits of RAM "storage_20_reg" due to constant propagation. Old ram width 166 bits, new ram width 119 bits.
  1817. INFO: [Synth 8-5784] Optimized 46 bits of RAM "storage_21_reg" due to constant propagation. Old ram width 166 bits, new ram width 120 bits.
  1818. INFO: [Synth 8-5784] Optimized 1 bits of RAM "storage_9_reg" due to constant propagation. Old ram width 66 bits, new ram width 65 bits.
  1819. RAM Pipeline Warning: Read Address Register Found For RAM mem_1_reg. We will not be able to pipeline it. This may degrade performance.
  1820. RAM Pipeline Warning: Read Address Register Found For RAM mem_1_reg. We will not be able to pipeline it. This may degrade performance.
  1821. WARNING: [Synth 8-7257] Removed RAM (storage_11_reg) due to inactive write enable.
  1822. RAM Pipeline Warning: Read Address Register Found For RAM mem_1_reg. We will not be able to pipeline it. This may degrade performance.
  1823. ---------------------------------------------------------------------------------
  1824. Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:13 ; elapsed = 00:01:14 . Memory (MB): peak = 3218.871 ; gain = 271.137 ; free physical = 1863 ; free virtual = 20735
  1825. ---------------------------------------------------------------------------------
  1826. ---------------------------------------------------------------------------------
  1827. Start ROM, RAM, DSP, Shift Register and Retiming Reporting
  1828. ---------------------------------------------------------------------------------
  1829.  
  1830. ROM: Preliminary Mapping Report
  1831. +---------------+--------------+---------------+----------------+
  1832. |Module Name | RTL Object | Depth x Width | Implemented As |
  1833. +---------------+--------------+---------------+----------------+
  1834. |fairwaves_xtrx | mem_2 | 64x8 | LUT |
  1835. |fairwaves_xtrx | mem_dat0_reg | 8192x32 | Block RAM |
  1836. |fairwaves_xtrx | p_0_out | 64x8 | LUT |
  1837. |fairwaves_xtrx | mem_dat0_reg | 8192x32 | Block RAM |
  1838. +---------------+--------------+---------------+----------------+
  1839.  
  1840.  
  1841. Block RAM: Preliminary Mapping Report (see note below)
  1842. +--------------------------------+-------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
  1843. |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
  1844. +--------------------------------+-------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
  1845. |VexRiscv/IBusCachedPlugin_cache | banks_0_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 |
  1846. |VexRiscv/IBusCachedPlugin_cache | ways_0_tags_reg | 128 x 22(READ_FIRST) | W | | 128 x 22(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
  1847. |VexRiscv/dataCache_1 | ways_0_tags_reg | 128 x 22(READ_FIRST) | W | | 128 x 22(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
  1848. |VexRiscv/dataCache_1 | ways_0_data_symbol0_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
  1849. |VexRiscv/dataCache_1 | ways_0_data_symbol1_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
  1850. |VexRiscv/dataCache_1 | ways_0_data_symbol2_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
  1851. |VexRiscv/dataCache_1 | ways_0_data_symbol3_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
  1852. |fairwaves_xtrx | storage_14_reg | 256 x 166(READ_FIRST) | W | | 256 x 166(WRITE_FIRST) | | R | Port A and B | 0 | 2 |
  1853. |fairwaves_xtrx | storage_15_reg | 256 x 166(READ_FIRST) | W | | 256 x 166(WRITE_FIRST) | | R | Port A and B | 0 | 2 |
  1854. |fairwaves_xtrx | storage_16_reg | 256 x 166(READ_FIRST) | W | | 256 x 166(WRITE_FIRST) | | R | Port A and B | 0 | 2 |
  1855. |fairwaves_xtrx | storage_17_reg | 256 x 166(READ_FIRST) | W | | 256 x 166(WRITE_FIRST) | | R | Port A and B | 0 | 2 |
  1856. |fairwaves_xtrx | storage_18_reg | 256 x 166(READ_FIRST) | W | | 256 x 166(WRITE_FIRST) | | R | Port A and B | 0 | 2 |
  1857. |fairwaves_xtrx | storage_19_reg | 256 x 166(READ_FIRST) | W | | 256 x 166(WRITE_FIRST) | | R | Port A and B | 0 | 2 |
  1858. |fairwaves_xtrx | storage_20_reg | 256 x 166(READ_FIRST) | W | | 256 x 166(WRITE_FIRST) | | R | Port A and B | 0 | 2 |
  1859. |fairwaves_xtrx | storage_21_reg | 256 x 166(READ_FIRST) | W | | 256 x 166(WRITE_FIRST) | | R | Port A and B | 0 | 2 |
  1860. |fairwaves_xtrx | storage_9_reg | 2 K x 66(READ_FIRST) | W | | 2 K x 66(WRITE_FIRST) | | R | Port A and B | 0 | 4 |
  1861. |fairwaves_xtrx | storage_7_reg | 256 x 66(READ_FIRST) | W | | 256 x 66(WRITE_FIRST) | | R | Port A and B | 0 | 1 |
  1862. |fairwaves_xtrx | mem_1_reg | 2 K x 32(WRITE_FIRST) | W | R | | | | Port A | 0 | 2 |
  1863. +--------------------------------+-------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
  1864.  
  1865. Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once.
  1866.  
  1867. Distributed RAM: Preliminary Mapping Report (see note below)
  1868. +---------------+----------------+-----------+----------------------+--------------+
  1869. |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
  1870. +---------------+----------------+-----------+----------------------+--------------+
  1871. |fairwaves_xtrx | storage_4_reg | Implied | 4 x 74 | RAM32M x 13 |
  1872. |fairwaves_xtrx | storage_8_reg | Implied | 256 x 60 | RAM64M x 80 |
  1873. |fairwaves_xtrx | storage_13_reg | Implied | 8 x 21 | RAM32M x 4 |
  1874. |fairwaves_xtrx | storage_12_reg | Implied | 8 x 3 | RAM32M x 1 |
  1875. |fairwaves_xtrx | storage_6_reg | Implied | 256 x 60 | RAM64M x 80 |
  1876. |fairwaves_xtrx | storage_1_reg | Implied | 16 x 10 | RAM32M x 2 |
  1877. |fairwaves_xtrx | storage_reg | Implied | 16 x 8 | RAM32M x 2 |
  1878. |fairwaves_xtrx | storage_2_reg | Implied | 16 x 10 | RAM32M x 2 |
  1879. |fairwaves_xtrx | storage_3_reg | Implied | 4 x 74 | RAM32M x 13 |
  1880. +---------------+----------------+-----------+----------------------+--------------+
  1881.  
  1882. Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
  1883.  
  1884. DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)
  1885. +------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
  1886. |Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
  1887. +------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
  1888. |VexRiscv | (A*B)' | 17 | 17 | - | - | 34 | 0 | 0 | - | - | - | 1 | 1 |
  1889. |VexRiscv | (A*B)' | 17 | 17 | - | - | 34 | 0 | 0 | - | - | - | 1 | 0 |
  1890. |VexRiscv | (A*B)' | 17 | 17 | - | - | 34 | 0 | 0 | - | - | - | 1 | 0 |
  1891. |VexRiscv | (A*B)' | 16 | 16 | - | - | 32 | 0 | 0 | - | - | - | 1 | 0 |
  1892. +------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
  1893.  
  1894. Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
  1895. ---------------------------------------------------------------------------------
  1896. Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
  1897. ---------------------------------------------------------------------------------
  1898. ---------------------------------------------------------------------------------
  1899. Start Applying XDC Timing Constraints
  1900. ---------------------------------------------------------------------------------
  1901. pcie_support/pcie_i/user_clk_out in more then one group at line 76 of file /home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc
  1902. ---------------------------------------------------------------------------------
  1903. Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:16 ; elapsed = 00:01:17 . Memory (MB): peak = 3218.871 ; gain = 271.137 ; free physical = 1783 ; free virtual = 20655
  1904. ---------------------------------------------------------------------------------
  1905. ---------------------------------------------------------------------------------
  1906. Start Timing Optimization
  1907. ---------------------------------------------------------------------------------
  1908. ---------------------------------------------------------------------------------
  1909. Finished Timing Optimization : Time (s): cpu = 00:01:18 ; elapsed = 00:01:19 . Memory (MB): peak = 3218.871 ; gain = 271.137 ; free physical = 1768 ; free virtual = 20639
  1910. ---------------------------------------------------------------------------------
  1911. ---------------------------------------------------------------------------------
  1912. Start ROM, RAM, DSP, Shift Register and Retiming Reporting
  1913. ---------------------------------------------------------------------------------
  1914.  
  1915. Block RAM: Final Mapping Report
  1916. +--------------------------------+-------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
  1917. |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
  1918. +--------------------------------+-------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
  1919. |VexRiscv/IBusCachedPlugin_cache | banks_0_reg | 1 K x 32(READ_FIRST) | W | | 1 K x 32(WRITE_FIRST) | | R | Port A and B | 0 | 1 |
  1920. |VexRiscv/IBusCachedPlugin_cache | ways_0_tags_reg | 128 x 22(READ_FIRST) | W | | 128 x 22(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
  1921. |VexRiscv/dataCache_1 | ways_0_tags_reg | 128 x 22(READ_FIRST) | W | | 128 x 22(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
  1922. |VexRiscv/dataCache_1 | ways_0_data_symbol0_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
  1923. |VexRiscv/dataCache_1 | ways_0_data_symbol1_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
  1924. |VexRiscv/dataCache_1 | ways_0_data_symbol2_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
  1925. |VexRiscv/dataCache_1 | ways_0_data_symbol3_reg | 1 K x 8(READ_FIRST) | W | | 1 K x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
  1926. |fairwaves_xtrx | storage_14_reg | 256 x 166(READ_FIRST) | W | | 256 x 166(WRITE_FIRST) | | R | Port A and B | 0 | 2 |
  1927. |fairwaves_xtrx | storage_15_reg | 256 x 166(READ_FIRST) | W | | 256 x 166(WRITE_FIRST) | | R | Port A and B | 0 | 2 |
  1928. |fairwaves_xtrx | storage_16_reg | 256 x 166(READ_FIRST) | W | | 256 x 166(WRITE_FIRST) | | R | Port A and B | 0 | 2 |
  1929. |fairwaves_xtrx | storage_17_reg | 256 x 166(READ_FIRST) | W | | 256 x 166(WRITE_FIRST) | | R | Port A and B | 0 | 2 |
  1930. |fairwaves_xtrx | storage_18_reg | 256 x 166(READ_FIRST) | W | | 256 x 166(WRITE_FIRST) | | R | Port A and B | 0 | 2 |
  1931. |fairwaves_xtrx | storage_19_reg | 256 x 166(READ_FIRST) | W | | 256 x 166(WRITE_FIRST) | | R | Port A and B | 0 | 2 |
  1932. |fairwaves_xtrx | storage_20_reg | 256 x 166(READ_FIRST) | W | | 256 x 166(WRITE_FIRST) | | R | Port A and B | 0 | 2 |
  1933. |fairwaves_xtrx | storage_21_reg | 256 x 166(READ_FIRST) | W | | 256 x 166(WRITE_FIRST) | | R | Port A and B | 0 | 2 |
  1934. |fairwaves_xtrx | storage_9_reg | 2 K x 66(READ_FIRST) | W | | 2 K x 66(WRITE_FIRST) | | R | Port A and B | 0 | 4 |
  1935. |fairwaves_xtrx | storage_7_reg | 256 x 66(READ_FIRST) | W | | 256 x 66(WRITE_FIRST) | | R | Port A and B | 0 | 1 |
  1936. |fairwaves_xtrx | mem_1_reg | 2 K x 32(WRITE_FIRST) | W | R | | | | Port A | 0 | 2 |
  1937. +--------------------------------+-------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
  1938.  
  1939.  
  1940. Distributed RAM: Final Mapping Report
  1941. +---------------+----------------+-----------+----------------------+--------------+
  1942. |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
  1943. +---------------+----------------+-----------+----------------------+--------------+
  1944. |fairwaves_xtrx | storage_4_reg | Implied | 4 x 74 | RAM32M x 13 |
  1945. |fairwaves_xtrx | storage_8_reg | Implied | 256 x 60 | RAM64M x 80 |
  1946. |fairwaves_xtrx | storage_13_reg | Implied | 8 x 21 | RAM32M x 4 |
  1947. |fairwaves_xtrx | storage_12_reg | Implied | 8 x 3 | RAM32M x 1 |
  1948. |fairwaves_xtrx | storage_6_reg | Implied | 256 x 60 | RAM64M x 80 |
  1949. |fairwaves_xtrx | storage_1_reg | Implied | 16 x 10 | RAM32M x 2 |
  1950. |fairwaves_xtrx | storage_reg | Implied | 16 x 8 | RAM32M x 2 |
  1951. |fairwaves_xtrx | storage_2_reg | Implied | 16 x 10 | RAM32M x 2 |
  1952. |fairwaves_xtrx | storage_3_reg | Implied | 4 x 74 | RAM32M x 13 |
  1953. +---------------+----------------+-----------+----------------------+--------------+
  1954.  
  1955. ---------------------------------------------------------------------------------
  1956. Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
  1957. ---------------------------------------------------------------------------------
  1958. ---------------------------------------------------------------------------------
  1959. Start Technology Mapping
  1960. ---------------------------------------------------------------------------------
  1961. INFO: [Synth 8-7052] The timing for the instance VexRiscv/IBusCachedPlugin_cache/banks_0_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1962. INFO: [Synth 8-7052] The timing for the instance VexRiscv/IBusCachedPlugin_cache/ways_0_tags_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1963. INFO: [Synth 8-7052] The timing for the instance VexRiscv/dataCache_1/ways_0_tags_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1964. INFO: [Synth 8-7052] The timing for the instance VexRiscv/RegFilePlugin_regFile_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1965. INFO: [Synth 8-7052] The timing for the instance VexRiscv/RegFilePlugin_regFile_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1966. INFO: [Synth 8-7052] The timing for the instance storage_14_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1967. INFO: [Synth 8-7052] The timing for the instance storage_14_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1968. INFO: [Synth 8-7052] The timing for the instance storage_15_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1969. INFO: [Synth 8-7052] The timing for the instance storage_15_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1970. INFO: [Synth 8-7052] The timing for the instance storage_16_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1971. INFO: [Synth 8-7052] The timing for the instance storage_16_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1972. INFO: [Synth 8-7052] The timing for the instance storage_17_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1973. INFO: [Synth 8-7052] The timing for the instance storage_17_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1974. INFO: [Synth 8-7052] The timing for the instance storage_18_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1975. INFO: [Synth 8-7052] The timing for the instance storage_18_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1976. INFO: [Synth 8-7052] The timing for the instance storage_19_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1977. INFO: [Synth 8-7052] The timing for the instance storage_19_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1978. INFO: [Synth 8-7052] The timing for the instance storage_20_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1979. INFO: [Synth 8-7052] The timing for the instance storage_20_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1980. INFO: [Synth 8-7052] The timing for the instance storage_21_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1981. INFO: [Synth 8-7052] The timing for the instance storage_21_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1982. INFO: [Synth 8-7052] The timing for the instance storage_9_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1983. INFO: [Synth 8-7052] The timing for the instance storage_9_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1984. INFO: [Synth 8-7052] The timing for the instance storage_9_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1985. INFO: [Synth 8-7052] The timing for the instance storage_9_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1986. INFO: [Synth 8-7052] The timing for the instance storage_7_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1987. INFO: [Synth 8-7052] The timing for the instance mem_1_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1988. INFO: [Synth 8-7052] The timing for the instance mem_1_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1989. INFO: [Synth 8-7052] The timing for the instance mem_dat0_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1990. INFO: [Synth 8-7052] The timing for the instance mem_dat0_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1991. INFO: [Synth 8-7052] The timing for the instance mem_dat0_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1992. INFO: [Synth 8-7052] The timing for the instance mem_dat0_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1993. INFO: [Synth 8-7052] The timing for the instance mem_dat0_reg_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1994. INFO: [Synth 8-7052] The timing for the instance mem_dat0_reg_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1995. INFO: [Synth 8-7052] The timing for the instance mem_dat0_reg_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1996. INFO: [Synth 8-7052] The timing for the instance mem_dat0_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
  1997. ---------------------------------------------------------------------------------
  1998. Finished Technology Mapping : Time (s): cpu = 00:01:22 ; elapsed = 00:01:23 . Memory (MB): peak = 3218.871 ; gain = 271.137 ; free physical = 1705 ; free virtual = 20576
  1999. ---------------------------------------------------------------------------------
  2000. ---------------------------------------------------------------------------------
  2001. Start IO Insertion
  2002. ---------------------------------------------------------------------------------
  2003. ---------------------------------------------------------------------------------
  2004. Start Flattening Before IO Insertion
  2005. ---------------------------------------------------------------------------------
  2006. ---------------------------------------------------------------------------------
  2007. Finished Flattening Before IO Insertion
  2008. ---------------------------------------------------------------------------------
  2009. ---------------------------------------------------------------------------------
  2010. Start Final Netlist Cleanup
  2011. ---------------------------------------------------------------------------------
  2012. ---------------------------------------------------------------------------------
  2013. Finished Final Netlist Cleanup
  2014. ---------------------------------------------------------------------------------
  2015. WARNING: [Synth 8-5396] Clock pin WCLK has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:20]
  2016. WARNING: [Synth 8-5396] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.v:7442]
  2017. ---------------------------------------------------------------------------------
  2018. Finished IO Insertion : Time (s): cpu = 00:01:26 ; elapsed = 00:01:27 . Memory (MB): peak = 3218.871 ; gain = 271.137 ; free physical = 1702 ; free virtual = 20589
  2019. ---------------------------------------------------------------------------------
  2020. ---------------------------------------------------------------------------------
  2021. Start Renaming Generated Instances
  2022. ---------------------------------------------------------------------------------
  2023. ---------------------------------------------------------------------------------
  2024. Finished Renaming Generated Instances : Time (s): cpu = 00:01:26 ; elapsed = 00:01:27 . Memory (MB): peak = 3218.871 ; gain = 271.137 ; free physical = 1702 ; free virtual = 20589
  2025. ---------------------------------------------------------------------------------
  2026. ---------------------------------------------------------------------------------
  2027. Start Rebuilding User Hierarchy
  2028. ---------------------------------------------------------------------------------
  2029. ---------------------------------------------------------------------------------
  2030. Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:26 ; elapsed = 00:01:28 . Memory (MB): peak = 3218.871 ; gain = 271.137 ; free physical = 1701 ; free virtual = 20589
  2031. ---------------------------------------------------------------------------------
  2032. ---------------------------------------------------------------------------------
  2033. Start Renaming Generated Ports
  2034. ---------------------------------------------------------------------------------
  2035. ---------------------------------------------------------------------------------
  2036. Finished Renaming Generated Ports : Time (s): cpu = 00:01:26 ; elapsed = 00:01:28 . Memory (MB): peak = 3218.871 ; gain = 271.137 ; free physical = 1702 ; free virtual = 20590
  2037. ---------------------------------------------------------------------------------
  2038. ---------------------------------------------------------------------------------
  2039. Start Handling Custom Attributes
  2040. ---------------------------------------------------------------------------------
  2041. ---------------------------------------------------------------------------------
  2042. Finished Handling Custom Attributes : Time (s): cpu = 00:01:27 ; elapsed = 00:01:28 . Memory (MB): peak = 3218.871 ; gain = 271.137 ; free physical = 1758 ; free virtual = 20645
  2043. ---------------------------------------------------------------------------------
  2044. ---------------------------------------------------------------------------------
  2045. Start Renaming Generated Nets
  2046. ---------------------------------------------------------------------------------
  2047. ---------------------------------------------------------------------------------
  2048. Finished Renaming Generated Nets : Time (s): cpu = 00:01:27 ; elapsed = 00:01:28 . Memory (MB): peak = 3218.871 ; gain = 271.137 ; free physical = 1757 ; free virtual = 20645
  2049. ---------------------------------------------------------------------------------
  2050. ---------------------------------------------------------------------------------
  2051. Start Writing Synthesis Report
  2052. ---------------------------------------------------------------------------------
  2053.  
  2054. Report BlackBoxes:
  2055. +------+--------------+----------+
  2056. | |BlackBox name |Instances |
  2057. +------+--------------+----------+
  2058. |1 |pcie_s7 | 1|
  2059. +------+--------------+----------+
  2060.  
  2061. Report Cell Usage:
  2062. +------+------------+------+
  2063. | |Cell |Count |
  2064. +------+------------+------+
  2065. |1 |pcie_s7 | 1|
  2066. |2 |BUFG | 3|
  2067. |3 |BUFGCTRL | 1|
  2068. |4 |CARRY4 | 249|
  2069. |5 |DSP48E1 | 4|
  2070. |7 |IBUFDS_GTE2 | 1|
  2071. |8 |ICAPE2 | 1|
  2072. |9 |LUT1 | 254|
  2073. |10 |LUT2 | 1118|
  2074. |11 |LUT3 | 1384|
  2075. |12 |LUT4 | 807|
  2076. |13 |LUT5 | 848|
  2077. |14 |LUT6 | 1673|
  2078. |15 |MMCME2_ADV | 1|
  2079. |16 |MUXF7 | 7|
  2080. |17 |RAM32M | 33|
  2081. |18 |RAM32X1D | 4|
  2082. |19 |RAM64M | 160|
  2083. |20 |RAMB18E1 | 8|
  2084. |22 |RAMB36E1 | 32|
  2085. |34 |STARTUPE2 | 1|
  2086. |35 |FDRE | 4145|
  2087. |36 |FDSE | 75|
  2088. |37 |IBUF | 8|
  2089. |38 |OBUF | 7|
  2090. +------+------------+------+
  2091. ---------------------------------------------------------------------------------
  2092. Finished Writing Synthesis Report : Time (s): cpu = 00:01:27 ; elapsed = 00:01:28 . Memory (MB): peak = 3218.871 ; gain = 271.137 ; free physical = 1757 ; free virtual = 20645
  2093. ---------------------------------------------------------------------------------
  2094. Synthesis finished with 0 errors, 0 critical warnings and 201 warnings.
  2095. Synthesis Optimization Runtime : Time (s): cpu = 00:01:24 ; elapsed = 00:01:26 . Memory (MB): peak = 3218.871 ; gain = 148.402 ; free physical = 1808 ; free virtual = 20695
  2096. Synthesis Optimization Complete : Time (s): cpu = 00:01:27 ; elapsed = 00:01:28 . Memory (MB): peak = 3218.871 ; gain = 271.137 ; free physical = 1808 ; free virtual = 20695
  2097. INFO: [Project 1-571] Translating synthesized netlist
  2098. INFO: [Project 1-454] Reading design checkpoint '/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/pcie_s7.dcp' for cell 'pcie_support/pcie_i'
  2099. Netlist sorting complete. Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.10 . Memory (MB): peak = 3218.871 ; gain = 0.000 ; free physical = 1904 ; free virtual = 20792
  2100. WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'pcie_support/pipe_clock_i/pclk_i1_bufgctrl.pclk_i1' of type 'BUFGCTRL' is 'ULTRASCALE'; it is being changed to match the current FPGA architecture, '7SERIES'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist.
  2101. INFO: [Netlist 29-17] Analyzing 525 Unisim elements for replacement
  2102. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
  2103. INFO: [Project 1-479] Netlist was created with Vivado 2021.2
  2104. INFO: [Project 1-570] Preparing netlist for logic optimization
  2105. Parsing XDC File [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc]
  2106. INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc:76]
  2107. WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -include_generated_clocks -of [get_nets sys_clk]'. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc:76]
  2108. Resolution: Verify the create_clock command was called to create the clock object before it is referenced.
  2109. INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc:76]
  2110. WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -include_generated_clocks -of [get_nets pcie_clk]'. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc:76]
  2111. Resolution: Verify the create_clock command was called to create the clock object before it is referenced.
  2112. INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc:76]
  2113. CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks -include_generated_clocks -of [get_nets sys_clk]]'. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc:76]
  2114. Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
  2115. CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group '. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc:76]
  2116. Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
  2117. CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks -include_generated_clocks -of [get_nets pcie_clk]]'. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc:76]
  2118. Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
  2119. CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group '. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc:76]
  2120. Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
  2121. CRITICAL WARNING: [Constraints 18-4644] set_clock_groups: All clock groups specified are empty. Please specify atleast one clock group which is not empty. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc:76]
  2122. WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -include_generated_clocks -of [get_nets sys_clk]'. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc:78]
  2123. Resolution: Verify the create_clock command was called to create the clock object before it is referenced.
  2124. INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc:78]
  2125. CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks -include_generated_clocks -of [get_nets sys_clk]]'. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc:78]
  2126. Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
  2127. CRITICAL WARNING: [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group '. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc:78]
  2128. Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
  2129. CRITICAL WARNING: [Vivado 12-5201] set_clock_groups: cannot set the clock group when only one non-empty group remains. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc:78]
  2130. WARNING: [Vivado 12-180] No cells matched 'get_cells -hierarchical -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}'. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc:87]
  2131. WARNING: [Vivado 12-508] No pins matched 'get_pins -filter {REF_PIN_NAME == PRE} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]'. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc:87]
  2132. WARNING: [Vivado 12-180] No cells matched 'get_cells -hierarchical -filter {ars_ff1 == TRUE}'. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc:89]
  2133. WARNING: [Vivado 12-508] No pins matched 'get_pins -filter {REF_PIN_NAME == C} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE}]'. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc:89]
  2134. WARNING: [Vivado 12-180] No cells matched 'get_cells -hierarchical -filter {ars_ff2 == TRUE}'. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc:89]
  2135. WARNING: [Vivado 12-508] No pins matched 'get_pins -filter {REF_PIN_NAME == D} -of_objects [get_cells -hierarchical -filter {ars_ff2 == TRUE}]'. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc:89]
  2136. Finished Parsing XDC File [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.xdc]
  2137. Parsing XDC File [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7-PCIE_X0Y0.xdc] for cell 'pcie_support/pcie_i/inst'
  2138. Finished Parsing XDC File [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7-PCIE_X0Y0.xdc] for cell 'pcie_support/pcie_i/inst'
  2139. INFO: [Project 1-538] Using original IP XDC constraints instead of the XDC constraints in dcp '/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/pcie_s7.dcp'
  2140. INFO: [Project 1-1714] 2 XPM XDC files have been applied to the design.
  2141. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  2142. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3268.688 ; gain = 0.000 ; free physical = 1895 ; free virtual = 20782
  2143. INFO: [Project 1-111] Unisim Transformation Summary:
  2144. A total of 197 instances were transformed.
  2145. RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 33 instances
  2146. RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances
  2147. RAM64M => RAM64M (RAMD64E(x4)): 160 instances
  2148.  
  2149. Synth Design complete, checksum: 93cf1df1
  2150. INFO: [Common 17-83] Releasing license: Synthesis
  2151. 135 Infos, 283 Warnings, 8 Critical Warnings and 0 Errors encountered.
  2152. synth_design completed successfully
  2153. synth_design: Time (s): cpu = 00:01:36 ; elapsed = 00:01:33 . Memory (MB): peak = 3268.688 ; gain = 320.953 ; free physical = 2118 ; free virtual = 21006
  2154. # report_timing_summary -file fairwaves_xtrx_timing_synth.rpt
  2155. INFO: [Timing 38-35] Done setting XDC timing constraints.
  2156. INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
  2157. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
  2158. # report_utilization -hierarchical -file fairwaves_xtrx_utilization_hierarchical_synth.rpt
  2159. # report_utilization -file fairwaves_xtrx_utilization_synth.rpt
  2160. # opt_design -directive default
  2161. Command: opt_design -directive default
  2162. INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: default
  2163. Attempting to get a license for feature 'Implementation' and/or device 'xc7a50t'
  2164. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a50t'
  2165. Running DRC as a precondition to command opt_design
  2166.  
  2167. Starting DRC Task
  2168. INFO: [DRC 23-27] Running DRC with 8 threads
  2169. INFO: [Project 1-461] DRC finished with 0 Errors
  2170. INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
  2171.  
  2172. Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.79 . Memory (MB): peak = 3339.746 ; gain = 64.031 ; free physical = 2080 ; free virtual = 20968
  2173.  
  2174. Starting Cache Timing Information Task
  2175. Ending Cache Timing Information Task | Checksum: 171aaa293
  2176.  
  2177. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3339.746 ; gain = 0.000 ; free physical = 2080 ; free virtual = 20968
  2178.  
  2179. Starting Logic Optimization Task
  2180.  
  2181. Phase 1 Retarget
  2182. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/CsrPlugin_mtvec_base[1]_i_1 into driver instance VexRiscv/CsrPlugin_mtvec_base[1]_i_2, which resulted in an inversion of 5 pins
  2183. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/IBusCachedPlugin_cache/basesoc_csr_bankarray_interface5_bank_bus_dat_r[31]_i_1 into driver instance VexRiscv/IBusCachedPlugin_cache/basesoc_csr_bankarray_interface5_bank_bus_dat_r[31]_i_3, which resulted in an inversion of 3 pins
  2184. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[10]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_46, which resulted in an inversion of 4 pins
  2185. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[14]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_45, which resulted in an inversion of 4 pins
  2186. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[16]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_64, which resulted in an inversion of 4 pins
  2187. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[17]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_63, which resulted in an inversion of 4 pins
  2188. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[18]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_62, which resulted in an inversion of 4 pins
  2189. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[19]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_61, which resulted in an inversion of 4 pins
  2190. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[1]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_48, which resulted in an inversion of 4 pins
  2191. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[20]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_60, which resulted in an inversion of 4 pins
  2192. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[21]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_59, which resulted in an inversion of 4 pins
  2193. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[22]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_58, which resulted in an inversion of 4 pins
  2194. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[23]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_57, which resulted in an inversion of 4 pins
  2195. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[24]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_56, which resulted in an inversion of 4 pins
  2196. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[25]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_55, which resulted in an inversion of 4 pins
  2197. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[26]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_54, which resulted in an inversion of 4 pins
  2198. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[27]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_53, which resulted in an inversion of 4 pins
  2199. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[28]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_52, which resulted in an inversion of 4 pins
  2200. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[29]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_51, which resulted in an inversion of 4 pins
  2201. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[30]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_50, which resulted in an inversion of 4 pins
  2202. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[31]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_49, which resulted in an inversion of 4 pins
  2203. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/HazardSimplePlugin_writeBackBuffer_payload_data[9]_i_1 into driver instance VexRiscv/dataCache_1/RegFilePlugin_regFile_reg_1_i_47, which resulted in an inversion of 4 pins
  2204. INFO: [Opt 31-1287] Pulled Inverter VexRiscv/dataCache_1/ways_0_data_symbol0_reg_i_2 into driver instance VexRiscv/dataCache_1/ways_0_data_symbol0_reg_i_18, which resulted in an inversion of 9 pins
  2205. INFO: [Opt 31-1287] Pulled Inverter basesoc_mmap_wishbone_dat_w[31]_i_1 into driver instance storage_14_reg_0_i_82, which resulted in an inversion of 535 pins
  2206. INFO: [Opt 31-1287] Pulled Inverter pcie_support/pcie_i/inst/inst/pcie_top_i/pcie_7x_i/pcie_block_i_i_17 into driver instance pcie_support/pcie_i_i_76, which resulted in an inversion of 1 pins
  2207. INFO: [Opt 31-138] Pushed 3 inverter(s) to 17 load pin(s).
  2208. INFO: [Opt 31-49] Retargeted 0 cell(s).
  2209. Phase 1 Retarget | Checksum: 1768802bf
  2210.  
  2211. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.46 . Memory (MB): peak = 3339.746 ; gain = 0.000 ; free physical = 1945 ; free virtual = 20833
  2212. INFO: [Opt 31-389] Phase Retarget created 2 cells and removed 88 cells
  2213. INFO: [Opt 31-1021] In phase Retarget, 5 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
  2214.  
  2215. Phase 2 Constant propagation
  2216. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  2217. Phase 2 Constant propagation | Checksum: 163614da5
  2218.  
  2219. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.57 . Memory (MB): peak = 3339.746 ; gain = 0.000 ; free physical = 1945 ; free virtual = 20833
  2220. INFO: [Opt 31-389] Phase Constant propagation created 79 cells and removed 117 cells
  2221. INFO: [Opt 31-1021] In phase Constant propagation, 2 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
  2222.  
  2223. Phase 3 Sweep
  2224. Phase 3 Sweep | Checksum: 17fd5f2a6
  2225.  
  2226. Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.91 . Memory (MB): peak = 3339.746 ; gain = 0.000 ; free physical = 1945 ; free virtual = 20833
  2227. INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 847 cells
  2228. INFO: [Opt 31-1021] In phase Sweep, 247 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
  2229.  
  2230. Phase 4 BUFG optimization
  2231. Phase 4 BUFG optimization | Checksum: 103fe7d40
  2232.  
  2233. Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3339.746 ; gain = 0.000 ; free physical = 1945 ; free virtual = 20832
  2234. INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
  2235. INFO: [Opt 31-1021] In phase BUFG optimization, 2 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
  2236.  
  2237. Phase 5 Shift Register Optimization
  2238. INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
  2239. Phase 5 Shift Register Optimization | Checksum: 103fe7d40
  2240.  
  2241. Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3339.746 ; gain = 0.000 ; free physical = 1944 ; free virtual = 20832
  2242. INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
  2243.  
  2244. Phase 6 Post Processing Netlist
  2245. Phase 6 Post Processing Netlist | Checksum: 17fd5f2a6
  2246.  
  2247. Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3339.746 ; gain = 0.000 ; free physical = 1944 ; free virtual = 20832
  2248. INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
  2249. INFO: [Opt 31-1021] In phase Post Processing Netlist, 3 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
  2250. Opt_design Change Summary
  2251. =========================
  2252.  
  2253.  
  2254. -------------------------------------------------------------------------------------------------------------------------
  2255. | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
  2256. -------------------------------------------------------------------------------------------------------------------------
  2257. | Retarget | 2 | 88 | 5 |
  2258. | Constant propagation | 79 | 117 | 2 |
  2259. | Sweep | 0 | 847 | 247 |
  2260. | BUFG optimization | 0 | 0 | 2 |
  2261. | Shift Register Optimization | 0 | 0 | 0 |
  2262. | Post Processing Netlist | 0 | 0 | 3 |
  2263. -------------------------------------------------------------------------------------------------------------------------
  2264.  
  2265.  
  2266.  
  2267. Starting Connectivity Check Task
  2268.  
  2269. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3339.746 ; gain = 0.000 ; free physical = 1944 ; free virtual = 20832
  2270. Ending Logic Optimization Task | Checksum: 252f58de8
  2271.  
  2272. Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3339.746 ; gain = 0.000 ; free physical = 1944 ; free virtual = 20832
  2273.  
  2274. Starting Power Optimization Task
  2275. INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
  2276. INFO: [Power 33-23] Power model is not available for STARTUPE2
  2277. INFO: [Timing 38-35] Done setting XDC timing constraints.
  2278. Running Vector-less Activity Propagation...
  2279.  
  2280. Finished Running Vector-less Activity Propagation
  2281. INFO: [Pwropt 34-9] Applying IDT optimizations ...
  2282. INFO: [Pwropt 34-10] Applying ODC optimizations ...
  2283.  
  2284.  
  2285. Starting PowerOpt Patch Enables Task
  2286. INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 48 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
  2287. INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
  2288. Number of BRAM Ports augmented: 11 newly gated: 1 Total Ports: 96
  2289. Ending PowerOpt Patch Enables Task | Checksum: 1a66aea93
  2290.  
  2291. Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.14 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2043 ; free virtual = 20934
  2292. Ending Power Optimization Task | Checksum: 1a66aea93
  2293.  
  2294. Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 3532.598 ; gain = 192.852 ; free physical = 2058 ; free virtual = 20949
  2295.  
  2296. Starting Final Cleanup Task
  2297. Ending Final Cleanup Task | Checksum: 1a66aea93
  2298.  
  2299. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2058 ; free virtual = 20949
  2300.  
  2301. Starting Netlist Obfuscation Task
  2302. Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2058 ; free virtual = 20949
  2303. Ending Netlist Obfuscation Task | Checksum: 1cd8aa7c8
  2304.  
  2305. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2058 ; free virtual = 20949
  2306. INFO: [Common 17-83] Releasing license: Implementation
  2307. 53 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
  2308. opt_design completed successfully
  2309. opt_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 3532.598 ; gain = 256.883 ; free physical = 2058 ; free virtual = 20949
  2310. # reset_property LOC [get_cells -hierarchical -filter {NAME=~pcie_support/*gtp_common.gtpe2_common_i}]
  2311. CRITICAL WARNING: [Constraints 18-4427] You are overriding a physical property set by a constraint that originated in a read only source. Your changes will not be saved with a project save. If you wish to make this change permanent, it is recommended you use an unmanaged Tcl file. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7-PCIE_X0Y0.xdc:99]
  2312. # reset_property LOC [get_cells -hierarchical -filter {NAME=~pcie_support/*genblk*.bram36_tdp_bl.bram36_tdp_bl}]
  2313. CRITICAL WARNING: [Constraints 18-4427] You are overriding a physical property set by a constraint that originated in a read only source. Your changes will not be saved with a project save. If you wish to make this change permanent, it is recommended you use an unmanaged Tcl file. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7-PCIE_X0Y0.xdc:114]
  2314. CRITICAL WARNING: [Constraints 18-4427] You are overriding a physical property set by a constraint that originated in a read only source. Your changes will not be saved with a project save. If you wish to make this change permanent, it is recommended you use an unmanaged Tcl file. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7-PCIE_X0Y0.xdc:113]
  2315. CRITICAL WARNING: [Constraints 18-4427] You are overriding a physical property set by a constraint that originated in a read only source. Your changes will not be saved with a project save. If you wish to make this change permanent, it is recommended you use an unmanaged Tcl file. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7-PCIE_X0Y0.xdc:112]
  2316. CRITICAL WARNING: [Constraints 18-4427] You are overriding a physical property set by a constraint that originated in a read only source. Your changes will not be saved with a project save. If you wish to make this change permanent, it is recommended you use an unmanaged Tcl file. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7-PCIE_X0Y0.xdc:111]
  2317. CRITICAL WARNING: [Constraints 18-4427] You are overriding a physical property set by a constraint that originated in a read only source. Your changes will not be saved with a project save. If you wish to make this change permanent, it is recommended you use an unmanaged Tcl file. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7-PCIE_X0Y0.xdc:115]
  2318. CRITICAL WARNING: [Constraints 18-4427] You are overriding a physical property set by a constraint that originated in a read only source. Your changes will not be saved with a project save. If you wish to make this change permanent, it is recommended you use an unmanaged Tcl file. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7-PCIE_X0Y0.xdc:116]
  2319. CRITICAL WARNING: [Constraints 18-4427] You are overriding a physical property set by a constraint that originated in a read only source. Your changes will not be saved with a project save. If you wish to make this change permanent, it is recommended you use an unmanaged Tcl file. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7-PCIE_X0Y0.xdc:117]
  2320. CRITICAL WARNING: [Constraints 18-4427] You are overriding a physical property set by a constraint that originated in a read only source. Your changes will not be saved with a project save. If you wish to make this change permanent, it is recommended you use an unmanaged Tcl file. [/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx.gen/sources_1/ip/pcie_s7/source/pcie_s7-PCIE_X0Y0.xdc:118]
  2321. # place_design -directive default
  2322. Command: place_design -directive default
  2323. Attempting to get a license for feature 'Implementation' and/or device 'xc7a50t'
  2324. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a50t'
  2325. INFO: [Timing 38-35] Done setting XDC timing constraints.
  2326. INFO: [DRC 23-27] Running DRC with 8 threads
  2327. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
  2328. INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
  2329. Running DRC as a precondition to command place_design
  2330. INFO: [DRC 23-27] Running DRC with 8 threads
  2331. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
  2332. INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
  2333.  
  2334. Starting Placer Task
  2335. INFO: [Place 46-5] The placer was invoked with the 'default' directive.
  2336. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
  2337.  
  2338. Phase 1 Placer Initialization
  2339.  
  2340. Phase 1.1 Placer Initialization Netlist Sorting
  2341. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2024 ; free virtual = 20915
  2342. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1ad99dfc9
  2343.  
  2344. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2024 ; free virtual = 20915
  2345. Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2024 ; free virtual = 20915
  2346.  
  2347. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
  2348. WARNING: [Place 30-568] A LUT 'pcie_clk_inst' is driving clock pin of 5121 registers. This could lead to large hold time violations. First few involved registers are:
  2349. s7pciephy_rx_datapath_pipe_ready_sink_d_payload_dat_reg[63] {FDRE}
  2350. VexRiscv/execute_to_memory_INSTRUCTION_reg[9] {FDRE}
  2351. basesoc_reader_data_fifo_level0_reg[5] {FDRE}
  2352. basesoc_reader_data_fifo_level0_reg[4] {FDRE}
  2353. storage_6_reg_0_63_51_53/RAMC {RAMD64E}
  2354. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 13a55bad7
  2355.  
  2356. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.46 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2044 ; free virtual = 20935
  2357.  
  2358. Phase 1.3 Build Placer Netlist Model
  2359. Phase 1.3 Build Placer Netlist Model | Checksum: 19ec25aba
  2360.  
  2361. Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2034 ; free virtual = 20926
  2362.  
  2363. Phase 1.4 Constrain Clocks/Macros
  2364. Phase 1.4 Constrain Clocks/Macros | Checksum: 19ec25aba
  2365.  
  2366. Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2034 ; free virtual = 20926
  2367. Phase 1 Placer Initialization | Checksum: 19ec25aba
  2368.  
  2369. Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2034 ; free virtual = 20925
  2370.  
  2371. Phase 2 Global Placement
  2372.  
  2373. Phase 2.1 Floorplanning
  2374. Phase 2.1 Floorplanning | Checksum: 20066eb94
  2375.  
  2376. Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2018 ; free virtual = 20909
  2377.  
  2378. Phase 2.2 Update Timing before SLR Path Opt
  2379. Phase 2.2 Update Timing before SLR Path Opt | Checksum: 17f9485a9
  2380.  
  2381. Time (s): cpu = 00:00:09 ; elapsed = 00:00:03 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2032 ; free virtual = 20923
  2382.  
  2383. Phase 2.3 Post-Processing in Floorplanning
  2384. Phase 2.3 Post-Processing in Floorplanning | Checksum: 185e7afc1
  2385.  
  2386. Time (s): cpu = 00:00:09 ; elapsed = 00:00:03 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2075 ; free virtual = 20966
  2387.  
  2388. Phase 2.4 Global Placement Core
  2389.  
  2390. Phase 2.4.1 Physical Synthesis In Placer
  2391. INFO: [Physopt 32-1035] Found 8 LUTNM shape to break, 1543 LUT instances to create LUTNM shape
  2392. INFO: [Physopt 32-1044] Break lutnm for timing: one critical 8, two critical 0, total 8, new lutff created 0
  2393. INFO: [Physopt 32-1138] End 1 Pass. Optimized 711 nets or LUTs. Breaked 8 LUTs, combined 703 existing LUTs and moved 0 existing LUT
  2394. INFO: [Physopt 32-65] No nets found for high-fanout optimization.
  2395. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
  2396. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
  2397. INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
  2398. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
  2399. INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization
  2400. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
  2401. INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
  2402. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
  2403. INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
  2404. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
  2405. INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
  2406. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
  2407. INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
  2408. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
  2409. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2086 ; free virtual = 20977
  2410.  
  2411. Summary of Physical Synthesis Optimizations
  2412. ============================================
  2413.  
  2414.  
  2415. -----------------------------------------------------------------------------------------------------------------------------------------------------------
  2416. | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
  2417. -----------------------------------------------------------------------------------------------------------------------------------------------------------
  2418. | LUT Combining | 8 | 703 | 711 | 0 | 1 | 00:00:01 |
  2419. | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
  2420. | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
  2421. | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
  2422. | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
  2423. | Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
  2424. | BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
  2425. | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
  2426. | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
  2427. | Total | 8 | 703 | 711 | 0 | 9 | 00:00:01 |
  2428. -----------------------------------------------------------------------------------------------------------------------------------------------------------
  2429.  
  2430.  
  2431. Phase 2.4.1 Physical Synthesis In Placer | Checksum: 57a5b34d
  2432.  
  2433. Time (s): cpu = 00:00:34 ; elapsed = 00:00:10 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2086 ; free virtual = 20977
  2434. Phase 2.4 Global Placement Core | Checksum: f509bb7c
  2435.  
  2436. Time (s): cpu = 00:00:35 ; elapsed = 00:00:10 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2085 ; free virtual = 20977
  2437. Phase 2 Global Placement | Checksum: f509bb7c
  2438.  
  2439. Time (s): cpu = 00:00:35 ; elapsed = 00:00:10 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2091 ; free virtual = 20983
  2440.  
  2441. Phase 3 Detail Placement
  2442.  
  2443. Phase 3.1 Commit Multi Column Macros
  2444. Phase 3.1 Commit Multi Column Macros | Checksum: 334010d9
  2445.  
  2446. Time (s): cpu = 00:00:37 ; elapsed = 00:00:10 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2091 ; free virtual = 20982
  2447.  
  2448. Phase 3.2 Commit Most Macros & LUTRAMs
  2449. Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b7df9033
  2450.  
  2451. Time (s): cpu = 00:00:40 ; elapsed = 00:00:11 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2091 ; free virtual = 20982
  2452.  
  2453. Phase 3.3 Area Swap Optimization
  2454. Phase 3.3 Area Swap Optimization | Checksum: 1741ca41a
  2455.  
  2456. Time (s): cpu = 00:00:40 ; elapsed = 00:00:11 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2091 ; free virtual = 20982
  2457.  
  2458. Phase 3.4 Pipeline Register Optimization
  2459. Phase 3.4 Pipeline Register Optimization | Checksum: c31426f4
  2460.  
  2461. Time (s): cpu = 00:00:40 ; elapsed = 00:00:11 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2091 ; free virtual = 20982
  2462.  
  2463. Phase 3.5 Fast Optimization
  2464. Phase 3.5 Fast Optimization | Checksum: bdeb5b5f
  2465.  
  2466. Time (s): cpu = 00:00:43 ; elapsed = 00:00:12 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2089 ; free virtual = 20980
  2467.  
  2468. Phase 3.6 Small Shape Detail Placement
  2469. Phase 3.6 Small Shape Detail Placement | Checksum: 17dc02e01
  2470.  
  2471. Time (s): cpu = 00:00:46 ; elapsed = 00:00:14 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2028 ; free virtual = 20919
  2472.  
  2473. Phase 3.7 Re-assign LUT pins
  2474. Phase 3.7 Re-assign LUT pins | Checksum: 13105e006
  2475.  
  2476. Time (s): cpu = 00:00:46 ; elapsed = 00:00:15 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2028 ; free virtual = 20919
  2477.  
  2478. Phase 3.8 Pipeline Register Optimization
  2479. Phase 3.8 Pipeline Register Optimization | Checksum: 17db4d034
  2480.  
  2481. Time (s): cpu = 00:00:46 ; elapsed = 00:00:15 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2028 ; free virtual = 20919
  2482.  
  2483. Phase 3.9 Fast Optimization
  2484. Phase 3.9 Fast Optimization | Checksum: 135c8ef96
  2485.  
  2486. Time (s): cpu = 00:00:51 ; elapsed = 00:00:16 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2028 ; free virtual = 20919
  2487. Phase 3 Detail Placement | Checksum: 135c8ef96
  2488.  
  2489. Time (s): cpu = 00:00:52 ; elapsed = 00:00:16 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2028 ; free virtual = 20919
  2490.  
  2491. Phase 4 Post Placement Optimization and Clean-Up
  2492.  
  2493. Phase 4.1 Post Commit Optimization
  2494. INFO: [Timing 38-35] Done setting XDC timing constraints.
  2495.  
  2496. Phase 4.1.1 Post Placement Optimization
  2497. Post Placement Optimization Initialization | Checksum: 2513fa160
  2498.  
  2499. Phase 4.1.1.1 BUFG Insertion
  2500.  
  2501. Starting Physical Synthesis Task
  2502.  
  2503. Phase 1 Physical Synthesis Initialization
  2504. INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
  2505. INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-2.057 | TNS=-43.980 |
  2506. Phase 1 Physical Synthesis Initialization | Checksum: 1e7f96e26
  2507.  
  2508. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.24 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2021 ; free virtual = 20912
  2509. INFO: [Place 46-33] Processed net pcie_support/pcie_i/inst/inst/user_reset_out, BUFG insertion was skipped due to placement/routing conflicts.
  2510. INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0.
  2511. Ending Physical Synthesis Task | Checksum: 1ac877d63
  2512.  
  2513. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.43 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2022 ; free virtual = 20913
  2514. Phase 4.1.1.1 BUFG Insertion | Checksum: 2513fa160
  2515.  
  2516. Time (s): cpu = 00:00:58 ; elapsed = 00:00:18 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2022 ; free virtual = 20913
  2517.  
  2518. Phase 4.1.1.2 Post Placement Timing Optimization
  2519. INFO: [Place 30-746] Post Placement Timing Summary WNS=-1.716. For the most accurate timing information please run report_timing.
  2520. Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: dc534d46
  2521.  
  2522. Time (s): cpu = 00:01:10 ; elapsed = 00:00:30 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2063 ; free virtual = 20962
  2523.  
  2524. Time (s): cpu = 00:01:10 ; elapsed = 00:00:30 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2063 ; free virtual = 20962
  2525. Phase 4.1 Post Commit Optimization | Checksum: dc534d46
  2526.  
  2527. Time (s): cpu = 00:01:10 ; elapsed = 00:00:30 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2070 ; free virtual = 20969
  2528.  
  2529. Phase 4.2 Post Placement Cleanup
  2530. Phase 4.2 Post Placement Cleanup | Checksum: dc534d46
  2531.  
  2532. Time (s): cpu = 00:01:11 ; elapsed = 00:00:30 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2072 ; free virtual = 20971
  2533.  
  2534. Phase 4.3 Placer Reporting
  2535.  
  2536. Phase 4.3.1 Print Estimated Congestion
  2537. INFO: [Place 30-612] Post-Placement Estimated Congestion
  2538. ____________________________________________________
  2539. | | Global Congestion | Short Congestion |
  2540. | Direction | Region Size | Region Size |
  2541. |___________|___________________|___________________|
  2542. | North| 1x1| 4x4|
  2543. |___________|___________________|___________________|
  2544. | South| 1x1| 1x1|
  2545. |___________|___________________|___________________|
  2546. | East| 1x1| 2x2|
  2547. |___________|___________________|___________________|
  2548. | West| 1x1| 1x1|
  2549. |___________|___________________|___________________|
  2550.  
  2551. Phase 4.3.1 Print Estimated Congestion | Checksum: dc534d46
  2552.  
  2553. Time (s): cpu = 00:01:11 ; elapsed = 00:00:30 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2073 ; free virtual = 20972
  2554. Phase 4.3 Placer Reporting | Checksum: dc534d46
  2555.  
  2556. Time (s): cpu = 00:01:11 ; elapsed = 00:00:30 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2073 ; free virtual = 20972
  2557.  
  2558. Phase 4.4 Final Placement Cleanup
  2559. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2073 ; free virtual = 20972
  2560.  
  2561. Time (s): cpu = 00:01:11 ; elapsed = 00:00:30 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2073 ; free virtual = 20972
  2562. Phase 4 Post Placement Optimization and Clean-Up | Checksum: 59786392
  2563.  
  2564. Time (s): cpu = 00:01:11 ; elapsed = 00:00:30 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2073 ; free virtual = 20971
  2565. Ending Placer Task | Checksum: 53d506cd
  2566.  
  2567. Time (s): cpu = 00:01:11 ; elapsed = 00:00:30 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2073 ; free virtual = 20971
  2568. INFO: [Common 17-83] Releasing license: Implementation
  2569. 36 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
  2570. place_design completed successfully
  2571. place_design: Time (s): cpu = 00:01:16 ; elapsed = 00:00:32 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2088 ; free virtual = 20987
  2572. # report_utilization -hierarchical -file fairwaves_xtrx_utilization_hierarchical_place.rpt
  2573. # report_utilization -file fairwaves_xtrx_utilization_place.rpt
  2574. # report_io -file fairwaves_xtrx_io.rpt
  2575. report_io: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2074 ; free virtual = 20976
  2576. # report_control_sets -verbose -file fairwaves_xtrx_control_sets.rpt
  2577. report_control_sets: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 2076 ; free virtual = 20978
  2578. # report_clock_utilization -file fairwaves_xtrx_clock_utilization.rpt
  2579. # route_design -directive default
  2580. Command: route_design -directive default
  2581. Attempting to get a license for feature 'Implementation' and/or device 'xc7a50t'
  2582. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a50t'
  2583. Running DRC as a precondition to command route_design
  2584. INFO: [DRC 23-27] Running DRC with 8 threads
  2585. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
  2586. INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
  2587.  
  2588.  
  2589. Starting Routing Task
  2590. INFO: [Route 35-270] Using Router directive 'default'.
  2591. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
  2592.  
  2593. Phase 1 Build RT Design
  2594. Checksum: PlaceDB: 358d1768 ConstDB: 0 ShapeSum: 1e47ef65 RouteDB: 0
  2595. Post Restoration Checksum: NetGraph: 9bea3467 NumContArr: 6d9c144b Constraints: 0 Timing: 0
  2596. Phase 1 Build RT Design | Checksum: 1098648b2
  2597.  
  2598. Time (s): cpu = 00:00:14 ; elapsed = 00:00:10 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1943 ; free virtual = 20856
  2599.  
  2600. Phase 2 Router Initialization
  2601.  
  2602. Phase 2.1 Create Timer
  2603. Phase 2.1 Create Timer | Checksum: 1098648b2
  2604.  
  2605. Time (s): cpu = 00:00:14 ; elapsed = 00:00:11 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1943 ; free virtual = 20856
  2606.  
  2607. Phase 2.2 Fix Topology Constraints
  2608. Phase 2.2 Fix Topology Constraints | Checksum: 1098648b2
  2609.  
  2610. Time (s): cpu = 00:00:14 ; elapsed = 00:00:11 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1911 ; free virtual = 20824
  2611.  
  2612. Phase 2.3 Pre Route Cleanup
  2613. Phase 2.3 Pre Route Cleanup | Checksum: 1098648b2
  2614.  
  2615. Time (s): cpu = 00:00:14 ; elapsed = 00:00:11 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1911 ; free virtual = 20824
  2616. Number of Nodes with overlaps = 0
  2617.  
  2618. Phase 2.4 Update Timing
  2619. Phase 2.4 Update Timing | Checksum: 1ccb71cd0
  2620.  
  2621. Time (s): cpu = 00:00:21 ; elapsed = 00:00:14 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1824 ; free virtual = 20737
  2622. INFO: [Route 35-416] Intermediate Timing Summary | WNS=-2.532 | TNS=-66.012| WHS=-3.306 | THS=-6514.396|
  2623.  
  2624.  
  2625. Router Utilization Summary
  2626. Global Vertical Routing Utilization = 0.246751 %
  2627. Global Horizontal Routing Utilization = 0.320666 %
  2628. Routable Net Status*
  2629. *Does not include unroutable nets such as driverless and loadless.
  2630. Run report_route_status for detailed report.
  2631. Number of Failed Nets = 11924
  2632. (Failed Nets is the sum of unrouted and partially routed nets)
  2633. Number of Unrouted Nets = 11924
  2634. Number of Partially Routed Nets = 0
  2635. Number of Node Overlaps = 2
  2636.  
  2637. Phase 2 Router Initialization | Checksum: fde9a75d
  2638.  
  2639. Time (s): cpu = 00:00:25 ; elapsed = 00:00:15 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1828 ; free virtual = 20741
  2640.  
  2641. Phase 3 Initial Routing
  2642.  
  2643. Phase 3.1 Global Routing
  2644. Phase 3.1 Global Routing | Checksum: fde9a75d
  2645.  
  2646. Time (s): cpu = 00:00:25 ; elapsed = 00:00:15 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1828 ; free virtual = 20741
  2647. Phase 3 Initial Routing | Checksum: 102fad485
  2648.  
  2649. Time (s): cpu = 00:00:45 ; elapsed = 00:00:19 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1814 ; free virtual = 20728
  2650. INFO: [Route 35-580] Design has 259 pins with tight setup and hold constraints.
  2651.  
  2652. The top 5 pins with tight setup and hold constraints:
  2653.  
  2654. +==============+===============+==============================+
  2655. | Launch Clock | Capture Clock | Pin |
  2656. +==============+===============+==============================+
  2657. | userclk1 | userclk1 | icap_data_storage_reg[24]/D |
  2658. | userclk1 | userclk1 | icap_data_storage_reg[11]/D |
  2659. | userclk1 | userclk1 | icap_data_storage_reg[5]/CE |
  2660. | userclk1 | userclk1 | icap_data_storage_reg[11]/CE |
  2661. | userclk1 | userclk1 | icap_data_storage_reg[14]/CE |
  2662. +--------------+---------------+------------------------------+
  2663.  
  2664. File with complete list of pins: tight_setup_hold_pins.txt
  2665.  
  2666.  
  2667. Phase 4 Rip-up And Reroute
  2668.  
  2669. Phase 4.1 Global Iteration 0
  2670. Number of Nodes with overlaps = 2130
  2671. Number of Nodes with overlaps = 194
  2672. Number of Nodes with overlaps = 44
  2673. Number of Nodes with overlaps = 16
  2674. Number of Nodes with overlaps = 3
  2675. Number of Nodes with overlaps = 1
  2676. Number of Nodes with overlaps = 0
  2677. INFO: [Route 35-416] Intermediate Timing Summary | WNS=-2.633 | TNS=-172.836| WHS=N/A | THS=N/A |
  2678.  
  2679. Phase 4.1 Global Iteration 0 | Checksum: 2a0df250f
  2680.  
  2681. Time (s): cpu = 00:08:58 ; elapsed = 00:02:58 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1835 ; free virtual = 20747
  2682.  
  2683. Phase 4.2 Global Iteration 1
  2684. Number of Nodes with overlaps = 30
  2685. Number of Nodes with overlaps = 18
  2686. Number of Nodes with overlaps = 9
  2687. Number of Nodes with overlaps = 6
  2688. Number of Nodes with overlaps = 1
  2689. Number of Nodes with overlaps = 0
  2690. INFO: [Route 35-416] Intermediate Timing Summary | WNS=-2.466 | TNS=-181.373| WHS=N/A | THS=N/A |
  2691.  
  2692. Phase 4.2 Global Iteration 1 | Checksum: 11a785778
  2693.  
  2694. Time (s): cpu = 00:09:02 ; elapsed = 00:03:01 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1836 ; free virtual = 20748
  2695.  
  2696. Phase 4.3 Global Iteration 2
  2697. Number of Nodes with overlaps = 3
  2698. Number of Nodes with overlaps = 1
  2699. Number of Nodes with overlaps = 0
  2700. INFO: [Route 35-416] Intermediate Timing Summary | WNS=-2.339 | TNS=-167.734| WHS=N/A | THS=N/A |
  2701.  
  2702. Phase 4.3 Global Iteration 2 | Checksum: 1a8d139d1
  2703.  
  2704. Time (s): cpu = 00:09:03 ; elapsed = 00:03:02 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1838 ; free virtual = 20750
  2705. Phase 4 Rip-up And Reroute | Checksum: 1a8d139d1
  2706.  
  2707. Time (s): cpu = 00:09:03 ; elapsed = 00:03:02 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1838 ; free virtual = 20750
  2708.  
  2709. Phase 5 Delay and Skew Optimization
  2710.  
  2711. Phase 5.1 Delay CleanUp
  2712.  
  2713. Phase 5.1.1 Update Timing
  2714. Phase 5.1.1 Update Timing | Checksum: 1b83e709b
  2715.  
  2716. Time (s): cpu = 00:09:04 ; elapsed = 00:03:02 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1838 ; free virtual = 20750
  2717. INFO: [Route 35-416] Intermediate Timing Summary | WNS=-2.339 | TNS=-167.734| WHS=N/A | THS=N/A |
  2718.  
  2719. Number of Nodes with overlaps = 0
  2720. Phase 5.1 Delay CleanUp | Checksum: 219ad642c
  2721.  
  2722. Time (s): cpu = 00:09:06 ; elapsed = 00:03:03 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1815 ; free virtual = 20727
  2723.  
  2724. Phase 5.2 Clock Skew Optimization
  2725. Phase 5.2 Clock Skew Optimization | Checksum: 219ad642c
  2726.  
  2727. Time (s): cpu = 00:09:06 ; elapsed = 00:03:03 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1815 ; free virtual = 20727
  2728. Phase 5 Delay and Skew Optimization | Checksum: 219ad642c
  2729.  
  2730. Time (s): cpu = 00:09:06 ; elapsed = 00:03:03 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1815 ; free virtual = 20727
  2731.  
  2732. Phase 6 Post Hold Fix
  2733.  
  2734. Phase 6.1 Hold Fix Iter
  2735.  
  2736. Phase 6.1.1 Update Timing
  2737. Phase 6.1.1 Update Timing | Checksum: 1bb25eed6
  2738.  
  2739. Time (s): cpu = 00:09:07 ; elapsed = 00:03:03 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1813 ; free virtual = 20725
  2740. INFO: [Route 35-416] Intermediate Timing Summary | WNS=-2.339 | TNS=-149.668| WHS=-0.732 | THS=-6.410 |
  2741.  
  2742. Phase 6.1 Hold Fix Iter | Checksum: 25d5e908c
  2743.  
  2744. Time (s): cpu = 00:09:07 ; elapsed = 00:03:03 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1813 ; free virtual = 20725
  2745. WARNING: [Route 35-468] The router encountered 23 pins that are both setup-critical and hold-critical and tried to fix hold violations at the expense of setup slack. Such pins are:
  2746. icap_data_storage_reg[0]/CE
  2747. icap_data_storage_reg[10]/CE
  2748. icap_data_storage_reg[11]/CE
  2749. icap_data_storage_reg[12]/CE
  2750. icap_data_storage_reg[13]/CE
  2751. icap_data_storage_reg[14]/CE
  2752. icap_data_storage_reg[15]/CE
  2753. icap_data_storage_reg[16]/CE
  2754. icap_data_storage_reg[17]/CE
  2755. icap_data_storage_reg[18]/CE
  2756. .. and 13 more pins.
  2757.  
  2758. Phase 6 Post Hold Fix | Checksum: 21ed3f27d
  2759.  
  2760. Time (s): cpu = 00:09:07 ; elapsed = 00:03:03 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1813 ; free virtual = 20725
  2761.  
  2762. Phase 7 Route finalize
  2763.  
  2764. Router Utilization Summary
  2765. Global Vertical Routing Utilization = 12.3569 %
  2766. Global Horizontal Routing Utilization = 12.43 %
  2767. Routable Net Status*
  2768. *Does not include unroutable nets such as driverless and loadless.
  2769. Run report_route_status for detailed report.
  2770. Number of Failed Nets = 0
  2771. (Failed Nets is the sum of unrouted and partially routed nets)
  2772. Number of Unrouted Nets = 0
  2773. Number of Partially Routed Nets = 0
  2774. Number of Node Overlaps = 0
  2775.  
  2776. Congestion Report
  2777. North Dir 1x1 Area, Max Cong = 84.6847%, No Congested Regions.
  2778. South Dir 1x1 Area, Max Cong = 89.1892%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile):
  2779. INT_L_X28Y86 -> INT_L_X28Y86
  2780. East Dir 1x1 Area, Max Cong = 83.8235%, No Congested Regions.
  2781. West Dir 1x1 Area, Max Cong = 82.3529%, No Congested Regions.
  2782.  
  2783. ------------------------------
  2784. Reporting congestion hotspots
  2785. ------------------------------
  2786. Direction: North
  2787. ----------------
  2788. Congested clusters found at Level 0
  2789. Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
  2790. Direction: South
  2791. ----------------
  2792. Congested clusters found at Level 0
  2793. Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 1
  2794. Direction: East
  2795. ----------------
  2796. Congested clusters found at Level 0
  2797. Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
  2798. Direction: West
  2799. ----------------
  2800. Congested clusters found at Level 0
  2801. Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
  2802.  
  2803. Phase 7 Route finalize | Checksum: 2653db834
  2804.  
  2805. Time (s): cpu = 00:09:08 ; elapsed = 00:03:03 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1813 ; free virtual = 20725
  2806.  
  2807. Phase 8 Verifying routed nets
  2808.  
  2809. Verification completed successfully
  2810. Phase 8 Verifying routed nets | Checksum: 2653db834
  2811.  
  2812. Time (s): cpu = 00:09:08 ; elapsed = 00:03:03 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1812 ; free virtual = 20724
  2813.  
  2814. Phase 9 Depositing Routes
  2815. Phase 9 Depositing Routes | Checksum: 1d71810ea
  2816.  
  2817. Time (s): cpu = 00:09:09 ; elapsed = 00:03:04 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1812 ; free virtual = 20724
  2818.  
  2819. Phase 10 Post Router Timing
  2820.  
  2821. Phase 10.1 Update Timing
  2822. Phase 10.1 Update Timing | Checksum: 1ae39c151
  2823.  
  2824. Time (s): cpu = 00:09:10 ; elapsed = 00:03:05 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1812 ; free virtual = 20724
  2825. INFO: [Route 35-57] Estimated Timing Summary | WNS=-2.339 | TNS=-149.668| WHS=0.018 | THS=0.000 |
  2826.  
  2827. WARNING: [Route 35-328] Router estimated timing not met.
  2828. Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design.
  2829. Phase 10 Post Router Timing | Checksum: 1ae39c151
  2830.  
  2831. Time (s): cpu = 00:09:10 ; elapsed = 00:03:05 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1812 ; free virtual = 20724
  2832. INFO: [Route 35-16] Router Completed Successfully
  2833.  
  2834. Time (s): cpu = 00:09:10 ; elapsed = 00:03:05 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1895 ; free virtual = 20807
  2835.  
  2836. Routing Is Done.
  2837. INFO: [Common 17-83] Releasing license: Implementation
  2838. 16 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
  2839. route_design completed successfully
  2840. route_design: Time (s): cpu = 00:09:16 ; elapsed = 00:03:06 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1895 ; free virtual = 20807
  2841. # phys_opt_design -directive default
  2842. Command: phys_opt_design -directive default
  2843. Attempting to get a license for feature 'Implementation' and/or device 'xc7a50t'
  2844. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a50t'
  2845. INFO: [Vivado_Tcl 4-241] Physical synthesis in post route mode ( 100.0% nets are fully routed)
  2846. INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: default
  2847. INFO: [Vivado_Tcl 4-1435] PhysOpt_Tcl_Interface Runtime Before Starting Physical Synthesis Task | CPU: 5.39s | WALL: 1.14s
  2848. Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1899 ; free virtual = 20811
  2849.  
  2850. Starting Physical Synthesis Task
  2851.  
  2852. Phase 1 Physical Synthesis Initialization
  2853. INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
  2854. INFO: [Physopt 32-668] Current Timing Summary | WNS=-2.338 | TNS=-146.101 | WHS=0.018 | THS=0.000 |
  2855. Phase 1 Physical Synthesis Initialization | Checksum: 20f04ee07
  2856.  
  2857. Time (s): cpu = 00:00:06 ; elapsed = 00:00:01 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1891 ; free virtual = 20803
  2858. WARNING: [Physopt 32-745] Physical Optimization has determined that the magnitude of the negative slack is too large and it is highly unlikely that slack will be improved. Post-Route Physical Optimization is most effective when WNS is above -0.5ns
  2859.  
  2860. Phase 2 Critical Path Optimization
  2861. INFO: [Physopt 32-668] Current Timing Summary | WNS=-2.338 | TNS=-146.101 | WHS=0.018 | THS=0.000 |
  2862. INFO: [Physopt 32-953] Path group WNS did not improve. Path group: icap_clk. Processed net: icap_o_icape2[0].
  2863. INFO: [Physopt 32-953] Path group WNS did not improve. Path group: icap_clk. Processed net: pcie_support/pipe_clock_i/userclk1.
  2864. INFO: [Physopt 32-953] Path group WNS did not improve. Path group: icap_clk. Processed net: ICAPE2_i_45_n_0.
  2865. INFO: [Physopt 32-953] Path group WNS did not improve. Path group: icap_clk. Processed net: icap__i[14].
  2866. INFO: [Physopt 32-953] Path group WNS did not improve. Path group: icap_clk. Processed net: icap_addr_storage[1].
  2867. INFO: [Physopt 32-663] Processed net icap_data_storage[14]. Re-placed instance icap_data_storage_reg[14]
  2868. INFO: [Physopt 32-952] Improved path group WNS = -2.002. Path group: userclk1. Processed net: icap_data_storage[14].
  2869. INFO: [Physopt 32-663] Processed net icap_data_storage[19]. Re-placed instance icap_data_storage_reg[19]
  2870. INFO: [Physopt 32-952] Improved path group WNS = -1.980. Path group: userclk1. Processed net: icap_data_storage[19].
  2871. INFO: [Physopt 32-953] Path group WNS did not improve. Path group: userclk1. Processed net: icap_data_storage[31].
  2872. INFO: [Physopt 32-663] Processed net VexRiscv/IBusCachedPlugin_cache/basesoc_writer_value_storage[57]_i_2_n_0. Re-placed instance VexRiscv/IBusCachedPlugin_cache/basesoc_writer_value_storage[57]_i_2
  2873. INFO: [Physopt 32-952] Improved path group WNS = -1.698. Path group: userclk1. Processed net: VexRiscv/IBusCachedPlugin_cache/basesoc_writer_value_storage[57]_i_2_n_0.
  2874. INFO: [Physopt 32-953] Path group WNS did not improve. Path group: userclk1. Processed net: VexRiscv/IBusCachedPlugin_cache/basesoc_writer_value_storage[57]_i_2_n_0.
  2875. INFO: [Physopt 32-710] Processed net VexRiscv/IBusCachedPlugin_cache/basesoc_writer_value_storage[57]_i_2_n_0. Critical path length was reduced through logic transformation on cell VexRiscv/IBusCachedPlugin_cache/basesoc_writer_value_storage[57]_i_2_comp.
  2876. INFO: [Physopt 32-952] Improved path group WNS = -1.456. Path group: userclk1. Processed net: VexRiscv/IBusCachedPlugin_cache/basesoc_reader_value_storage[57]_i_5_n_0.
  2877. INFO: [Physopt 32-953] Path group WNS did not improve. Path group: userclk1. Processed net: basesoc_csr_bankarray_interface3_bank_bus_dat_r[0].
  2878. INFO: [Physopt 32-663] Processed net VexRiscv/IBusCachedPlugin_cache/basesoc_csr_bankarray_interface3_bank_bus_dat_r[0]_i_4_n_0. Re-placed instance VexRiscv/IBusCachedPlugin_cache/basesoc_csr_bankarray_interface3_bank_bus_dat_r[0]_i_4
  2879. INFO: [Physopt 32-952] Improved path group WNS = -1.297. Path group: userclk1. Processed net: VexRiscv/IBusCachedPlugin_cache/basesoc_csr_bankarray_interface3_bank_bus_dat_r[0]_i_4_n_0.
  2880. INFO: [Physopt 32-953] Path group WNS did not improve. Path group: userclk1. Processed net: icap_data_storage[17].
  2881. INFO: [Physopt 32-710] Processed net VexRiscv/IBusCachedPlugin_cache/basesoc_writer_value_storage[57]_i_2_n_0. Critical path length was reduced through logic transformation on cell VexRiscv/IBusCachedPlugin_cache/basesoc_writer_value_storage[57]_i_2_comp_1.
  2882. INFO: [Physopt 32-952] Improved path group WNS = -0.978. Path group: userclk1. Processed net: VexRiscv/IBusCachedPlugin_cache/basesoc_writer_value_storage[31]_i_3_n_0.
  2883. INFO: [Physopt 32-710] Processed net VexRiscv/IBusCachedPlugin_cache/basesoc_writer_value_storage[57]_i_2_n_0. Critical path length was reduced through logic transformation on cell VexRiscv/IBusCachedPlugin_cache/basesoc_writer_value_storage[57]_i_2_comp.
  2884. INFO: [Physopt 32-952] Improved path group WNS = -0.792. Path group: userclk1. Processed net: VexRiscv/IBusCachedPlugin_cache/basesoc_state_reg_0.
  2885. INFO: [Physopt 32-953] Path group WNS did not improve. Path group: userclk1. Processed net: VexRiscv/IBusCachedPlugin_cache/dataCache_1_io_mem_cmd_s2mPipe_rData_address_reg[14].
  2886. INFO: [Physopt 32-710] Processed net VexRiscv/IBusCachedPlugin_cache/dataCache_1_io_mem_cmd_s2mPipe_rData_address_reg[14]. Critical path length was reduced through logic transformation on cell VexRiscv/IBusCachedPlugin_cache/basesoc_csr_bankarray_interface3_bank_bus_dat_r[31]_i_1_comp.
  2887. INFO: [Physopt 32-952] Improved path group WNS = -0.767. Path group: userclk1. Processed net: VexRiscv/IBusCachedPlugin_cache/basesoc_csr_bankarray_interface3_bank_bus_dat_r[31]_i_3_n_0.
  2888. INFO: [Physopt 32-710] Processed net VexRiscv/IBusCachedPlugin_cache/basesoc_writer_value_storage[57]_i_2_n_0. Critical path length was reduced through logic transformation on cell VexRiscv/IBusCachedPlugin_cache/basesoc_writer_value_storage[57]_i_2_comp_2.
  2889. INFO: [Physopt 32-952] Improved path group WNS = -0.673. Path group: userclk1. Processed net: VexRiscv/IBusCachedPlugin_cache/basesoc_reader_value_storage[57]_i_4_n_0.
  2890. INFO: [Physopt 32-663] Processed net VexRiscv/comb_array_muxed0[0]. Re-placed instance VexRiscv/mem_1_reg_0_i_11
  2891. INFO: [Physopt 32-952] Improved path group WNS = -0.544. Path group: userclk1. Processed net: VexRiscv/comb_array_muxed0[0].
  2892. INFO: [Physopt 32-953] Path group WNS did not improve. Path group: clk_250mhz. Processed net: pcie_support/pipe_clock_i/pclk_sel.
  2893. INFO: [Physopt 32-663] Processed net VexRiscv/IBusCachedPlugin_cache/flash_mosi_storage[39]_i_2_n_0. Re-placed instance VexRiscv/IBusCachedPlugin_cache/flash_mosi_storage[39]_i_2
  2894. INFO: [Physopt 32-952] Improved path group WNS = -0.461. Path group: userclk1. Processed net: VexRiscv/IBusCachedPlugin_cache/flash_mosi_storage[39]_i_2_n_0.
  2895. INFO: [Physopt 32-953] Path group WNS did not improve. Path group: userclk1. Processed net: icap_addr_storage[2].
  2896. INFO: [Physopt 32-953] Path group WNS did not improve. Path group: userclk1. Processed net: VexRiscv/IBusCachedPlugin_cache/flash_control_storage[15]_i_2_n_0.
  2897. INFO: [Physopt 32-663] Processed net VexRiscv/IBusCachedPlugin_cache/basesoc_csr_bankarray_interface1_bank_bus_dat_r[15]_i_2_n_0. Re-placed instance VexRiscv/IBusCachedPlugin_cache/basesoc_csr_bankarray_interface1_bank_bus_dat_r[15]_i_2
  2898. INFO: [Physopt 32-952] Improved path group WNS = -0.429. Path group: userclk1. Processed net: VexRiscv/IBusCachedPlugin_cache/basesoc_csr_bankarray_interface1_bank_bus_dat_r[15]_i_2_n_0.
  2899. INFO: [Physopt 32-953] Path group WNS did not improve. Path group: userclk1. Processed net: VexRiscv/IBusCachedPlugin_cache/basesoc_reader_value_storage[57]_i_4_n_0_repN_1.
  2900. INFO: [Physopt 32-710] Processed net VexRiscv/IBusCachedPlugin_cache/basesoc_reader_value_storage[57]_i_4_n_0_repN_1. Critical path length was reduced through logic transformation on cell VexRiscv/IBusCachedPlugin_cache/basesoc_reader_value_storage[57]_i_4_comp_2.
  2901. INFO: [Physopt 32-952] Improved path group WNS = -0.415. Path group: userclk1. Processed net: VexRiscv/IBusCachedPlugin_cache/mem_2_adr0[2]_i_2_n_0.
  2902. INFO: [Physopt 32-953] Path group WNS did not improve. Path group: userclk1. Processed net: basesoc_writer_index_reg[0].
  2903. INFO: [Physopt 32-953] Path group WNS did not improve. Path group: userclk1. Processed net: basesoc_writer_table_do_read.
  2904. INFO: [Physopt 32-710] Processed net basesoc_writer_table_do_read. Critical path length was reduced through logic transformation on cell basesoc_writer_index[0]_i_2_comp.
  2905. INFO: [Physopt 32-952] Improved path group WNS = -0.411. Path group: userclk1. Processed net: basesoc_writer_index[0]_i_4_n_0.
  2906. INFO: [Physopt 32-953] Path group WNS did not improve. Path group: userclk1. Processed net: VexRiscv/IBusCachedPlugin_cache/mem_1_reg_0_i_33_n_0.
  2907. INFO: [Physopt 32-710] Processed net VexRiscv/IBusCachedPlugin_cache/mem_1_reg_0_i_33_n_0. Critical path length was reduced through logic transformation on cell VexRiscv/IBusCachedPlugin_cache/mem_1_reg_0_i_33_comp.
  2908. INFO: [Physopt 32-952] Improved path group WNS = -0.359. Path group: userclk1. Processed net: VexRiscv/IBusCachedPlugin_cache/_zz_iBus_rsp_valid_i_2_n_0.
  2909. INFO: [Physopt 32-953] Path group WNS did not improve. Path group: userclk1. Processed net: VexRiscv/IBusCachedPlugin_cache/basesoc_state_reg_0_repN.
  2910. INFO: [Physopt 32-710] Processed net VexRiscv/IBusCachedPlugin_cache/basesoc_state_reg_0_repN. Critical path length was reduced through logic transformation on cell VexRiscv/IBusCachedPlugin_cache/mem_2_adr0[0]_i_1_comp_1.
  2911. INFO: [Physopt 32-952] Improved path group WNS = -0.333. Path group: userclk1. Processed net: VexRiscv/IBusCachedPlugin_cache/basesoc_writer_value_storage[31]_i_3_n_0_repN.
  2912. INFO: [Physopt 32-953] Path group WNS did not improve. Path group: userclk1. Processed net: VexRiscv/comb_array_muxed0[0].
  2913. INFO: [Physopt 32-710] Processed net VexRiscv/comb_array_muxed0[0]. Critical path length was reduced through logic transformation on cell VexRiscv/mem_1_reg_0_i_11_comp.
  2914. INFO: [Physopt 32-952] Improved path group WNS = -0.328. Path group: userclk1. Processed net: VexRiscv/mem_1_reg_0_i_32_n_0.
  2915. INFO: [Physopt 32-953] Path group WNS did not improve. Path group: userclk1. Processed net: VexRiscv/IBusCachedPlugin_cache/basesoc_csr_bankarray_sel_r_i_3_n_0.
  2916. INFO: [Physopt 32-663] Processed net VexRiscv/IBusCachedPlugin_cache/basesoc_slave_sel_r[2]_i_2_n_0. Re-placed instance VexRiscv/IBusCachedPlugin_cache/basesoc_slave_sel_r[2]_i_2
  2917. INFO: [Physopt 32-952] Improved path group WNS = -0.327. Path group: userclk1. Processed net: VexRiscv/IBusCachedPlugin_cache/basesoc_slave_sel_r[2]_i_2_n_0.
  2918. INFO: [Physopt 32-953] Path group WNS did not improve. Path group: userclk1. Processed net: VexRiscv/IBusCachedPlugin_cache/_zz_iBus_rsp_valid_i_2_n_0_repN.
  2919. INFO: [Physopt 32-663] Processed net VexRiscv/IBusCachedPlugin_cache/FSM_sequential_subfragments_resetinserter_state_reg[2][0]. Re-placed instance VexRiscv/IBusCachedPlugin_cache/icap_data_storage[31]_i_1
  2920. INFO: [Physopt 32-952] Improved path group WNS = -0.130. Path group: userclk1. Processed net: VexRiscv/IBusCachedPlugin_cache/FSM_sequential_subfragments_resetinserter_state_reg[2][0].
  2921. INFO: [Physopt 32-953] Path group WNS did not improve. Path group: userclk1. Processed net: storage_9_dat1[54].
  2922. INFO: [Physopt 32-710] Processed net basesoc_reader_data_fifo_syncfifo_re. Critical path length was reduced through logic transformation on cell storage_9_reg_0_i_2_comp.
  2923. INFO: [Physopt 32-735] Processed net storage_9_reg_0_i_23_n_0. Optimization improves timing on the net.
  2924. INFO: [Physopt 32-668] Current Timing Summary | WNS=-2.322 | TNS=-73.690 | WHS=0.018 | THS=0.000 |
  2925. INFO: [Physopt 32-953] Path group WNS did not improve. Path group: icap_clk. Processed net: icap_o_icape2[0].
  2926. INFO: [Physopt 32-953] Path group WNS did not improve. Path group: icap_clk. Processed net: pcie_support/pipe_clock_i/userclk1.
  2927. INFO: [Physopt 32-953] Path group WNS did not improve. Path group: icap_clk. Processed net: ICAPE2_i_45_n_0.
  2928. INFO: [Physopt 32-953] Path group WNS did not improve. Path group: icap_clk. Processed net: icap__i[14].
  2929. INFO: [Physopt 32-953] Path group WNS did not improve. Path group: icap_clk. Processed net: icap_addr_storage[1].
  2930. INFO: [Physopt 32-953] Path group WNS did not improve. Path group: clk_250mhz. Processed net: pcie_support/pipe_clock_i/pclk_sel.
  2931. INFO: [Physopt 32-668] Current Timing Summary | WNS=-2.322 | TNS=-73.690 | WHS=0.018 | THS=0.000 |
  2932. Phase 2 Critical Path Optimization | Checksum: 20f04ee07
  2933.  
  2934. Time (s): cpu = 00:01:15 ; elapsed = 00:00:38 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1923 ; free virtual = 20835
  2935. Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1923 ; free virtual = 20835
  2936. INFO: [Physopt 32-669] Post Physical Optimization Timing Summary | WNS=-2.322 | TNS=-73.690 | WHS=0.018 | THS=0.000 |
  2937.  
  2938. Summary of Physical Synthesis Optimizations
  2939. ============================================
  2940.  
  2941.  
  2942. -------------------------------------------------------------------------------------------------------------------------------------------------------------
  2943. | Optimization | WNS Gain (ns) | TNS Gain (ns) | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
  2944. -------------------------------------------------------------------------------------------------------------------------------------------------------------
  2945. | Critical Path | 0.016 | 72.411 | 0 | 0 | 20 | 0 | 1 | 00:00:36 |
  2946. -------------------------------------------------------------------------------------------------------------------------------------------------------------
  2947.  
  2948.  
  2949. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1923 ; free virtual = 20835
  2950. Ending Physical Synthesis Task | Checksum: 282b6cefe
  2951.  
  2952. Time (s): cpu = 00:01:15 ; elapsed = 00:00:38 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1924 ; free virtual = 20837
  2953. INFO: [Common 17-83] Releasing license: Implementation
  2954. 79 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
  2955. phys_opt_design completed successfully
  2956. phys_opt_design: Time (s): cpu = 00:01:21 ; elapsed = 00:00:40 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1976 ; free virtual = 20889
  2957. # write_checkpoint -force fairwaves_xtrx_route.dcp
  2958. INFO: [Timing 38-480] Writing timing data to binary archive.
  2959. Writing placer database...
  2960. Writing XDEF routing.
  2961. Writing XDEF routing logical nets.
  2962. Writing XDEF routing special nets.
  2963. Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.50 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1947 ; free virtual = 20879
  2964. INFO: [Common 17-1381] The checkpoint '/home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx_route.dcp' has been generated.
  2965. # report_timing_summary -no_header -no_detailed_paths
  2966. INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
  2967. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
  2968. ------------------------------------------------------------------------------------------------
  2969. | Timer Settings
  2970. | --------------
  2971. ------------------------------------------------------------------------------------------------
  2972.  
  2973. Enable Multi Corner Analysis : Yes
  2974. Enable Pessimism Removal : Yes
  2975. Pessimism Removal Resolution : Nearest Common Node
  2976. Enable Input Delay Default Clock : No
  2977. Enable Preset / Clear Arcs : No
  2978. Disable Flight Delays : No
  2979. Ignore I/O Paths : No
  2980. Timing Early Launch at Borrowing Latches : No
  2981. Borrow Time for Max Delay Exceptions : Yes
  2982. Merge Timing Exceptions : Yes
  2983.  
  2984. Corner Analyze Analyze
  2985. Name Max Paths Min Paths
  2986. ------ --------- ---------
  2987. Slow Yes Yes
  2988. Fast Yes Yes
  2989.  
  2990.  
  2991. ------------------------------------------------------------------------------------------------
  2992. | Report Methodology
  2993. | ------------------
  2994. ------------------------------------------------------------------------------------------------
  2995.  
  2996. No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.
  2997.  
  2998.  
  2999.  
  3000. check_timing report
  3001.  
  3002. Table of Contents
  3003. -----------------
  3004. 1. checking no_clock (0)
  3005. 2. checking constant_clock (0)
  3006. 3. checking pulse_width_clock (4)
  3007. 4. checking unconstrained_internal_endpoints (0)
  3008. 5. checking no_input_delay (2)
  3009. 6. checking no_output_delay (3)
  3010. 7. checking multiple_clock (616)
  3011. 8. checking generated_clocks (0)
  3012. 9. checking loops (0)
  3013. 10. checking partial_input_delay (0)
  3014. 11. checking partial_output_delay (0)
  3015. 12. checking latch_loops (0)
  3016.  
  3017. 1. checking no_clock (0)
  3018. ------------------------
  3019. There are 0 register/latch pins with no clock.
  3020.  
  3021.  
  3022. 2. checking constant_clock (0)
  3023. ------------------------------
  3024. There are 0 register/latch pins with constant_clock.
  3025.  
  3026.  
  3027. 3. checking pulse_width_clock (4)
  3028. ---------------------------------
  3029. There are 4 register/latch pins which need pulse_width check. (LOW)
  3030.  
  3031.  
  3032. 4. checking unconstrained_internal_endpoints (0)
  3033. ------------------------------------------------
  3034. There are 0 pins that are not constrained for maximum delay.
  3035.  
  3036. There are 0 pins that are not constrained for maximum delay due to constant clock.
  3037.  
  3038.  
  3039. 5. checking no_input_delay (2)
  3040. ------------------------------
  3041. There are 2 input ports with no input delay specified. (HIGH)
  3042.  
  3043. There are 0 input ports with no input delay but user has a false path constraint.
  3044.  
  3045.  
  3046. 6. checking no_output_delay (3)
  3047. -------------------------------
  3048. There are 3 ports with no output delay specified. (HIGH)
  3049.  
  3050. There are 0 ports with no output delay but user has a false path constraint
  3051.  
  3052. There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
  3053.  
  3054.  
  3055. 7. checking multiple_clock (616)
  3056. --------------------------------
  3057. There are 616 register/latch pins with multiple clocks. (HIGH)
  3058.  
  3059.  
  3060. 8. checking generated_clocks (0)
  3061. --------------------------------
  3062. There are 0 generated clocks that are not connected to a clock source.
  3063.  
  3064.  
  3065. 9. checking loops (0)
  3066. ---------------------
  3067. There are 0 combinational loops in the design.
  3068.  
  3069.  
  3070. 10. checking partial_input_delay (0)
  3071. ------------------------------------
  3072. There are 0 input ports with partial input delay specified.
  3073.  
  3074.  
  3075. 11. checking partial_output_delay (0)
  3076. -------------------------------------
  3077. There are 0 ports with partial output delay specified.
  3078.  
  3079.  
  3080. 12. checking latch_loops (0)
  3081. ----------------------------
  3082. There are 0 combinational latch loops in the design through latch input
  3083.  
  3084.  
  3085.  
  3086. ------------------------------------------------------------------------------------------------
  3087. | Design Timing Summary
  3088. | ---------------------
  3089. ------------------------------------------------------------------------------------------------
  3090.  
  3091. WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
  3092. ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
  3093. -2.322 -73.690 76 21183 0.018 0.000 0 21183 0.000 0.000 0 6333
  3094.  
  3095.  
  3096. Timing constraints are not met.
  3097.  
  3098.  
  3099. ------------------------------------------------------------------------------------------------
  3100. | Clock Summary
  3101. | -------------
  3102. ------------------------------------------------------------------------------------------------
  3103.  
  3104. Clock Waveform(ns) Period(ns) Frequency(MHz)
  3105. ----- ------------ ---------- --------------
  3106. icap_clk {0.000 64.000} 128.000 7.812
  3107. pcie_x2_clk_p {0.000 5.000} 10.000 100.000
  3108. txoutclk_x0y0 {0.000 5.000} 10.000 100.000
  3109. clk_125mhz {0.000 4.000} 8.000 125.000
  3110. clk_250mhz {0.000 2.000} 4.000 250.000
  3111. mmcm_fb {0.000 5.000} 10.000 100.000
  3112. userclk1 {0.000 4.000} 8.000 125.000
  3113.  
  3114.  
  3115. ------------------------------------------------------------------------------------------------
  3116. | Intra Clock Table
  3117. | -----------------
  3118. ------------------------------------------------------------------------------------------------
  3119.  
  3120. Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
  3121. ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
  3122. icap_clk 118.955 0.000 0 109 0.459 0.000 0 109 63.500 0.000 0 40
  3123. pcie_x2_clk_p 8.692 0.000 0 7 0.215 0.000 0 7 4.146 0.000 0 12
  3124. txoutclk_x0y0 3.000 0.000 0 3
  3125. clk_125mhz 1.399 0.000 0 1792 0.118 0.000 0 1792 0.047 0.000 0 828
  3126. clk_250mhz -0.432 -0.432 1 1297 0.294 0.000 0 1297 0.000 0.000 0 618
  3127. mmcm_fb 8.751 0.000 0 2
  3128. userclk1 0.049 0.000 0 19236 0.018 0.000 0 19236 0.547 0.000 0 5446
  3129.  
  3130.  
  3131. ------------------------------------------------------------------------------------------------
  3132. | Inter Clock Table
  3133. | -----------------
  3134. ------------------------------------------------------------------------------------------------
  3135.  
  3136. From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
  3137. ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
  3138. userclk1 icap_clk -2.322 -73.131 75 75 2.158 0.000 0 75
  3139. clk_250mhz clk_125mhz 0.088 0.000 0 1303 0.055 0.000 0 1303
  3140. clk_125mhz clk_250mhz -0.558 -0.558 1 1302 0.055 0.000 0 1302
  3141. icap_clk userclk1 0.055 0.000 0 65 0.052 0.000 0 65
  3142. clk_125mhz userclk1 4.190 0.000 0 9 0.089 0.000 0 9
  3143. clk_250mhz userclk1 0.190 0.000 0 9 0.089 0.000 0 9
  3144.  
  3145.  
  3146. ------------------------------------------------------------------------------------------------
  3147. | Other Path Groups Table
  3148. | -----------------------
  3149. ------------------------------------------------------------------------------------------------
  3150.  
  3151. Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
  3152. ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
  3153. **async_default** userclk1 userclk1 5.961 0.000 0 2 0.689 0.000 0 2
  3154.  
  3155.  
  3156. # report_route_status -file fairwaves_xtrx_route_status.rpt
  3157. # report_drc -file fairwaves_xtrx_drc.rpt
  3158. Command: report_drc -file fairwaves_xtrx_drc.rpt
  3159. INFO: [IP_Flow 19-1839] IP Catalog is up to date.
  3160. INFO: [DRC 23-27] Running DRC with 8 threads
  3161. INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/mikek/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets/build/fairwaves_xtrx/gateware/fairwaves_xtrx_drc.rpt.
  3162. report_drc completed successfully
  3163. # report_timing_summary -datasheet -max_paths 10 -file fairwaves_xtrx_timing.rpt
  3164. INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
  3165. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
  3166. # report_power -file fairwaves_xtrx_power.rpt
  3167. Command: report_power -file fairwaves_xtrx_power.rpt
  3168. INFO: [Power 33-23] Power model is not available for STARTUPE2
  3169. Running Vector-less Activity Propagation...
  3170.  
  3171. Finished Running Vector-less Activity Propagation
  3172. WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
  3173. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
  3174. 1 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
  3175. report_power completed successfully
  3176. # set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
  3177. # set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]
  3178. # set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
  3179. # write_bitstream -force fairwaves_xtrx.bit
  3180. Command: write_bitstream -force fairwaves_xtrx.bit
  3181. Attempting to get a license for feature 'Implementation' and/or device 'xc7a50t'
  3182. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a50t'
  3183. Running DRC as a precondition to command write_bitstream
  3184. INFO: [IP_Flow 19-1839] IP Catalog is up to date.
  3185. INFO: [DRC 23-27] Running DRC with 8 threads
  3186. WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
  3187.  
  3188. set_property CFGBVS value1 [current_design]
  3189. #where value1 is either VCCO or GND
  3190.  
  3191. set_property CONFIG_VOLTAGE value2 [current_design]
  3192. #where value2 is the voltage provided to configuration bank 0
  3193.  
  3194. Refer to the device configuration user guide for more information.
  3195. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_HL_reg input VexRiscv/execute_to_memory_MUL_HL_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
  3196. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_HL_reg input VexRiscv/execute_to_memory_MUL_HL_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
  3197. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_LH_reg input VexRiscv/execute_to_memory_MUL_LH_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
  3198. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_LH_reg input VexRiscv/execute_to_memory_MUL_LH_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
  3199. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_LL_reg input VexRiscv/execute_to_memory_MUL_LL_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
  3200. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_LL_reg input VexRiscv/execute_to_memory_MUL_LL_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
  3201. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/memory_to_writeBack_MUL_HH_reg input VexRiscv/memory_to_writeBack_MUL_HH_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
  3202. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/memory_to_writeBack_MUL_HH_reg input VexRiscv/memory_to_writeBack_MUL_HH_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
  3203. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP VexRiscv/execute_to_memory_MUL_HL_reg multiplier stage VexRiscv/execute_to_memory_MUL_HL_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
  3204. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP VexRiscv/execute_to_memory_MUL_LH_reg multiplier stage VexRiscv/execute_to_memory_MUL_LH_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
  3205. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP VexRiscv/execute_to_memory_MUL_LL_reg multiplier stage VexRiscv/execute_to_memory_MUL_LL_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
  3206. WARNING: [DRC PDRC-153] Gated clock check: Net sys_clk is a gated clock net sourced by a combinational pin pcie_clk_inst/O, cell pcie_clk_inst. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
  3207. WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT pcie_clk_inst is driving clock pin of 5121 cells. This could lead to large hold time violations. Involved cells are:
  3208. FSM_onehot_basesoc_grant_reg[0], FSM_onehot_basesoc_grant_reg[1], FSM_onehot_basesoc_grant_reg[2], FSM_sequential_subfragments_fsm0_state_reg, FSM_sequential_subfragments_fsm1_state_reg[0], FSM_sequential_subfragments_fsm1_state_reg[1], FSM_sequential_subfragments_litepcietlpdepacketizer_state_reg[0], FSM_sequential_subfragments_litepcietlpdepacketizer_state_reg[1], FSM_sequential_subfragments_litepcietlppacketizer_state_reg[0], FSM_sequential_subfragments_litepcietlppacketizer_state_reg[1], FSM_sequential_subfragments_litepciewishbonemaster_state_reg[0], FSM_sequential_subfragments_litepciewishbonemaster_state_reg[1], FSM_sequential_subfragments_s7spiflash_state_reg[0], FSM_sequential_subfragments_s7spiflash_state_reg[1], VexRiscv/CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr_reg[0]... and (the first 15 of 5121 listed)
  3209. WARNING: [DRC RTSTAT-10] No routable loads: 1 net(s) have no routable loads. The problem bus(es) and/or net(s) are pcie_support/pcie_i/inst/inst/store_ltssm.
  3210. INFO: [Vivado 12-3199] DRC finished with 0 Errors, 15 Warnings
  3211. INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
  3212. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
  3213. Loading data files...
  3214. Loading site data...
  3215. Loading route data...
  3216. Processing options...
  3217. Creating bitmap...
  3218. Creating bitstream...
  3219. Bitstream compression saved 5594400 bits.
  3220. Writing bitstream ./fairwaves_xtrx.bit...
  3221. INFO: [Vivado 12-1842] Bitgen Completed Successfully.
  3222. INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
  3223. INFO: [Common 17-83] Releasing license: Implementation
  3224. 9 Infos, 15 Warnings, 0 Critical Warnings and 0 Errors encountered.
  3225. write_bitstream completed successfully
  3226. write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:13 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1994 ; free virtual = 20907
  3227. # write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit "up 0x0 fairwaves_xtrx.bit" -file fairwaves_xtrx.bin
  3228. Command: write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit {up 0x0 fairwaves_xtrx.bit} -file fairwaves_xtrx.bin
  3229. Creating config memory files...
  3230. Creating bitstream load up from address 0x00000000
  3231. Loading bitfile fairwaves_xtrx.bit
  3232. Writing file ./fairwaves_xtrx.bin
  3233. Writing log file ./fairwaves_xtrx.prm
  3234. ===================================
  3235. Configuration Memory information
  3236. ===================================
  3237. File Format BIN
  3238. Interface SPIX4
  3239. Size 16M
  3240. Start Address 0x00000000
  3241. End Address 0x00FFFFFF
  3242.  
  3243. Addr1 Addr2 Date File(s)
  3244. 0x00000000 0x0016C6E3 Dec 21 16:23:00 2021 fairwaves_xtrx.bit
  3245. 0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
  3246. write_cfgmem completed successfully
  3247. # set_property BITSTREAM.CONFIG.TIMER_CFG 0x0001fbd0 [current_design]
  3248. # set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design]
  3249. # write_bitstream -force fairwaves_xtrx_operational.bit
  3250. Command: write_bitstream -force fairwaves_xtrx_operational.bit
  3251. Attempting to get a license for feature 'Implementation' and/or device 'xc7a50t'
  3252. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a50t'
  3253. Running DRC as a precondition to command write_bitstream
  3254. INFO: [IP_Flow 19-1839] IP Catalog is up to date.
  3255. INFO: [DRC 23-27] Running DRC with 8 threads
  3256. WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
  3257.  
  3258. set_property CFGBVS value1 [current_design]
  3259. #where value1 is either VCCO or GND
  3260.  
  3261. set_property CONFIG_VOLTAGE value2 [current_design]
  3262. #where value2 is the voltage provided to configuration bank 0
  3263.  
  3264. Refer to the device configuration user guide for more information.
  3265. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_HL_reg input VexRiscv/execute_to_memory_MUL_HL_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
  3266. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_HL_reg input VexRiscv/execute_to_memory_MUL_HL_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
  3267. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_LH_reg input VexRiscv/execute_to_memory_MUL_LH_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
  3268. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_LH_reg input VexRiscv/execute_to_memory_MUL_LH_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
  3269. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_LL_reg input VexRiscv/execute_to_memory_MUL_LL_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
  3270. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_LL_reg input VexRiscv/execute_to_memory_MUL_LL_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
  3271. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/memory_to_writeBack_MUL_HH_reg input VexRiscv/memory_to_writeBack_MUL_HH_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
  3272. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/memory_to_writeBack_MUL_HH_reg input VexRiscv/memory_to_writeBack_MUL_HH_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
  3273. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP VexRiscv/execute_to_memory_MUL_HL_reg multiplier stage VexRiscv/execute_to_memory_MUL_HL_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
  3274. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP VexRiscv/execute_to_memory_MUL_LH_reg multiplier stage VexRiscv/execute_to_memory_MUL_LH_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
  3275. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP VexRiscv/execute_to_memory_MUL_LL_reg multiplier stage VexRiscv/execute_to_memory_MUL_LL_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
  3276. WARNING: [DRC PDRC-153] Gated clock check: Net sys_clk is a gated clock net sourced by a combinational pin pcie_clk_inst/O, cell pcie_clk_inst. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
  3277. WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT pcie_clk_inst is driving clock pin of 5121 cells. This could lead to large hold time violations. Involved cells are:
  3278. FSM_onehot_basesoc_grant_reg[0], FSM_onehot_basesoc_grant_reg[1], FSM_onehot_basesoc_grant_reg[2], FSM_sequential_subfragments_fsm0_state_reg, FSM_sequential_subfragments_fsm1_state_reg[0], FSM_sequential_subfragments_fsm1_state_reg[1], FSM_sequential_subfragments_litepcietlpdepacketizer_state_reg[0], FSM_sequential_subfragments_litepcietlpdepacketizer_state_reg[1], FSM_sequential_subfragments_litepcietlppacketizer_state_reg[0], FSM_sequential_subfragments_litepcietlppacketizer_state_reg[1], FSM_sequential_subfragments_litepciewishbonemaster_state_reg[0], FSM_sequential_subfragments_litepciewishbonemaster_state_reg[1], FSM_sequential_subfragments_s7spiflash_state_reg[0], FSM_sequential_subfragments_s7spiflash_state_reg[1], VexRiscv/CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr_reg[0]... and (the first 15 of 5121 listed)
  3279. WARNING: [DRC RTSTAT-10] No routable loads: 1 net(s) have no routable loads. The problem bus(es) and/or net(s) are pcie_support/pcie_i/inst/inst/store_ltssm.
  3280. INFO: [Vivado 12-3199] DRC finished with 0 Errors, 15 Warnings
  3281. INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
  3282. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
  3283. Loading data files...
  3284. Loading site data...
  3285. Loading route data...
  3286. Processing options...
  3287. Creating bitmap...
  3288. Creating bitstream...
  3289. Bitstream compression saved 5594400 bits.
  3290. Writing bitstream ./fairwaves_xtrx_operational.bit...
  3291. INFO: [Vivado 12-1842] Bitgen Completed Successfully.
  3292. INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
  3293. INFO: [Common 17-83] Releasing license: Implementation
  3294. 9 Infos, 15 Warnings, 0 Critical Warnings and 0 Errors encountered.
  3295. write_bitstream completed successfully
  3296. write_bitstream: Time (s): cpu = 00:00:25 ; elapsed = 00:00:11 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1983 ; free virtual = 20899
  3297. # write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit "up 0x0 fairwaves_xtrx_operational.bit" -file fairwaves_xtrx_operational.bin
  3298. Command: write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit {up 0x0 fairwaves_xtrx_operational.bit} -file fairwaves_xtrx_operational.bin
  3299. Creating config memory files...
  3300. Creating bitstream load up from address 0x00000000
  3301. Loading bitfile fairwaves_xtrx_operational.bit
  3302. Writing file ./fairwaves_xtrx_operational.bin
  3303. Writing log file ./fairwaves_xtrx_operational.prm
  3304. ===================================
  3305. Configuration Memory information
  3306. ===================================
  3307. File Format BIN
  3308. Interface SPIX4
  3309. Size 16M
  3310. Start Address 0x00000000
  3311. End Address 0x00FFFFFF
  3312.  
  3313. Addr1 Addr2 Date File(s)
  3314. 0x00000000 0x0016C6E3 Dec 21 16:23:12 2021 fairwaves_xtrx_operational.bit
  3315. 0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
  3316. write_cfgmem completed successfully
  3317. # set_property BITSTREAM.CONFIG.NEXT_CONFIG_ADDR 0x00400000 [current_design]
  3318. # write_bitstream -force fairwaves_xtrx_fallback.bit
  3319. Command: write_bitstream -force fairwaves_xtrx_fallback.bit
  3320. Attempting to get a license for feature 'Implementation' and/or device 'xc7a50t'
  3321. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a50t'
  3322. Running DRC as a precondition to command write_bitstream
  3323. INFO: [IP_Flow 19-1839] IP Catalog is up to date.
  3324. INFO: [DRC 23-27] Running DRC with 8 threads
  3325. WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
  3326.  
  3327. set_property CFGBVS value1 [current_design]
  3328. #where value1 is either VCCO or GND
  3329.  
  3330. set_property CONFIG_VOLTAGE value2 [current_design]
  3331. #where value2 is the voltage provided to configuration bank 0
  3332.  
  3333. Refer to the device configuration user guide for more information.
  3334. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_HL_reg input VexRiscv/execute_to_memory_MUL_HL_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
  3335. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_HL_reg input VexRiscv/execute_to_memory_MUL_HL_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
  3336. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_LH_reg input VexRiscv/execute_to_memory_MUL_LH_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
  3337. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_LH_reg input VexRiscv/execute_to_memory_MUL_LH_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
  3338. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_LL_reg input VexRiscv/execute_to_memory_MUL_LL_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
  3339. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/execute_to_memory_MUL_LL_reg input VexRiscv/execute_to_memory_MUL_LL_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
  3340. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/memory_to_writeBack_MUL_HH_reg input VexRiscv/memory_to_writeBack_MUL_HH_reg/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
  3341. WARNING: [DRC DPIP-1] Input pipelining: DSP VexRiscv/memory_to_writeBack_MUL_HH_reg input VexRiscv/memory_to_writeBack_MUL_HH_reg/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
  3342. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP VexRiscv/execute_to_memory_MUL_HL_reg multiplier stage VexRiscv/execute_to_memory_MUL_HL_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
  3343. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP VexRiscv/execute_to_memory_MUL_LH_reg multiplier stage VexRiscv/execute_to_memory_MUL_LH_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
  3344. WARNING: [DRC DPOP-2] MREG Output pipelining: DSP VexRiscv/execute_to_memory_MUL_LL_reg multiplier stage VexRiscv/execute_to_memory_MUL_LL_reg/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
  3345. WARNING: [DRC PDRC-153] Gated clock check: Net sys_clk is a gated clock net sourced by a combinational pin pcie_clk_inst/O, cell pcie_clk_inst. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
  3346. WARNING: [DRC PLHOLDVIO-2] Non-Optimal connections which could lead to hold violations: A LUT pcie_clk_inst is driving clock pin of 5121 cells. This could lead to large hold time violations. Involved cells are:
  3347. FSM_onehot_basesoc_grant_reg[0], FSM_onehot_basesoc_grant_reg[1], FSM_onehot_basesoc_grant_reg[2], FSM_sequential_subfragments_fsm0_state_reg, FSM_sequential_subfragments_fsm1_state_reg[0], FSM_sequential_subfragments_fsm1_state_reg[1], FSM_sequential_subfragments_litepcietlpdepacketizer_state_reg[0], FSM_sequential_subfragments_litepcietlpdepacketizer_state_reg[1], FSM_sequential_subfragments_litepcietlppacketizer_state_reg[0], FSM_sequential_subfragments_litepcietlppacketizer_state_reg[1], FSM_sequential_subfragments_litepciewishbonemaster_state_reg[0], FSM_sequential_subfragments_litepciewishbonemaster_state_reg[1], FSM_sequential_subfragments_s7spiflash_state_reg[0], FSM_sequential_subfragments_s7spiflash_state_reg[1], VexRiscv/CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr_reg[0]... and (the first 15 of 5121 listed)
  3348. WARNING: [DRC RTSTAT-10] No routable loads: 1 net(s) have no routable loads. The problem bus(es) and/or net(s) are pcie_support/pcie_i/inst/inst/store_ltssm.
  3349. INFO: [Vivado 12-3199] DRC finished with 0 Errors, 15 Warnings
  3350. INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
  3351. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
  3352. Loading data files...
  3353. Loading site data...
  3354. Loading route data...
  3355. Processing options...
  3356. Creating bitmap...
  3357. Creating bitstream...
  3358. Bitstream compression saved 5594400 bits.
  3359. Writing bitstream ./fairwaves_xtrx_fallback.bit...
  3360. INFO: [Vivado 12-1842] Bitgen Completed Successfully.
  3361. INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
  3362. INFO: [Common 17-83] Releasing license: Implementation
  3363. 9 Infos, 15 Warnings, 0 Critical Warnings and 0 Errors encountered.
  3364. write_bitstream completed successfully
  3365. write_bitstream: Time (s): cpu = 00:00:25 ; elapsed = 00:00:11 . Memory (MB): peak = 3532.598 ; gain = 0.000 ; free physical = 1985 ; free virtual = 20903
  3366. # write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit "up 0x0 fairwaves_xtrx_fallback.bit" -file fairwaves_xtrx_fallback.bin
  3367. Command: write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit {up 0x0 fairwaves_xtrx_fallback.bit} -file fairwaves_xtrx_fallback.bin
  3368. Creating config memory files...
  3369. Creating bitstream load up from address 0x00000000
  3370. Loading bitfile fairwaves_xtrx_fallback.bit
  3371. Writing file ./fairwaves_xtrx_fallback.bin
  3372. Writing log file ./fairwaves_xtrx_fallback.prm
  3373. ===================================
  3374. Configuration Memory information
  3375. ===================================
  3376. File Format BIN
  3377. Interface SPIX4
  3378. Size 16M
  3379. Start Address 0x00000000
  3380. End Address 0x00FFFFFF
  3381.  
  3382. Addr1 Addr2 Date File(s)
  3383. 0x00000000 0x0016C6E3 Dec 21 16:23:23 2021 fairwaves_xtrx_fallback.bit
  3384. 0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
  3385. write_cfgmem completed successfully
  3386. # quit
  3387. INFO: [Common 17-206] Exiting Vivado at Tue Dec 21 16:23:24 2021...
  3388. (Litex_Nov2021) mikek@mike-AERO-17:~/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets$
  3389. (Litex_Nov2021) mikek@mike-AERO-17:~/Documents/Cyclone5_SOC/Litex_New_release_Sept2021/litex-boards/litex_boards/targets$
  3390.  
  3391.  
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement