// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2018 PHYTEC Messtechnik GmbH
 * Author: Christian Hemp <c.hemp@phytec.de>
 */

/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-phytec-phycore-som.dtsi"
#include "imx6qdl-phytec-mira.dtsi"
#include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
#include "imx6qdl-phytec-mira-peb-av-02.dtsi"
#include "imx6qdl-phytec-peb-wlbt-01.dtsi"
#include <dt-bindings/sound/fsl-imx-audmux.h>

/ {
	model = "PHYTEC phyBOARD-Mira Quad full featured with NAND";
	compatible = "phytec,imx6q-pbac06-nand", "phytec,imx6q-pbac06",
		     "phytec,imx6qdl-pcm058", "fsl,imx6q";

	chosen {
		linux,stdout-path = &uart2;
	};
};

#define SSI_TEST_MASTER
/*
 * port 4 is datasheet port 5 (aud5)
 * port 6 is datasheet port 7 (ssi3)
 */
#define AUDMUX_EXT_PORT 4
#define AUDMUX_INT_PORT MX31_AUDMUX_PORT1_SSI0
#define AUDMUX_INT_PORT_NAME aud5
&audmux {
        status = "okay";
	//ssi3 {
	ssi1 {
         fsl,audmux-port = <AUDMUX_INT_PORT>;
         fsl,port-config = <
#ifdef SSI_TEST_MASTER
	IMX_AUDMUX_V2_PTCR_SYN
#else
	(IMX_AUDMUX_V2_PTCR_TFSDIR |
	IMX_AUDMUX_V2_PTCR_TFSEL(AUDMUX_EXT_PORT) |
	IMX_AUDMUX_V2_PTCR_TCLKDIR |
	IMX_AUDMUX_V2_PTCR_TCSEL(AUDMUX_EXT_PORT) |
	IMX_AUDMUX_V2_PTCR_SYN
	)
#endif
             IMX_AUDMUX_V2_PDCR_RXDSEL(AUDMUX_EXT_PORT)
	>;
     };

     AUDMUX_INT_PORT_NAME {
         fsl,audmux-port = <AUDMUX_EXT_PORT>;
         fsl,port-config = <
#ifdef SSI_TEST_MASTER
             (IMX_AUDMUX_V2_PTCR_TFSDIR |
             IMX_AUDMUX_V2_PTCR_TFSEL(AUDMUX_INT_PORT) |
             IMX_AUDMUX_V2_PTCR_TCLKDIR |
             IMX_AUDMUX_V2_PTCR_TCSEL(AUDMUX_INT_PORT) |
	     	IMX_AUDMUX_V2_PTCR_SYN
	     )
#else
	IMX_AUDMUX_V2_PTCR_SYN
#endif
             IMX_AUDMUX_V2_PDCR_RXDSEL(AUDMUX_INT_PORT)
         >;
     };
};


&ssi1 {
     pinctrl-names = "default";
     pinctrl-0 = <&pinctrl_audmux>;
     fsl,mode = "i2s-master";
     status = "okay";

     // select the a clock parent suitable for 48000 Hz sampling rate
     assigned-clocks = <&clks IMX6QDL_CLK_SSI1_SEL>, <&clks IMX6QDL_CLK_SSI1>;
     assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
     assigned-clock-rates = <0>, <49152000>;
};

//&ssi3 {
//     pinctrl-names = "default";
//     pinctrl-0 = <&pinctrl_audmux>;
//     fsl,mode = "i2s-master";
//     status = "okay";
//
//     // select the a clock parent suitable for 48000 Hz sampling rate
//     assigned-clocks = <&clks IMX6QDL_CLK_SSI3_SEL>, <&clks IMX6QDL_CLK_SSI3>;
//     assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
//     assigned-clock-rates = <0>, <49152000>;
//};

/ {
     codec_test: codec_test {
         compatible = "linux,snd-soc-dummy";
         #sound-dai-cells = <0>;
     };


     sound@2 {
         compatible = "simple-audio-card";
         simple-audio-card,name = "loopback-ssi-test";
         simple-audio-card,format="dsp_a";

#ifdef SSI_TEST_MASTER
         simple-audio-card,frame-master = <&sound2_ssi>;
         simple-audio-card,bitclock-master = <&sound2_ssi>;
#else
         simple-audio-card,frame-master = <&codec_test>;
         simple-audio-card,bitclock-master = <&codec_test>;
#endif
             sound2_ssi: simple-audio-card,cpu {
                 //sound-dai = <&ssi3>;
                 sound-dai = <&ssi1>;
                 system-clock-frequency = <1536000>;
                 dai-tdm-slot-num = <8>;
                 dai-tdm-slot-width = <16>;
             };
             sound2codec: simple-audio-card,codec {
                 sound-dai = <&codec_test>;
             };
     };

};

&iomuxc {

	pinctrl-names = "default";

	pinctrl_audmux: audmuxgrp {
		fsl,pins = <
			MX6QDL_PAD_DISP0_DAT19__AUD5_RXD        0x130b0 // wandboard  jp1.20
			MX6QDL_PAD_DISP0_DAT16__AUD5_TXC	0x130b0 // wandboard, jp1.14
			MX6QDL_PAD_DISP0_DAT17__AUD5_TXD	0x110b0 // wandboard  jp1.16
			MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS	0x130b0 // wandboard  jp1.18
			MX6QDL_PAD_GPIO_19__CCM_CLKO1           0x130b0 // wandboard  jp4.18
		>;
	};
};

&can1 {
	status = "okay";
};

&dim_gpio_leds {
	status = "okay";
};

&fec {
	status = "okay";
};

&gpmi {
	status = "okay";
};

&hdmi {
	status = "okay";
};

&i2c1 {
	status = "okay";
};

&i2c2 {
	status = "okay";
};

&i2c_rtc {
	status = "okay";
};

&leddim {
	status = "okay";
};

&m25p80 {
	status = "okay";
};

&pcie {
	status = "okay";
};

&uart3 {
	status = "okay";
};

&usbh1 {
	status = "okay";
};

&usbotg {
	status = "okay";
};

&usdhc1 {
	status = "okay";
};