module pipe(

	input			clk,// Para a placa
	input 		rst,
	output[31:0] out_valor1,
	output[31:0] out_valor2,
	output[31:0] out_valor3
);

reg[31:0] decode_IR;
reg[31:0] execute_IR;
reg[31:0] memory_IR;
reg[31:0] wback_IR;

reg [9:0] PC; // Contador de programa do MIPS
reg [9:0] PC_decode;
reg [9:0] PC_execute;

reg halt;
reg jump_enable;

reg [31:0] IR; // Registrador de instrução do MIPS

wire [31:0] out_mem_inst; //saída da memória de instruções
wire [31:0] out_mem_data; //saída da memória de dados
wire signal_wren;

wire [4:0] signal_rd; // utilizado para "criar" o multiplexador que seleciona o registrador de destino do MIPS
wire [31:0] signal_dado_a_ser_escrito; // utilizado para "criar" o multiplexador que seleciona qual dado será salvo no banco de registradores do MIPS

wire [31:0] dado_lido_1; // dado lido do banco de registardores
wire [31:0] dado_lido_2; // dado lido do banco de registardores

wire [31:0] signal_reg_para_a_placa; // para a placa


	// DECODE
	reg[5:0] ex_opcode;
	reg[31:0] ex_a;
	reg[31:0] ex_b;
	reg[4:0] ex_dest;
	reg[25:0] ex_address;
	reg[31:0] ex_immediate;
	// EXECUTE
	reg[31:0] mem_saidaULA;
	reg[4:0]  mem_dest;
	reg[31:0] mem_b;
	reg[5:0]  mem_opcode;
   //
	reg[31:0] wb_write;
	reg[4:0] wb_dest;


	// instanciando a memória de instruções (ROM)
	mem_inst mem_i(.address(PC),
					.clock(clk),
					.q(out_mem_inst));

	// instanciando a memória de dados (RAM)
	mem_data mem_d(.address(mem_saidaULA[9:0]),
					.clock(clk),
					.data(mem_b),
					.wren(signal_wren),
					.q(out_mem_data));
	//para a placa		  para a placa

	// instanciando o banco de registardores
	banco_de_registradores br(.reset(rst),
								.br_in_clk(clk),
								.br_in_rs_decode(decode_IR[25:21]),
								.br_in_rt_decode(decode_IR[20:16]),
								.br_in_rd_decode(signal_rd),
								.br_in_data(wb_write),
								.br_out_R_rs(dado_lido_1),
								.br_out_R_rt(dado_lido_2));


  assign wb_enable = ( wback_IR[31:26] == 6'b000000 || wback_IR[31:26] == 6'b001000 ) ? 1 : 0 ;
  assign signal_wren = ( memory_IR[31:26] == 6'b101011 ) ? 1 : 0 ;

	always@(posedge clk) begin
		if(rst == 1'b1) begin
			decode_IR <= 32'b0;
			PC <= 10'b0;
			halt <= 1'b1;
			jump_enable <= 0;
		end
		else
		begin
			if(halt == 1'b1) begin
				halt <= 1'b0;
				PC <= PC + 1;
			end
			else
			begin
				if(jump_enable == 0) begin
					PC <= PC + 1;
					PC_decode <= PC;
					decode_IR <= out_mem_inst;
				end
				else begin
					PC <= PC_execute;
					decode_IR <= out_mem_inst;
				end
			end
		end

    //Decode
	 if( decode_IR[31:26] == 6'b001000 || decode_IR[31:26] == 6'b100011 ) begin
		ex_dest <= decode_IR[20:16];
	 end
	 else begin
		ex_dest <= decode_IR[15:11];
	 end

    ex_a <= dado_lido_1;
    ex_b <= dado_lido_2;

    ex_immediate <= {{16{decode_IR[15]}}, decode_IR[15:0]};
    execute_IR <= decode_IR;

    //Execute
    if ( execute_IR[31:26] == 6'b000000 ) begin
      //ADD
      if ( execute_IR[5:0] == 6'b100000 ) begin
        mem_saidaULA <= ex_a + ex_b;
        mem_dest <= ex_dest;
      end
      //SUB
      else if ( execute_IR[5:0] == 6'b100010 ) begin
        mem_saidaULA <= ex_a - ex_b;
        mem_dest <= ex_dest;
      end
    end
    // ADDI
	 else if ( execute_IR[31:26] == 6'b001000 ) begin
      mem_saidaULA <= ex_a + ex_immediate;
      mem_dest     <= ex_dest;
    end
	 //load
	 else if( execute_IR[31:26] == 6'b100011 ) begin
      mem_saidaULA <= ex_a + ex_immediate;
		mem_dest <= ex_dest;
	 end
	 //store
	 else if( execute_IR[31:26] == 6'b101011 ) begin
	   mem_saidaULA <= ex_a + ex_immediate;
		mem_b <= ex_b;
	 end

    memory_IR <= execute_IR;
    //Fim execute

	 //Memory

	 if( memory_IR[31:26] == 6'b000000 || memory_IR[31:26] == 6'b001000 ) begin
		wb_write  <= mem_saidaULA;
      wb_dest   <= mem_dest;
	 end
	 if( memory_IR[31:26] == 6'b100011 ) begin
      wb_write <= out_mem_data;
      wb_dest  <= mem_dest;
    end

	 wback_IR <= memory_IR;
    //Writeback


  end
endmodule