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- ----------------------------------------------------------------------------------
- -- Company:
- -- Engineer:
- --
- -- Create Date: 19:19:52 12/12/2017
- -- Design Name:
- -- Module Name: adc - Behavioral
- -- Project Name:
- -- Target Devices:
- -- Tool versions:
- -- Description:
- --
- -- Dependencies:
- --
- -- Revision:
- -- Revision 0.01 - File Created
- -- Additional Comments:
- --
- ----------------------------------------------------------------------------------
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- -- Uncomment the following library declaration if using
- -- arithmetic functions with Signed or Unsigned values
- --use IEEE.NUMERIC_STD.ALL;
- -- Uncomment the following library declaration if instantiating
- -- any Xilinx primitives in this code.
- --library UNISIM;
- --use UNISIM.VComponents.all;
- entity adc is
- port(
- reset3 : in STD_LOGIC;
- clk: in STD_LOGIC;
- SPI_MISO :in STD_LOGIC;
- AMP_CS : out STD_LOGIC;
- SPI_SCK : out STD_LOGIC;
- AMP_SHDN : out STD_LOGIC ;
- sf_ceo: out STD_logic:='1';
- fpga_init_b: out STD_logic:='0';
- dac_cs: out STD_logic:='1';
- AD_CONV : out STD_LOGIC;
- SPI_MOSI : OUT STD_LOGIC;
- SPI_SS_B : out std_logic:='1' ;
- output2 : out std_logic_vector (13 downto 6);
- output4 : out std_logic_vector (13 downto 0)
- );
- end adc;
- architecture Behavioral of adc is
- Type State_typex is (S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10);
- Signal y: State_typex:=S0;
- signal output : std_logic_vector (13 downto 0):="00000000000000";
- signal output3 : std_logic_vector (13 downto 0):="00000000000000";
- Signal enable : std_logic:='0';
- Signal i4 : Integer:=0 ;
- Signal j : Integer range 0 to 50;
- Signal clock1m : std_logic := '0' ;
- constant gain: std_logic_vector(7 downto 0):="10001000";
- begin
- process (clk )
- begin
- if(clk = '1' and clk'event)then
- if(j = 25) then
- clock1m <= clock1m xor '1' ;
- j <= j+1;
- elsif j=50 then
- clock1m<= clock1m xor '1';
- j<=0;
- else
- j<=j+1;
- end if;
- end if;
- end process ;
- amp_shdn <= '0';
- dac_cs <= '1';
- spi_ss_b <= '1';
- sf_ceo <= '1';
- fpga_init_b <= '0';
- process ( clock1m )
- begin
- if (falling_edge(clock1m)) then
- if y=s6 then
- output <= output(12 downto 0) & spi_miso;
- elsif y=s8 then
- output3<= output3(12 downto 0 ) & spi_miso ;
- end if ;
- end if;
- end process ;
- gain1 : process(clock1m, y)
- begin
- if(falling_edge(clock1m) and y = s2) then
- spi_mosi <= gain(i4);
- end if;
- end process;
- process( clk ,reset3)
- begin
- if reset3 = '1' then
- y<=S0 ;
- elsif (clk'event and clk ='1' and j = 25) then
- Case y is
- when S0 =>
- y <= S1;
- amp_cs <= '1';
- when S1 =>
- y <= S2 ;
- amp_cs <= '0';
- when S2 =>
- if(i4 < 7) then
- i4 <= i4+1 ;
- y<=S2;
- else
- y<=S3 ;
- end if;
- when S3 =>
- amp_cs <= '1';
- i4 <= 0 ;
- y <= S4 ;
- when S4 =>
- y<=S5 ;
- when S5 =>
- y <= S6;
- when S6 =>
- if( i4<14 ) then
- i4<=i4+1;
- y <= S6;
- elsif(i4 = 14) then
- i4 <= 0;
- y <= S7 ;
- end if;
- when S7 =>
- i4 <= 0;
- y<= S8 ;
- when S8 =>
- if (i4 < 14) then
- i4 <= i4+1 ;
- y<= s8 ;
- else
- i4<=0;
- y<= S9 ;
- end if ;
- when S9 =>
- i4 <= i4+1 ;
- if( i4=1 ) then
- i4<=0 ;
- y <= S10;
- else
- y<=s9 ;
- end if ;
- when S10 =>
- i4 <= i4+1 ;
- if( i4=1 ) then
- i4<=0 ;
- y <= S4;
- output2<=output (13 downto 6);
- output4<=output3 ;
- else
- y<=s10;
- end if;
- when others => y<=S0;
- end case;
- end if;
- end process ;
- spisck1: process ( clock1m )
- begin
- if(falling_edge(clock1m)) then
- if( (y = s3 ) or ( y = s10 ))
- then
- enable <= '0' ;
- elsif (( i4 = 0 and y = s2 ) or (y = s4 ) ) then
- enable <= '1' ;
- end if ;
- end if;
- end process;
- spi_sck <= clock1m when enable = '1' else '0' ;
- ad_conv <= clock1m when y =s4 else '0' ;
- end Behavioral;
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