processor

`timescale 1ns / 1ps

module Main(
    input clk,
    input man_clk,
    input MODE_clk,
    input MODE_main,
    input  [15:0] CMD,
    input  [3:0] op1,
    input  [3:0] op2,
    input  [3:0] op3,
    output [3:0] regA,
    output [3:0] regB,
    output [7:0] BUS
    );
    reg [3:0] addr;
    reg [3:0] nxt_addr;
    reg [3:0] CMD_op;
    reg [3:0] op1_r;
    reg [3:0] op2_r;
    reg [3:0] op3_r;
    reg [4:0] A;
    reg [4:0] B;
    reg [15:0] mem[15:0];
    reg ZF;
    reg GF;
    reg LF;
    reg [3:0] main_output;
    reg [3:0] error;
    integer i;
    /*
      error codes:
        0000: no error
        0001: no previous result "FETCH first argument didn't yield a result" *no op3_r @ addr-1*
        0010: Invalid FETCH argument
        0011: Invalid storage address, only the last 2 addresses can store values



    */

    //initialization of variables
    initial begin
      A = 4'b0000;
      B = 4'b0000;
      addr = 4'b0000;
      nxt_addr = 4'b0000;
    end

    always @ ( * ) begin
      //converting inputs to the main array "mem"
      mem[addr] = CMD;

      //setting up the registers
      for(i=0;i<=3;i=i+1)
      begin
        CMD_op[i] = mem[addr][i];
        op1_r[i]  = mem[addr][i+3];
        op2_r  = mem[addr][i+8];
        op3_r  = mem[addr][i+12];
      end
      //Operations and command main case
      case (CMD_op)
        //NOP
        4'b0000: nxt_addr = addr + 4'b0001 ;
        //ADD
        4'b0001: begin
                  op3_r = op1_r + op2_r;
                  nxt_addr = addr + 4'b0001;
                 end
       //SUB
       4'b0010: begin
                 op3_r = op2_r - op1_r;
                 nxt_addr = addr + 4'b0001;
                end
      //AND
      4'b0011: begin
                op3_r = op1_r & op2_r;
                if (op3_r == 4'b0000) begin
                  ZF = 1'b1;
                end
                nxt_addr = addr + 4'b0001;

               end
      //OR
      4'b0100: begin
                op3_r = op1_r | op2_r;
                nxt_addr = addr + 4'b0001;
               end
      //JMP
      4'b0101: nxt_addr = op1_r ;
      //JMPZ
      4'b0110: begin
                if(ZF)
                  begin
                    ZF = 1'b0;
                    nxt_addr = op1_r;
                  end
               end
      //JMPG
      4'b0111: begin
                if (GF) begin
                  GF = 1'b0;
                  nxt_addr = op1_r;
                end else begin
                  nxt_addr = addr + 4'b0001;
                end
                end

      //JMPL
      4'b1000: begin
                if (LF) begin
                  LF = 1'b0;
                  nxt_addr = op1_r;
                end else begin
                  nxt_addr = addr + 4'b0001;
                end
                end

      //LOADA
      4'b1001: begin
                if (op1_r == 4'b0000) begin
                  A = op2_r;
                  if (!(op3_r == 4'b1110 || op3_r == 4'b1111)) begin
                    error = 4'b0011;
                  end
                  mem[op3_r][0:3] = A;
                end else if (op1_r == 4'b0001) begin
                  A = mem[addr - 4'b0001][12:15];
                  if (!(op2_r == 4'b1110 || op2_r == 4'b1111)) begin
                    error = 4'b0011;
                  end
                  mem[op2_r][0:3] = A;
                end

               end                                                                                                  /*LOADA,LOADB : op1_r is mode select, immediate value or previous operation's result
                                                                                                                    depending on the mode, the immediate value mode considers the second argument as
      //LOADB                                                                                                       the value and the third argument as the address of where it's gonna store the value*/
      4'b1010: begin
                if (op1_r == 4'b0000) begin
                  B = op2_r;
                  if (!(op3_r == 4'b1110 || op3_r == 4'b1111)) begin
                    error = 4'b0011;
                  end
                  mem[op3_r][0:3] = B;
                end else if (op1_r == 4'b0001) begin
                  B = mem[addr - 4'b0001][12:15];
                  if (!(op2_r == 4'b1110 || op2_r == 4'b1111)) begin
                    error = 4'b0011;
                  end
                  mem[op2_r][0:3] = B;
                end
               end

      //FETCH
      /*
      FETCH command arguments:
        0000: previous result
        0001: reg A
        0010: reg B
        0011: current address
        0100: ZF
        0101: GF
        0110: LF
      */
      4'b1011: begin
                main_output = 4'b0000;
                case (op1_r)
                  4'b0000: begin
                            if (mem[addr - 4'b0001][0:3] == 4'b0001 || mem[addr - 4'b0001][0:3] == 4'b0010 || mem[addr - 4'b0001][0:3] == 4'b0011 || mem[addr - 4'b0001][0:3] == 4'b0100) begin
                              main_output = mem[addr - 4'b0001][12:15];
                            end else begin
                              error = 4'b0001;
                            end
                           end
                 4'b0001:  begin
                            main_output = A;
                           end
                 4'b0010:  begin
                            main_output = B;
                           end
                 4'b0011:  begin
                            main_output = addr;
                           end
                 4'b0100:  begin
                            main_output[0] = ZF;
                           end
                 4'b0101: begin
                            main_output[0] = GF;
                          end
                 4'b0110: begin
                            main_output[0] = LF;
                          end
                  default: error = 4'b0010 ;
                endcase



               end
      //LD0

      //comp

      //CLR

        default: ;
      endcase

    end














    /* The OP codes:
        NOP:    0000
        ADD:    0001
        SUB:    0010
        AND:    0011
        OR:     0100
        JMP:    0101
        JMPZ:   0110
        JMPG:   0111
        JMPL:   1000
        LOADA:  1001
        LOADB:  1010
        FETCH:  1011
        LD0:    1100
        LD1:    1101
        CLR:    1111
    */
endmodule