`define SW 3
`define Sa  3'b000
`define Sb  3'b001
`define Sc  3'b010
`define Sd  3'b011
`define Se  3'b100


module top_module(clk, reset, in, out);
    input clk, reset;
    input [1:0] in;
    output [1:0] out;

    reg [1:0] out;

    wire [2:0] presentState, nextStateReset;
    reg [2:0] nextState;

    vDFF #(`SW) STATE(clk, nextStateReset, presentState);
    assign nextStateReset = reset ? `Sa : nextState;

    always @(*) begin
        case({presentState,in})
            {`Sa,2'b11} : {nextState, out} = {`Sb,2'b01};
            {`Sa,2'b00} : {nextState, out} = {`Sc,2'b01};
            {`Sa,2'b01} : {nextState, out} = {`Sa,2'b01};
            {`Sa,2'b10} : {nextState, out} = {`Sa,2'b01};

            {`Sb,2'b00} : {nextState, out} = {`Sb,2'b11};
            {`Sb,2'b01} : {nextState, out} = {`Se,2'b11};
            {`Sb,2'b10} : {nextState, out} = {`Sb,2'b11};
            {`Sb,2'b11} : {nextState, out} = {`Sb,2'b11};

            {`Sc,2'b00} : {nextState, out} = {`Sc,2'b10};
            {`Sc,2'b01} : {nextState, out} = {`Sb,2'b10};
            {`Sc,2'b10} : {nextState, out} = {`Sd,2'b10};
            {`Sc,2'b11} : {nextState, out} = {`Se,2'b10};

            {`Sd,2'b00} : {nextState, out} = {`Sc,2'b11};
            {`Sd,2'b01} : {nextState, out} = {`Sc,2'b11};
            {`Sd,2'b10} : {nextState, out} = {`Sc,2'b11};
            {`Sd,2'b11} : {nextState, out} = {`Sc,2'b11};

            {`Se,2'b00} : {nextState, out} = {`Sd,2'b00};
            {`Se,2'b01} : {nextState, out} = {`Se,2'b00};
            {`Se,2'b10} : {nextState, out} = {`Se,2'b00};
            {`Se,2'b11} : {nextState, out} = {`Se,2'b00};

            default : {nextState, out} = {3'bxxx,2'bxx};

        endcase

    end



endmodule

module vDFF(clk,D,Q);
  parameter n=1;
  input clk;
  input [n-1:0] D;
  output [n-1:0] Q;
  reg [n-1:0] Q;
  always @(posedge clk)
    Q <= D;
endmodule