module zad1(
    input [0:2] KEY,
    output [9:0] LEDR);

    counter_modulo_k ex1(KEY[0], KEY[1], KEY[2], LEDR[4:0], LEDR[9]);

endmodule

module counter_modulo_k
    #(parameter k=20)
    (input clk, aclr, enable,
    output reg [N-1:0] Q,
    output reg rollover);

    localparam N=clogb2(k-1);
    function integer clogb2(input [31:0] v);
    for(clogb2=0;v>0;clogb2=clogb2+1)
        v=v>>1;
    endfunction

    always@(posedge clk, negedge aclr)
        if(!aclr)
            Q<=0;
        else
            if(enable==1)
                begin
                    if(Q==(k-1))
                        begin
                            rollover<=1;
                            Q<=0;
                        end
                    else
                        begin
                            rollover<=0;
                            Q<=Q+1;
                        end
                end

endmodule