library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity zadatak is
	port (
		iA   : in std_logic_vector (7 downto 0);
		iB   : in std_logic_vector (2 downto 0);
		iSEL : in std_logic_vector (1 downto 0);
		oY   : out std_logic_vector(3 downto 0);
		oZERO: out std_logic
	);
end entity;

architecture ponasanje of zadatak is
	signal sPK : std_logic_vector (2 downto 0);
	signal sPK1: std_logic_vector (3 downto 0);
	signal sSAB: std_logic_vector (3 downto 0);
	signal sPOM: std_logic_vector (3 downto 0);
	signal sDEK: std_logic_vector (7 downto 0);
	signal sY  : std_logic_vector (3 downto 0);

begin

	--prioritetni koder
	process (iA,sPK) begin
		if   (iA(7)='1') then
			sPK <= "111";
		elsif(iA(6)='1') then
			sPK <= "110";
		elsif(iA(5)='1') then
			sPK <= "101";
		elsif(iA(4)='1') then
			sPK <= "100";
		elsif(iA(3)='1') then
			sPK <= "011";
		elsif(iA(2)='1') then
			sPK <= "010";
		elsif(iA(1)='1') then
			sPK <= "001";
			else sPK <= "000";
		end if;
	end process;

	--sabirac
		sPK1 <= '0' & sPK;
		sSAB <= sPK1 + iB;

	--pomerac
		sPOM <= '0' & '0' & sSAB(3 downto 2);

	--dekoder
	process(iB,sDEK) begin
		if   (iB(2 downto 0)="000") then
			sDEK <= "00000001";
		elsif(iB(2 downto 0)="001") then
			sDEK <= "00000010";
		elsif(iB(2 downto 0)="010") then
			sDEK <= "00000100";
		elsif(iB(2 downto 0)="011") then
			sDEK <= "00001000";
		elsif(iB(2 downto 0)="100") then
			sDEK <= "00010000";
		elsif(iB(2 downto 0)="101") then
			sDEK <= "00100000";
		elsif(iB(2 downto 0)="110") then
			sDEK <= "01000000";
		else sDEK <= "10000000";
		end if;
	end process;

	--MuX
	oY <= sSAB when iSEL <= "00" else
			sPOM when iSEL <= "01" else
			sDEK(7 downto 4) when iSEL <="10" else
			sDEK(3 downto 0);

	--komparator
	sY <= sSAB when iSEL <= "00" else
			sPOM when iSEL <= "01" else
			sDEK(7 downto 4) when iSEL <="10" else
			sDEK(3 downto 0);
	process(sY) begin
		if(sY <= "0000") then
			oZERO <= '1';
		else oZERO <= '0';
		end if;
	end process;

end architecture;