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CLK_4_MS

s4int Nov 15th, 2017 68 Never
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  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company:
  4. // Engineer:
  5. //
  6. // Create Date:    11:39:21 11/14/2017
  7. // Design Name:
  8. // Module Name:    CLK_4_MS
  9. // Project Name:
  10. // Target Devices:
  11. // Tool versions:
  12. // Description:
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module CLK_4_MS(
  22.     input CLK_IN, RST,
  23.     output CLK_OUT
  24.     );
  25.    
  26.     localparam HIGH = 1'b1, LOW = 1'b0;
  27.    
  28.     reg P_STATE, N_STATE;
  29.     reg [26'b0] CNT, CNT_NXT;
  30.  
  31.     assign CLK_OUT = P_STATE;
  32.    
  33.     always @ (posedge CLK, posedge RST)
  34.         begin
  35.             if (RST)
  36.                 begin
  37.                     P_STATE <= 0;
  38.                     CNT <= 26'b0;
  39.                 end
  40.             else
  41.                 begin
  42.                     CNT <= CNT_NXT;
  43.                     P_STATE <= N_STATE;
  44.                 end
  45.         end
  46.    
  47.     always @ (CNT)
  48.         begin
  49.             if (CNT >= 12500000)
  50.                 begin
  51.                     CNT_NXT = 0;
  52.                     N_STATE = ~P_STATE;
  53.                 end
  54.             else
  55.                 begin
  56.                     CNT_NXT = CNT + 1;
  57.                     N_STATE = P_STATE;
  58.                 end
  59.         end
  60. endmodule
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