CLK_4_MS

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:    11:39:21 11/14/2017
// Design Name:
// Module Name:    CLK_4_MS
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module CLK_4_MS(
	input CLK_IN, RST,
	output CLK_OUT
    );

	localparam HIGH = 1'b1, LOW = 1'b0;

	reg P_STATE, N_STATE;
	reg [26'b0] CNT, CNT_NXT;

	assign CLK_OUT = P_STATE;

	always @ (posedge CLK, posedge RST)
		begin
			if (RST)
				begin
					P_STATE <= 0;
					CNT <= 26'b0;
				end
			else
				begin
					CNT <= CNT_NXT;
					P_STATE <= N_STATE;
				end
		end

	always @ (CNT)
		begin
			if (CNT >= 12500000)
				begin
					CNT_NXT = 0;
					N_STATE = ~P_STATE;
				end
			else
				begin
					CNT_NXT = CNT + 1;
					N_STATE = P_STATE;
				end
		end
endmodule