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memory2port.sv

bobomarinov Jun 10th, 2019 102 Never
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  1. module memory2port(data_in1,
  2.            data_in2,
  3.            address1,
  4.            write_request1,
  5.            data_out1,
  6.            write_clk,
  7.            read_clk,
  8.            address2,
  9.            write_request2,
  10.            data_out2);
  11.    
  12.    parameter MEMORY_WIDTH = 4;
  13.    parameter MEMORY_LENGTH = 16;
  14.    parameter ADDRESS_SIZE = 4;
  15.  
  16.    input write_clk, read_clk;
  17.  
  18.    input [MEMORY_WIDTH - 1:0] data_in1;
  19.    input              write_request1;
  20.    output [MEMORY_WIDTH - 1:0] data_out1;
  21.  
  22.    input [MEMORY_WIDTH - 1:0]  data_in2;
  23.    input               write_request2;
  24.    output [MEMORY_WIDTH - 1:0] data_out2;  
  25.  
  26.    reg [MEMORY_WIDTH - 1:0]    memory [MEMORY_LENGTH - 1:0];
  27.    input [ADDRESS_SIZE - 1:0]  address1;
  28.    input [ADDRESS_SIZE - 1:0]  address2;
  29.  
  30.    reg [ADDRESS_SIZE - 1:0]    addr1; //memory length
  31.    reg [ADDRESS_SIZE - 1:0]    addr2;            
  32.  
  33.    assign data_out1 = memory[addr1];    
  34.    assign data_out2 = memory[addr2];   
  35.  
  36.    always@(posedge write_clk)begin //edin clk zakasnenie
  37.       addr1 <= address1;
  38.    end
  39.  
  40.    always@(posedge read_clk)begin //edin clk zakasnenie
  41.       addr2 <= address2;
  42.    end
  43.    
  44.    always@(posedge write_clk)begin
  45.       if(write_request1)begin    //write1  
  46.      memory[address1] <= data_in1;
  47.       end
  48.    end
  49.    always@(posedge read_clk)begin
  50.       if(write_request2)begin     //write2
  51.      memory[address2] <= data_in2;
  52.       end
  53.    end
  54. endmodule
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