memory2port.sv

module memory2port(data_in1,
           data_in2,
           address1,
           write_request1,
           data_out1,
           write_clk,
           read_clk,
           address2,
           write_request2,
           data_out2);

   parameter MEMORY_WIDTH = 4;
   parameter MEMORY_LENGTH = 16;
   parameter ADDRESS_SIZE = 4;

   input write_clk, read_clk;

   input [MEMORY_WIDTH - 1:0] data_in1;
   input              write_request1;
   output [MEMORY_WIDTH - 1:0] data_out1;

   input [MEMORY_WIDTH - 1:0]  data_in2;
   input               write_request2;
   output [MEMORY_WIDTH - 1:0] data_out2;

   reg [MEMORY_WIDTH - 1:0]    memory [MEMORY_LENGTH - 1:0];
   input [ADDRESS_SIZE - 1:0]  address1;
   input [ADDRESS_SIZE - 1:0]  address2;

   reg [ADDRESS_SIZE - 1:0]    addr1; //memory length
   reg [ADDRESS_SIZE - 1:0]    addr2;

   assign data_out1 = memory[addr1];
   assign data_out2 = memory[addr2];

   always@(posedge write_clk)begin //edin clk zakasnenie
      addr1 <= address1;
   end

   always@(posedge read_clk)begin //edin clk zakasnenie
      addr2 <= address2;
   end

   always@(posedge write_clk)begin
      if(write_request1)begin    //write1
     memory[address1] <= data_in1;
      end
   end
   always@(posedge read_clk)begin
      if(write_request2)begin     //write2
     memory[address2] <= data_in2;
      end
   end
endmodule