module zad4(
    input CLOCK_50,
    output [7:0] LEDR);

    timer(CLOCK_50,LEDR);

endmodule

module timer(
    input CLOCK,
    output reg [7:0] out);

    wire clk_0_1, clk_0_25, clk_0_5, clk_0_8, clk_1_2, clk_1_5, clk_1_8, clk_2_0;

    counter_to_make_delay0_1sek ex1(CLOCK,1, clk_0_1);
    counter_to_make_delay0_25sek ex2(CLOCK,1, clk_0_25);
    counter_to_make_delay0_5sek ex3(CLOCK,1, clk_0_5);
    counter_to_make_delay0_8sek ex4(CLOCK,1, clk_0_8);
    counter_to_make_delay1_2sek ex5(CLOCK,1, clk_1_2);
    counter_to_make_delay1_5sek ex6(CLOCK,1, clk_1_5);
    counter_to_make_delay1_8sek ex7(CLOCK,1, clk_1_8);
    counter_to_make_delay2sek ex8(CLOCK,1, clk_2_0);

    always@(posedge clk_0_1)
        if(clk_0_1)
            out[0]=~out[0];

    always@(posedge clk_0_25)
        if(clk_0_25)
            out[1]=~out[1];

    always@(posedge clk_0_5)
        if(clk_0_5)
            out[2]=~out[2];

    always@(posedge clk_0_8)
        if(clk_0_8)
            out[3]=~out[3];

    always@(posedge clk_1_2)
        if(clk_1_2)
            out[4]=~out[4];

    always@(posedge clk_1_5)
        if(clk_1_5)
            out[5]=~out[5];

    always@(posedge clk_1_8)
        if(clk_1_8)
            out[6]=~out[6];

    always@(posedge clk_2_0)
        if(clk_2_0)
            out[7]=~out[7];

endmodule

module counter_to_make_delay2sek(
    input clk, aclr,
    output reg clockTact);

    reg [28:0] i;

    always@(posedge clk, negedge aclr)
        if(!aclr)
            begin
                i<=0;
                clockTact<=0;
            end
        else
            begin
                if(i==100000000)
                    begin
                        i<=0;
                        clockTact<=1;
                    end
                else
                    begin
                        i<=i+1;
                        clockTact<=0;
                    end
            end

endmodule