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  1. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  2. no sdio debug board detected
  3.  
  4. BL2 Built : 20:03:32, Sep 23 2015.
  5. ver:5cf4fc5 - xiaobo.gu@droid05
  6.  
  7. Board ID = 1
  8. set vcck to 1100 mv
  9. set vddee to 1000 mv
  10. CPU clk: 1536MHz
  11. DDR channel setting: DDR0 Rank0+1 diff
  12. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  13. no sdio debug board detected
  14.  
  15. BL2 Built : 20:03:32, Sep 23 2015.
  16. ver:5cf4fc5 - xiaobo.gu@droid05
  17.  
  18. Board ID = 1
  19. set vcck to 1100 mv
  20. set vddee to 1000 mv
  21. CPU clk: 1536MHz
  22. DDR channel setting: DDR0 Rank0+1 diff
  23. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  24. no sdio debug board detected
  25.  
  26. BL2 Built : 20:03:32, Sep 23 2015.
  27. ver:5cf4fc5 - xiaobo.gu@droid05
  28.  
  29. Board ID = 1
  30. set vcck to 1100 mv
  31. set vddee to 1000 mv
  32. CPU clk: 1536MHz
  33. DDR channel setting: DDR0 Rank0+1 diff
  34. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  35. no sdio debug board detected
  36.  
  37. BL2 Built : 20:03:32, Sep 23 2015.
  38. ver:5cf4fc5 - xiaobo.gu@droid05
  39.  
  40. Board ID = 1
  41. set vcck to 1100 mv
  42. set vddee to 1000 mv
  43. CPU clk: 1536MHz
  44. DDR channel setting: DDR0 Rank0+1 diff
  45. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  46. no sdio debug board detected
  47.  
  48. BL2 Built : 20:03:32, Sep 23 2015.
  49. ver:5cf4fc5 - xiaobo.gu@droid05
  50.  
  51. Board ID = 1
  52. set vcck to 1100 mv
  53. set vddee to 1000 mv
  54. CPU clk: 1536MHz
  55. DDR channel setting: DDR0 Rank0+1 diff
  56. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  57. no sdio debug board detected
  58.  
  59. BL2 Built : 20:03:32, Sep 23 2015.
  60. ver:5cf4fc5 - xiaobo.gu@droid05
  61.  
  62. Board ID = 1
  63. set vcck to 1100 mv
  64. set vddee to 1000 mv
  65. CPU clk: 1536MHz
  66. DDR channel setting: DDR0 Rank0+1 diff
  67. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  68. no sdio debug board detected
  69.  
  70. BL2 Built : 20:03:32, Sep 23 2015.
  71. ver:5cf4fc5 - xiaobo.gu@droid05
  72.  
  73. Board ID = 1
  74. set vcck to 1100 mv
  75. set vddee to 1000 mv
  76. CPU clk: 1536MHz
  77. DDR channel setting: DDR0 Rank0+1 diff
  78. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  79. no sdio debug board detected
  80.  
  81. BL2 Built : 20:03:32, Sep 23 2015.
  82. ver:5cf4fc5 - xiaobo.gu@droid05
  83.  
  84. Board ID = 1
  85. set vcck to 1100 mv
  86. set vddee to 1000 mv
  87. CPU clk: 1536MHz
  88. DDR channel setting: DDR0 Rank0+1 diff
  89. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  90. no sdio debug board detected
  91.  
  92. BL2 Built : 20:03:32, Sep 23 2015.
  93. ver:5cf4fc5 - xiaobo.gu@droid05
  94.  
  95. Board ID = 1
  96. set vcck to 1100 mv
  97. set vddee to 1000 mv
  98. CPU clk: 1536MHz
  99. DDR channel setting: DDR0 Rank0+1 diff
  100. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  101. no sdio debug board detected
  102.  
  103. BL2 Built : 20:03:32, Sep 23 2015.
  104. ver:5cf4fc5 - xiaobo.gu@droid05
  105.  
  106. Board ID = 1
  107. set vcck to 1100 mv
  108. set vddee to 1000 mv
  109. CPU clk: 1536MHz
  110. DDR channel setting: DDR0 Rank0+1 diff
  111. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  112. no sdio debug board detected
  113.  
  114. BL2 Built : 20:03:32, Sep 23 2015.
  115. ver:5cf4fc5 - xiaobo.gu@droid05
  116.  
  117. Board ID = 1
  118. set vcck to 1100 mv
  119. set vddee to 1000 mv
  120. CPU clk: 1536MHz
  121. DDR channel setting: DDR0 Rank0+1 diff
  122. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  123. no sdio debug board detected
  124.  
  125. BL2 Built : 20:03:32, Sep 23 2015.
  126. ver:5cf4fc5 - xiaobo.gu@droid05
  127.  
  128. Board ID = 1
  129. set vcck to 1100 mv
  130. set vddee to 1000 mv
  131. CPU clk: 1536MHz
  132. DDR channel setting: DDR0 Rank0+1 diff
  133. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  134. no sdio debug board detected
  135.  
  136. BL2 Built : 20:03:32, Sep 23 2015.
  137. ver:5cf4fc5 - xiaobo.gu@droid05
  138.  
  139. Board ID = 1
  140. set vcck to 1100 mv
  141. set vddee to 1000 mv
  142. CPU clk: 1536MHz
  143. DDR channel setting: DDR0 Rank0+1 diff
  144. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  145. no sdio debug board detected
  146.  
  147. BL2 Built : 20:03:32, Sep 23 2015.
  148. ver:5cf4fc5 - xiaobo.gu@droid05
  149.  
  150. Board ID = 1
  151. set vcck to 1100 mv
  152. set vddee to 1000 mv
  153. CPU clk: 1536MHz
  154. DDR channel setting: DDR0 Rank0+1 diff
  155. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  156. no sdio debug board detected
  157.  
  158. BL2 Built : 20:03:32, Sep 23 2015.
  159. ver:5cf4fc5 - xiaobo.gu@droid05
  160.  
  161. Board ID = 1
  162. set vcck to 1100 mv
  163. set vddee to 1000 mv
  164. CPU clk: 1536MHz
  165. DDR channel setting: DDR0 Rank0+1 diff
  166. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  167. no sdio debug board detected
  168.  
  169. BL2 Built : 20:03:32, Sep 23 2015.
  170. ver:5cf4fc5 - xiaobo.gu@droid05
  171.  
  172. Board ID = 1
  173. set vcck to 1100 mv
  174. set vddee to 1000 mv
  175. CPU clk: 1536MHz
  176. DDR channel setting: DDR0 Rank0+1 diff
  177. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  178. no sdio debug board detected
  179.  
  180. BL2 Built : 20:03:32, Sep 23 2015.
  181. ver:5cf4fc5 - xiaobo.gu@droid05
  182.  
  183. Board ID = 1
  184. set vcck to 1100 mv
  185. set vddee to 1000 mv
  186. CPU clk: 1536MHz
  187. DDR channel setting: DDR0 Rank0+1 diff
  188. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  189. no sdio debug board detected
  190.  
  191. BL2 Built : 20:03:32, Sep 23 2015.
  192. ver:5cf4fc5 - xiaobo.gu@droid05
  193.  
  194. Board ID = 1
  195. set vcck to 1100 mv
  196. set vddee to 1000 mv
  197. CPU clk: 1536MHz
  198. DDR channel setting: DDR0 Rank0+1 diff
  199. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  200. no sdio debug board detected
  201.  
  202. BL2 Built : 20:03:32, Sep 23 2015.
  203. ver:5cf4fc5 - xiaobo.gu@droid05
  204.  
  205. Board ID = 1
  206. set vcck to 1100 mv
  207. set vddee to 1000 mv
  208. CPU clk: 1536MHz
  209. DDR channel setting: DDR0 Rank0+1 diff
  210. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  211. no sdio debug board detected
  212.  
  213. BL2 Built : 20:03:32, Sep 23 2015.
  214. ver:5cf4fc5 - xiaobo.gu@droid05
  215.  
  216. Board ID = 1
  217. set vcck to 1100 mv
  218. set vddee to 1000 mv
  219. CPU clk: 1536MHz
  220. DDR channel setting: DDR0 Rank0+1 diff
  221. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  222. no sdio debug board detected
  223.  
  224. BL2 Built : 20:03:32, Sep 23 2015.
  225. ver:5cf4fc5 - xiaobo.gu@droid05
  226.  
  227. Board ID = 1
  228. set vcck to 1100 mv
  229. set vddee to 1000 mv
  230. CPU clk: 1536MHz
  231. DDR channel setting: DDR0 Rank0+1 diff
  232. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  233. no sdio debug board detected
  234.  
  235. BL2 Built : 20:03:32, Sep 23 2015.
  236. ver:5cf4fc5 - xiaobo.gu@droid05
  237.  
  238. Board ID = 1
  239. set vcck to 1100 mv
  240. set vddee to 1000 mv
  241. CPU clk: 1536MHz
  242. DDR channel setting: DDR0 Rank0+1 diff
  243. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  244. no sdio debug board detected
  245.  
  246. BL2 Built : 20:03:32, Sep 23 2015.
  247. ver:5cf4fc5 - xiaobo.gu@droid05
  248.  
  249. Board ID = 1
  250. set vcck to 1100 mv
  251. set vddee to 1000 mv
  252. CPU clk: 1536MHz
  253. DDR channel setting: DDR0 Rank0+1 diff
  254. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  255. no sdio debug board detected
  256.  
  257. BL2 Built : 20:03:32, Sep 23 2015.
  258. ver:5cf4fc5 - xiaobo.gu@droid05
  259.  
  260. Board ID = 1
  261. set vcck to 1100 mv
  262. set vddee to 1000 mv
  263. CPU clk: 1536MHz
  264. DDR channel setting: DDR0 Rank0+1 diff
  265. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  266. no sdio debug board detected
  267.  
  268. BL2 Built : 20:03:32, Sep 23 2015.
  269. ver:5cf4fc5 - xiaobo.gu@droid05
  270.  
  271. Board ID = 1
  272. set vcck to 1100 mv
  273. set vddee to 1000 mv
  274. CPU clk: 1536MHz
  275. DDR channel setting: DDR0 Rank0+1 diff
  276. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  277. no sdio debug board detected
  278.  
  279. BL2 Built : 20:03:32, Sep 23 2015.
  280. ver:5cf4fc5 - xiaobo.gu@droid05
  281.  
  282. Board ID = 1
  283. set vcck to 1100 mv
  284. set vddee to 1000 mv
  285. CPU clk: 1536MHz
  286. DDR channel setting: DDR0 Rank0+1 diff
  287. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  288. no sdio debug board detected
  289.  
  290. BL2 Built : 20:03:32, Sep 23 2015.
  291. ver:5cf4fc5 - xiaobo.gu@droid05
  292.  
  293. Board ID = 1
  294. set vcck to 1100 mv
  295. set vddee to 1000 mv
  296. CPU clk: 1536MHz
  297. DDR channel setting: DDR0 Rank0+1 diff
  298. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  299. no sdio debug board detected
  300.  
  301. BL2 Built : 20:03:32, Sep 23 2015.
  302. ver:5cf4fc5 - xiaobo.gu@droid05
  303.  
  304. Board ID = 1
  305. set vcck to 1100 mv
  306. set vddee to 1000 mv
  307. CPU clk: 1536MHz
  308. DDR channel setting: DDR0 Rank0+1 diff
  309. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  310. no sdio debug board detected
  311.  
  312. BL2 Built : 20:03:32, Sep 23 2015.
  313. ver:5cf4fc5 - xiaobo.gu@droid05
  314.  
  315. Board ID = 1
  316. set vcck to 1100 mv
  317. set vddee to 1000 mv
  318. CPU clk: 1536MHz
  319. DDR channel setting: DDR0 Rank0+1 diff
  320. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  321. no sdio debug board detected
  322.  
  323. BL2 Built : 20:03:32, Sep 23 2015.
  324. ver:5cf4fc5 - xiaobo.gu@droid05
  325.  
  326. Board ID = 1
  327. set vcck to 1100 mv
  328. set vddee to 1000 mv
  329. CPU clk: 1536MHz
  330. DDR channel setting: DDR0 Rank0+1 diff
  331. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  332. no sdio debug board detected
  333.  
  334. BL2 Built : 20:03:32, Sep 23 2015.
  335. ver:5cf4fc5 - xiaobo.gu@droid05
  336.  
  337. Board ID = 1
  338. set vcck to 1100 mv
  339. set vddee to 1000 mv
  340. CPU clk: 1536MHz
  341. DDR channel setting: DDR0 Rank0+1 diff
  342. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  343. no sdio debug board detected
  344.  
  345. BL2 Built : 20:03:32, Sep 23 2015.
  346. ver:5cf4fc5 - xiaobo.gu@droid05
  347.  
  348. Board ID = 1
  349. set vcck to 1100 mv
  350. set vddee to 1000 mv
  351. CPU clk: 1536MHz
  352. DDR channel setting: DDR0 Rank0+1 diff
  353. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  354. no sdio debug board detected
  355.  
  356. BL2 Built : 20:03:32, Sep 23 2015.
  357. ver:5cf4fc5 - xiaobo.gu@droid05
  358.  
  359. Board ID = 1
  360. set vcck to 1100 mv
  361. set vddee to 1000 mv
  362. CPU clk: 1536MHz
  363. DDR channel setting: DDR0 Rank0+1 diff
  364. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  365. no sdio debug board detected
  366.  
  367. BL2 Built : 20:03:32, Sep 23 2015.
  368. ver:5cf4fc5 - xiaobo.gu@droid05
  369.  
  370. Board ID = 1
  371. set vcck to 1100 mv
  372. set vddee to 1000 mv
  373. CPU clk: 1536MHz
  374. DDR channel setting: DDR0 Rank0+1 diff
  375. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  376. no sdio debug board detected
  377.  
  378. BL2 Built : 20:03:32, Sep 23 2015.
  379. ver:5cf4fc5 - xiaobo.gu@droid05
  380.  
  381. Board ID = 1
  382. set vcck to 1100 mv
  383. set vddee to 1000 mv
  384. CPU clk: 1536MHz
  385. DDR channel setting: DDR0 Rank0+1 diff
  386. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  387. no sdio debug board detected
  388.  
  389. BL2 Built : 20:03:32, Sep 23 2015.
  390. ver:5cf4fc5 - xiaobo.gu@droid05
  391.  
  392. Board ID = 1
  393. set vcck to 1100 mv
  394. set vddee to 1000 mv
  395. CPU clk: 1536MHz
  396. DDR channel setting: DDR0 Rank0+1 diff
  397. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  398. no sdio debug board detected
  399.  
  400. BL2 Built : 20:03:32, Sep 23 2015.
  401. ver:5cf4fc5 - xiaobo.gu@droid05
  402.  
  403. Board ID = 1
  404. set vcck to 1100 mv
  405. set vddee to 1000 mv
  406. CPU clk: 1536MHz
  407. DDR channel setting: DDR0 Rank0+1 diff
  408. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  409. no sdio debug board detected
  410.  
  411. BL2 Built : 20:03:32, Sep 23 2015.
  412. ver:5cf4fc5 - xiaobo.gu@droid05
  413.  
  414. Board ID = 1
  415. set vcck to 1100 mv
  416. set vddee to 1000 mv
  417. CPU clk: 1536MHz
  418. DDR channel setting: DDR0 Rank0+1 diff
  419. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  420. no sdio debug board detected
  421.  
  422. BL2 Built : 20:03:32, Sep 23 2015.
  423. ver:5cf4fc5 - xiaobo.gu@droid05
  424.  
  425. Board ID = 1
  426. set vcck to 1100 mv
  427. set vddee to 1000 mv
  428. CPU clk: 1536MHz
  429. DDR channel setting: DDR0 Rank0+1 diff
  430. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  431. no sdio debug board detected
  432.  
  433. BL2 Built : 20:03:32, Sep 23 2015.
  434. ver:5cf4fc5 - xiaobo.gu@droid05
  435.  
  436. Board ID = 1
  437. set vcck to 1100 mv
  438. set vddee to 1000 mv
  439. CPU clk: 1536MHz
  440. DDR channel setting: DDR0 Rank0+1 diff
  441. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  442. no sdio debug board detected
  443.  
  444. BL2 Built : 20:03:32, Sep 23 2015.
  445. ver:5cf4fc5 - xiaobo.gu@droid05
  446.  
  447. Board ID = 1
  448. set vcck to 1100 mv
  449. set vddee to 1000 mv
  450. CPU clk: 1536MHz
  451. DDR channel setting: DDR0 Rank0+1 diff
  452. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  453. no sdio debug board detected
  454.  
  455. BL2 Built : 20:03:32, Sep 23 2015.
  456. ver:5cf4fc5 - xiaobo.gu@droid05
  457.  
  458. Board ID = 1
  459. set vcck to 1100 mv
  460. set vddee to 1000 mv
  461. CPU clk: 1536MHz
  462. DDR channel setting: DDR0 Rank0+1 diff
  463. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  464. no sdio debug board detected
  465.  
  466. BL2 Built : 20:03:32, Sep 23 2015.
  467. ver:5cf4fc5 - xiaobo.gu@droid05
  468.  
  469. Board ID = 1
  470. set vcck to 1100 mv
  471. set vddee to 1000 mv
  472. CPU clk: 1536MHz
  473. DDR channel setting: DDR0 Rank0+1 diff
  474. GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
  475. no sdio debug board detected
  476.  
  477. BL2 Built : 20:03:32, Sep 23 2015.
  478. ver:5cf4fc5 - xiaobo.gu@droid05
  479.  
  480. Board ID = 1
  481. set vcck to 1100 mv
  482. set vddee to 1000 mv
  483. CPU clk: 1536MHz
  484. DDR channel setting: DDR0 Rank0+1 diff
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