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- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
- GXBB:BL1:08dafd:0a8993;FEAT:EDFC318C;POC:3;RCY:0;EMMC:0;READ:0;CHK:0;
- no sdio debug board detected
- BL2 Built : 20:03:32, Sep 23 2015.
- ver:5cf4fc5 - xiaobo.gu@droid05
- Board ID = 1
- set vcck to 1100 mv
- set vddee to 1000 mv
- CPU clk: 1536MHz
- DDR channel setting: DDR0 Rank0+1 diff
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